IT1263830B - Circuito di generazione di impulsi per dispositivi a semiconduttore - Google Patents
Circuito di generazione di impulsi per dispositivi a semiconduttoreInfo
- Publication number
- IT1263830B IT1263830B ITMI930132A ITMI930132A IT1263830B IT 1263830 B IT1263830 B IT 1263830B IT MI930132 A ITMI930132 A IT MI930132A IT MI930132 A ITMI930132 A IT MI930132A IT 1263830 B IT1263830 B IT 1263830B
- Authority
- IT
- Italy
- Prior art keywords
- type mos
- mos transistors
- level
- generation circuit
- pulse generation
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
- H03K3/356—Bistable circuits
- H03K3/356104—Bistable circuits using complementary field-effect transistors
- H03K3/356113—Bistable circuits using complementary field-effect transistors using additional transistors in the input circuit
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/18—Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/4076—Timing circuits
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
- H03K19/018507—Interface arrangements
- H03K19/018521—Interface arrangements of complementary type, e.g. CMOS
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/153—Arrangements in which a pulse is delivered at the instant when a predetermined characteristic of an input signal is present or at a fixed time interval after this instant
- H03K5/1534—Transition or edge detectors
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Dram (AREA)
- Manipulation Of Pulses (AREA)
Abstract
La presente invenzione è diretta ad un circuito di generazione di impulsi da impiegare in un dispositivo a semiconduttore in cui transistor MOS di tipo P (6, 7) sono collegati in parallelo, transistor (16, 17 e 18, 19) MOS di tipo N collegati in serie sono collegati in serie ai transistor MOS di tipo P (6, 7) in modo in parallelo, il potenziale di un nodo (N1) è fornito a transistor MOS di tipo P (7) ed ai transistor MOS di tipo N (16, 19), mentre il potenziale di un nodo (N2) è fornito al transistor MOS (6) di tipo P ed ai transistor MOS di tipo N (17, 18), in modo tale che un impulso monostabile o schottky avente una forma: d'onda sostanzialmente identica può essere generato o quando un segnale d'orologio di ingresso ?IN varia il suo livello da un livello "H" ad un livello "L" o dal livello "L" al livello "H".
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP01636292A JP3228985B2 (ja) | 1992-01-31 | 1992-01-31 | パルス発生回路 |
Publications (3)
Publication Number | Publication Date |
---|---|
ITMI930132A0 ITMI930132A0 (it) | 1993-01-27 |
ITMI930132A1 ITMI930132A1 (it) | 1994-07-27 |
IT1263830B true IT1263830B (it) | 1996-09-04 |
Family
ID=11914227
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
ITMI930132A IT1263830B (it) | 1992-01-31 | 1993-01-27 | Circuito di generazione di impulsi per dispositivi a semiconduttore |
Country Status (5)
Country | Link |
---|---|
US (1) | US5304857A (it) |
JP (1) | JP3228985B2 (it) |
KR (1) | KR960002822B1 (it) |
DE (1) | DE4302224C2 (it) |
IT (1) | IT1263830B (it) |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3331032A (en) * | 1966-03-15 | 1967-07-11 | Motorola Inc | Voltage controlled oscillator operative in the monostable, astable or gated mode |
US3668423A (en) * | 1971-03-18 | 1972-06-06 | Gte Automatic Electric Lab Inc | Logic circuit delay system comprising monostable means for providing different time delays for positive and negative transitions |
US4370569A (en) * | 1980-10-30 | 1983-01-25 | Hewlett-Packard Company | Integratable single pulse circuit |
JPS62202616A (ja) * | 1986-02-28 | 1987-09-07 | Sharp Corp | 論理回路 |
US4808840A (en) * | 1987-11-20 | 1989-02-28 | International Business Machines Corporation | Dynamic edge-triggered latch |
JPH03205912A (ja) * | 1989-10-16 | 1991-09-09 | Fujitsu Ltd | トリガパルス発生回路 |
-
1992
- 1992-01-31 JP JP01636292A patent/JP3228985B2/ja not_active Expired - Fee Related
-
1993
- 1993-01-26 US US08/009,178 patent/US5304857A/en not_active Expired - Lifetime
- 1993-01-26 KR KR1019930000940A patent/KR960002822B1/ko not_active IP Right Cessation
- 1993-01-27 IT ITMI930132A patent/IT1263830B/it active IP Right Grant
- 1993-01-27 DE DE4302224A patent/DE4302224C2/de not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
DE4302224C2 (de) | 1994-06-09 |
JP3228985B2 (ja) | 2001-11-12 |
US5304857A (en) | 1994-04-19 |
DE4302224A1 (it) | 1993-08-05 |
JPH05218818A (ja) | 1993-08-27 |
ITMI930132A0 (it) | 1993-01-27 |
KR960002822B1 (ko) | 1996-02-26 |
ITMI930132A1 (it) | 1994-07-27 |
KR930017032A (ko) | 1993-08-30 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
0001 | Granted | ||
TA | Fee payment date (situation as of event date), data collected since 19931001 |
Effective date: 19960126 |