ITMI930132A1 - Circuito di generazione di impulsi per dispositivi a semiconduttore - Google Patents

Circuito di generazione di impulsi per dispositivi a semiconduttore

Info

Publication number
ITMI930132A1
ITMI930132A1 IT000132A ITMI930132A ITMI930132A1 IT MI930132 A1 ITMI930132 A1 IT MI930132A1 IT 000132 A IT000132 A IT 000132A IT MI930132 A ITMI930132 A IT MI930132A IT MI930132 A1 ITMI930132 A1 IT MI930132A1
Authority
IT
Italy
Prior art keywords
generation circuit
semiconductor devices
pulse generation
pulse
semiconductor
Prior art date
Application number
IT000132A
Other languages
English (en)
Inventor
Kenji Tokami
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Publication of ITMI930132A0 publication Critical patent/ITMI930132A0/it
Publication of ITMI930132A1 publication Critical patent/ITMI930132A1/it
Application granted granted Critical
Publication of IT1263830B publication Critical patent/IT1263830B/it

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K3/00Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356Bistable circuits
    • H03K3/356104Bistable circuits using complementary field-effect transistors
    • H03K3/356113Bistable circuits using complementary field-effect transistors using additional transistors in the input circuit
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C8/00Arrangements for selecting an address in a digital store
    • G11C8/18Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076Timing circuits
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175Coupling arrangements; Interface arrangements
    • H03K19/0185Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507Interface arrangements
    • H03K19/018521Interface arrangements of complementary type, e.g. CMOS
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K5/00Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/153Arrangements in which a pulse is delivered at the instant when a predetermined characteristic of an input signal is present or at a fixed time interval after this instant
    • H03K5/1534Transition or edge detectors

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Dram (AREA)
  • Manipulation Of Pulses (AREA)
ITMI930132A 1992-01-31 1993-01-27 Circuito di generazione di impulsi per dispositivi a semiconduttore IT1263830B (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP01636292A JP3228985B2 (ja) 1992-01-31 1992-01-31 パルス発生回路

Publications (3)

Publication Number Publication Date
ITMI930132A0 ITMI930132A0 (it) 1993-01-27
ITMI930132A1 true ITMI930132A1 (it) 1994-07-27
IT1263830B IT1263830B (it) 1996-09-04

Family

ID=11914227

Family Applications (1)

Application Number Title Priority Date Filing Date
ITMI930132A IT1263830B (it) 1992-01-31 1993-01-27 Circuito di generazione di impulsi per dispositivi a semiconduttore

Country Status (5)

Country Link
US (1) US5304857A (it)
JP (1) JP3228985B2 (it)
KR (1) KR960002822B1 (it)
DE (1) DE4302224C2 (it)
IT (1) IT1263830B (it)

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3331032A (en) * 1966-03-15 1967-07-11 Motorola Inc Voltage controlled oscillator operative in the monostable, astable or gated mode
US3668423A (en) * 1971-03-18 1972-06-06 Gte Automatic Electric Lab Inc Logic circuit delay system comprising monostable means for providing different time delays for positive and negative transitions
US4370569A (en) * 1980-10-30 1983-01-25 Hewlett-Packard Company Integratable single pulse circuit
JPS62202616A (ja) * 1986-02-28 1987-09-07 Sharp Corp 論理回路
US4808840A (en) * 1987-11-20 1989-02-28 International Business Machines Corporation Dynamic edge-triggered latch
JPH03205912A (ja) * 1989-10-16 1991-09-09 Fujitsu Ltd トリガパルス発生回路

Also Published As

Publication number Publication date
DE4302224C2 (de) 1994-06-09
JP3228985B2 (ja) 2001-11-12
US5304857A (en) 1994-04-19
IT1263830B (it) 1996-09-04
DE4302224A1 (it) 1993-08-05
JPH05218818A (ja) 1993-08-27
ITMI930132A0 (it) 1993-01-27
KR960002822B1 (ko) 1996-02-26
KR930017032A (ko) 1993-08-30

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Legal Events

Date Code Title Description
0001 Granted
TA Fee payment date (situation as of event date), data collected since 19931001

Effective date: 19960126