IT1251074B - Procedimento per produrre un dispositivo cmos bipolare - Google Patents

Procedimento per produrre un dispositivo cmos bipolare

Info

Publication number
IT1251074B
IT1251074B ITMI911906A ITMI911906A IT1251074B IT 1251074 B IT1251074 B IT 1251074B IT MI911906 A ITMI911906 A IT MI911906A IT MI911906 A ITMI911906 A IT MI911906A IT 1251074 B IT1251074 B IT 1251074B
Authority
IT
Italy
Prior art keywords
transistor
self
cmos device
bipolar
aligned
Prior art date
Application number
ITMI911906A
Other languages
English (en)
Inventor
Myungsung Kim
Soon-Kwon Lim
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of ITMI911906A0 publication Critical patent/ITMI911906A0/it
Publication of ITMI911906A1 publication Critical patent/ITMI911906A1/it
Application granted granted Critical
Publication of IT1251074B publication Critical patent/IT1251074B/it

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8248Combination of bipolar and field-effect technology
    • H01L21/8249Bipolar and MOS technology
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28575Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising AIIIBV compounds
    • H01L21/28581Deposition of Schottky electrodes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8222Bipolar technology
    • H01L21/8228Complementary devices, e.g. complementary transistors
    • H01L21/82285Complementary vertical transistors
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00Metal treatment
    • Y10S148/009Bi-MOS

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Bipolar Transistors (AREA)

Abstract

Procedimento per produrre un dispositivo CMOS bipolare per comprendere un transistor CMOS unipolare con una porta di polisilicio e un transistor NPN e VPNP auto-allineati su uno stesso chip. Un dispositivo CMOS bipolare prodotto secondo la presente invenzione è superiore ad un dispositivo non autoallineato in velocità operativa e densità integrata mediante autoallineamento di un transistor NPN bipolare e un transistor VPNP. Inoltre, un dispositivo CMOS con una porta di silicio e un transistor NPN e VPNP auto-allineati è integrato su uno stesso chip di modo che è possibile realizzare un dispositivo BiCMOS analogico e digitale con elevate prestazioni.
ITMI911906A 1991-02-25 1991-07-09 Procedimento per produrre un dispositivo cmos bipolare IT1251074B (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019910003021A KR940003589B1 (ko) 1991-02-25 1991-02-25 BiCMOS 소자의 제조 방법

Publications (3)

Publication Number Publication Date
ITMI911906A0 ITMI911906A0 (it) 1991-07-09
ITMI911906A1 ITMI911906A1 (it) 1993-01-09
IT1251074B true IT1251074B (it) 1995-05-04

Family

ID=19311461

Family Applications (1)

Application Number Title Priority Date Filing Date
ITMI911906A IT1251074B (it) 1991-02-25 1991-07-09 Procedimento per produrre un dispositivo cmos bipolare

Country Status (7)

Country Link
US (1) US5132234A (it)
JP (1) JPH04278576A (it)
KR (1) KR940003589B1 (it)
DE (1) DE4123434A1 (it)
FR (1) FR2673324A1 (it)
GB (1) GB2253091A (it)
IT (1) IT1251074B (it)

Families Citing this family (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3282172B2 (ja) * 1994-07-29 2002-05-13 ソニー株式会社 BiMOS半導体装置の製造方法
US5273914A (en) * 1988-10-14 1993-12-28 Matsushita Electric Industrial Co., Ltd. Method of fabricating a CMOS semiconductor devices
US5169794A (en) * 1991-03-22 1992-12-08 National Semiconductor Corporation Method of fabrication of pnp structure in a common substrate containing npn or MOS structures
JPH0529329A (ja) * 1991-07-24 1993-02-05 Canon Inc 半導体装置の製造方法
WO1993016494A1 (en) * 1992-01-31 1993-08-19 Analog Devices, Inc. Complementary bipolar polysilicon emitter devices
US5352617A (en) * 1992-04-27 1994-10-04 Sony Corporation Method for manufacturing Bi-CMOS transistor devices
US5648281A (en) * 1992-09-21 1997-07-15 Siliconix Incorporated Method for forming an isolation structure and a bipolar transistor on a semiconductor substrate
US5374569A (en) * 1992-09-21 1994-12-20 Siliconix Incorporated Method for forming a BiCDMOS
US5559044A (en) * 1992-09-21 1996-09-24 Siliconix Incorporated BiCDMOS process technology
JP2886420B2 (ja) * 1992-10-23 1999-04-26 三菱電機株式会社 半導体装置の製造方法
US6249030B1 (en) * 1992-12-07 2001-06-19 Hyundai Electronics Industries Co., Ltd. BI-CMOS integrated circuit
US5488003A (en) * 1993-03-31 1996-01-30 Intel Corporation Method of making emitter trench BiCMOS using integrated dual layer emitter mask
JPH07106452A (ja) * 1993-10-04 1995-04-21 Mitsubishi Electric Corp 半導体装置およびその製造方法
US5395799A (en) * 1993-10-04 1995-03-07 At&T Corp. Method of fabricating semiconductor devices having electrodes comprising layers of doped tungsten disilicide
US5439833A (en) * 1994-03-15 1995-08-08 National Semiconductor Corp. Method of making truly complementary and self-aligned bipolar and CMOS transistor structures with minimized base and gate resistances and parasitic capacitance
US5462888A (en) * 1994-06-06 1995-10-31 At&T Ipm Corp. Process for manufacturing semiconductor BICMOS device
US6445043B1 (en) 1994-11-30 2002-09-03 Agere Systems Isolated regions in an integrated circuit
WO1996030940A2 (en) * 1995-03-28 1996-10-03 Philips Electronics N.V. METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE WITH BiCMOS CIRCUIT
US5702959A (en) * 1995-05-31 1997-12-30 Texas Instruments Incorporated Method for making an isolated vertical transistor
JP2776350B2 (ja) * 1995-12-18 1998-07-16 日本電気株式会社 半導体集積回路装置の製造方法
US6245604B1 (en) * 1996-01-16 2001-06-12 Micron Technology Bipolar-CMOS (BiCMOS) process for fabricating integrated circuits
US5681765A (en) * 1996-10-28 1997-10-28 National Semiconductor Corporation Process for fabricating single polysilicon high performance BICMOS
US5766990A (en) * 1997-08-08 1998-06-16 National Semiconductor Corporation Method of manufacturing a high speed bipolar transistor in a CMOS process
US6611044B2 (en) 1998-09-11 2003-08-26 Koninklijke Philips Electronics N.V. Lateral bipolar transistor and method of making same
US6245607B1 (en) 1998-12-28 2001-06-12 Industrial Technology Research Institute Buried channel quasi-unipolar transistor
JP2001203288A (ja) * 2000-01-20 2001-07-27 Mitsubishi Electric Corp 半導体装置の製造方法
US7927948B2 (en) 2005-07-20 2011-04-19 Micron Technology, Inc. Devices with nanocrystals and methods of formation
US9722041B2 (en) 2012-09-19 2017-08-01 Vishay-Siliconix Breakdown voltage blocking device

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63239856A (ja) * 1987-03-27 1988-10-05 Hitachi Ltd 半導体集積回路装置及びその製造方法
US4784966A (en) * 1987-06-02 1988-11-15 Texas Instruments Incorporated Self-aligned NPN bipolar transistor built in a double polysilicon CMOS technology
JPS63311753A (ja) * 1987-06-15 1988-12-20 Sanyo Electric Co Ltd 半導体集積回路の製造方法
US4855244A (en) * 1987-07-02 1989-08-08 Texas Instruments Incorporated Method of making vertical PNP transistor in merged bipolar/CMOS technology
ATE98815T1 (de) * 1988-01-21 1994-01-15 Exar Corp Verfahren zum herstellen eines komplementaeren bicmos-transistors mit isoliertem vertikalem pnp- transistor.
US4868135A (en) * 1988-12-21 1989-09-19 International Business Machines Corporation Method for manufacturing a Bi-CMOS device
US5047357A (en) * 1989-02-03 1991-09-10 Texas Instruments Incorporated Method for forming emitters in a BiCMOS process
US4951115A (en) * 1989-03-06 1990-08-21 International Business Machines Corp. Complementary transistor structure and method for manufacture
US4902639A (en) * 1989-08-03 1990-02-20 Motorola, Inc. Process for making BiCMOS integrated circuit having a shallow trench bipolar transistor with vertical base contacts
US4987089A (en) * 1990-07-23 1991-01-22 Micron Technology, Inc. BiCMOS process and process for forming bipolar transistors on wafers also containing FETs

Also Published As

Publication number Publication date
US5132234A (en) 1992-07-21
DE4123434A1 (de) 1992-09-24
GB9115286D0 (en) 1991-08-28
KR920017274A (ko) 1992-09-26
GB2253091A (en) 1992-08-26
FR2673324A1 (fr) 1992-08-28
ITMI911906A0 (it) 1991-07-09
KR940003589B1 (ko) 1994-04-25
JPH04278576A (ja) 1992-10-05
ITMI911906A1 (it) 1993-01-09

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Legal Events

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0001 Granted
TA Fee payment date (situation as of event date), data collected since 19931001

Effective date: 19970731