JPS6425454A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS6425454A JPS6425454A JP62181497A JP18149787A JPS6425454A JP S6425454 A JPS6425454 A JP S6425454A JP 62181497 A JP62181497 A JP 62181497A JP 18149787 A JP18149787 A JP 18149787A JP S6425454 A JPS6425454 A JP S6425454A
- Authority
- JP
- Japan
- Prior art keywords
- type
- layer
- collector
- transistor
- well region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title abstract 2
- 239000000758 substrate Substances 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/082—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including bipolar components only
- H01L27/0823—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including bipolar components only including vertical bipolar transistors only
- H01L27/0826—Combination of vertical complementary transistors
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Bipolar Transistors (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Bipolar Integrated Circuits (AREA)
Abstract
PURPOSE:To accelerate the operation of a transistor by forming an NPN transistor in such a manner that its shallow N-type well is used as a collector and a PNP transistor on an N<+> type buried layer in such a manner that the P<+> type buried layer is used as a collector. CONSTITUTION:A deep N<+> type buried layer 2 and a shallow N<+> type buried layer 3 are formed on a P<-> type semiconductor substrate 1, P<+> type buried layers 4a, 4b are formed, and N-type well regions 6b, 6c and a P-type well region 7 are formed on the layers 3, 4a, 4b. A P-type active base layer 10, and an N<+> type collector wall layer 9, an N<+> type emitter layer 14 and a P<+> type base layer 13 are formed in a well region 6b to construct an NPN transistor. A P<+> type emitter layer 13, an N<+> type base contact layer 14 and a P<+> type collector contact layer 13 are formed on a well region 6c to construct a PNP transistor. According to this configuration, both the transistors can be reduced at its collector series resistance to be accelerated in its operation.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62181497A JP2537886B2 (en) | 1987-07-21 | 1987-07-21 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62181497A JP2537886B2 (en) | 1987-07-21 | 1987-07-21 | Semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS6425454A true JPS6425454A (en) | 1989-01-27 |
JP2537886B2 JP2537886B2 (en) | 1996-09-25 |
Family
ID=16101792
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP62181497A Expired - Fee Related JP2537886B2 (en) | 1987-07-21 | 1987-07-21 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2537886B2 (en) |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61236153A (en) * | 1985-04-12 | 1986-10-21 | Hitachi Ltd | Semiconductor device |
-
1987
- 1987-07-21 JP JP62181497A patent/JP2537886B2/en not_active Expired - Fee Related
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61236153A (en) * | 1985-04-12 | 1986-10-21 | Hitachi Ltd | Semiconductor device |
Also Published As
Publication number | Publication date |
---|---|
JP2537886B2 (en) | 1996-09-25 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
LAPS | Cancellation because of no payment of annual fees |