IT1153577B - Procedimento per definire particolari di dimensioni submicroniche in dispositivi a semiconduttori - Google Patents

Procedimento per definire particolari di dimensioni submicroniche in dispositivi a semiconduttori

Info

Publication number
IT1153577B
IT1153577B IT23909/82A IT2390982A IT1153577B IT 1153577 B IT1153577 B IT 1153577B IT 23909/82 A IT23909/82 A IT 23909/82A IT 2390982 A IT2390982 A IT 2390982A IT 1153577 B IT1153577 B IT 1153577B
Authority
IT
Italy
Prior art keywords
procedure
semiconductor devices
defining details
submicronic dimensions
submicronic
Prior art date
Application number
IT23909/82A
Other languages
English (en)
Other versions
IT8223909A0 (it
Inventor
Rafael Matityahu Levin
Original Assignee
Western Electric Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Western Electric Co filed Critical Western Electric Co
Publication of IT8223909A0 publication Critical patent/IT8223909A0/it
Application granted granted Critical
Publication of IT1153577B publication Critical patent/IT1153577B/it

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/872—Schottky diodes
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/942—Masking
    • Y10S438/944—Shadow
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/942—Masking
    • Y10S438/947—Subphotolithographic processing

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Manufacturing & Machinery (AREA)
  • Toxicology (AREA)
  • Health & Medical Sciences (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Ceramic Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Drying Of Semiconductors (AREA)
  • Weting (AREA)
IT23909/82A 1981-10-28 1982-10-25 Procedimento per definire particolari di dimensioni submicroniche in dispositivi a semiconduttori IT1153577B (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/315,757 US4441931A (en) 1981-10-28 1981-10-28 Method of making self-aligned guard regions for semiconductor device elements

Publications (2)

Publication Number Publication Date
IT8223909A0 IT8223909A0 (it) 1982-10-25
IT1153577B true IT1153577B (it) 1987-01-14

Family

ID=23225928

Family Applications (1)

Application Number Title Priority Date Filing Date
IT23909/82A IT1153577B (it) 1981-10-28 1982-10-25 Procedimento per definire particolari di dimensioni submicroniche in dispositivi a semiconduttori

Country Status (9)

Country Link
US (1) US4441931A (it)
JP (1) JPS5884432A (it)
BE (1) BE894797A (it)
CA (1) CA1186809A (it)
DE (1) DE3239819A1 (it)
FR (1) FR2515425B1 (it)
GB (1) GB2108759B (it)
IT (1) IT1153577B (it)
NL (1) NL8204152A (it)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5950567A (ja) * 1982-09-16 1984-03-23 Hitachi Ltd 電界効果トランジスタの製造方法
JPS60201666A (ja) * 1984-03-27 1985-10-12 Nec Corp 半導体装置
DE3576766D1 (de) * 1984-10-26 1990-04-26 Siemens Ag Schottky-kontakt auf einer halbleiteroberflaeche und verfahren zu dessen herstellung.
US4655875A (en) * 1985-03-04 1987-04-07 Hitachi, Ltd. Ion implantation process
US4712291A (en) * 1985-06-06 1987-12-15 The United States Of America As Represented By The Secretary Of The Air Force Process of fabricating TiW/Si self-aligned gate for GaAs MESFETs
US4669178A (en) * 1986-05-23 1987-06-02 International Business Machines Corporation Process for forming a self-aligned low resistance path in semiconductor devices
US5141891A (en) * 1988-11-09 1992-08-25 Mitsubishi Denki Kabushiki Kaisha MIS-type semiconductor device of LDD structure and manufacturing method thereof
US5120668A (en) * 1991-07-10 1992-06-09 Ibm Corporation Method of forming an inverse T-gate FET transistor
US6040222A (en) * 1999-02-02 2000-03-21 United Microelectronics Corp. Method for fabricating an electrostatistic discharge protection device to protect an integrated circuit
US6514840B2 (en) * 1999-04-13 2003-02-04 International Business Machines Corporation Micro heating of selective regions
US6699775B2 (en) * 2000-02-22 2004-03-02 International Rectifier Corporation Manufacturing process for fast recovery diode
US20060022291A1 (en) * 2004-07-28 2006-02-02 Vladimir Drobny Unguarded schottky diodes with sidewall spacer at the perimeter of the diode
US8901699B2 (en) 2005-05-11 2014-12-02 Cree, Inc. Silicon carbide junction barrier Schottky diodes with suppressed minority carrier injection
JP2011129619A (ja) * 2009-12-16 2011-06-30 Toyota Motor Corp 半導体装置の製造方法
JP5726330B2 (ja) * 2011-01-07 2015-05-27 ユニバーシティー オブ カルカッタ ３次元物体の保護区域を計算するように構成された方法およびシステム

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3920861A (en) * 1972-12-18 1975-11-18 Rca Corp Method of making a semiconductor device
DE2432719B2 (de) * 1974-07-08 1977-06-02 Siemens AG, 1000 Berlin und 8000 München Verfahren zum erzeugen von feinen strukturen aus aufdampfbaren materialien auf einer unterlage und anwendung des verfahrens
US4037307A (en) * 1975-03-21 1977-07-26 Bell Telephone Laboratories, Incorporated Methods for making transistor structures
US4026740A (en) * 1975-10-29 1977-05-31 Intel Corporation Process for fabricating narrow polycrystalline silicon members
JPS5263680A (en) * 1975-11-19 1977-05-26 Matsushita Electric Ind Co Ltd Production of semiconductor device
JPS5819129B2 (ja) * 1975-12-10 1983-04-16 株式会社東芝 ハンドウタイソウチノ セイゾウホウホウ
JPS52147063A (en) * 1976-06-02 1977-12-07 Toshiba Corp Semiconductor electrode forming method
DE2641334C2 (de) * 1976-09-14 1985-06-27 Siemens AG, 1000 Berlin und 8000 München Verfahren zur Herstellung integrierter MIS-Schaltungen
US4145459A (en) * 1978-02-02 1979-03-20 Rca Corporation Method of making a short gate field effect transistor
DE2842589A1 (de) * 1978-09-29 1980-05-08 Siemens Ag Feldeffekttransistor mit verringerter substratsteuerung der kanalbreite
US4261095A (en) * 1978-12-11 1981-04-14 International Business Machines Corporation Self aligned schottky guard ring
JPS56125843A (en) * 1980-03-07 1981-10-02 Chiyou Lsi Gijutsu Kenkyu Kumiai Forming method of fine pattern
JPS56131933A (en) * 1980-03-19 1981-10-15 Chiyou Lsi Gijutsu Kenkyu Kumiai Forming method of pattern of metallic film

Also Published As

Publication number Publication date
IT8223909A0 (it) 1982-10-25
FR2515425B1 (fr) 1986-01-17
DE3239819A1 (de) 1983-05-05
NL8204152A (nl) 1983-05-16
GB2108759A (en) 1983-05-18
US4441931A (en) 1984-04-10
GB2108759B (en) 1985-07-17
JPS5884432A (ja) 1983-05-20
CA1186809A (en) 1985-05-07
FR2515425A1 (fr) 1983-04-29
BE894797A (fr) 1983-02-14

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