JPS56131933A - Forming method of pattern of metallic film - Google Patents

Forming method of pattern of metallic film

Info

Publication number
JPS56131933A
JPS56131933A JP3521080A JP3521080A JPS56131933A JP S56131933 A JPS56131933 A JP S56131933A JP 3521080 A JP3521080 A JP 3521080A JP 3521080 A JP3521080 A JP 3521080A JP S56131933 A JPS56131933 A JP S56131933A
Authority
JP
Japan
Prior art keywords
film
pattern
accumulated
forming
thin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3521080A
Other languages
Japanese (ja)
Inventor
Katsuya Okumura
Hidetaro Nishimura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
CHIYOU LSI GIJUTSU KENKYU KUMIAI
CHO LSI GIJUTSU KENKYU KUMIAI
Original Assignee
CHIYOU LSI GIJUTSU KENKYU KUMIAI
CHO LSI GIJUTSU KENKYU KUMIAI
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by CHIYOU LSI GIJUTSU KENKYU KUMIAI, CHO LSI GIJUTSU KENKYU KUMIAI filed Critical CHIYOU LSI GIJUTSU KENKYU KUMIAI
Priority to JP3521080A priority Critical patent/JPS56131933A/en
Publication of JPS56131933A publication Critical patent/JPS56131933A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32134—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by liquid etching only

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Chemical & Material Sciences (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Plasma & Fusion (AREA)
  • ing And Chemical Polishing (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Weting (AREA)

Abstract

PURPOSE:To enable forming of metallic film pattern with ultra-thin 2-layer structure by using the notable difference in etching speed between the Al film accumulated near the step and other Al coated parts. CONSTITUTION:After forming an SiO2 film 3 and a contact hole 4 on an Si substrate 2 with a diffusion layer 1, a steep step 6 is formed on the film using a resist 5. The thin polycrystal line film 7 is accumulated on substrate 2 covering the step 6. Then, Al film 8 is accumulated all over. The part of Al film 8a near the step 6 will be of considerably low density and quality, compared with other parts of Al film. Then, by etching the whole film, the part of the film 8a near the step 6 is preferentially and locally removed by a small width, thus forming Al pattern 9. Then the film 7 is etched using the pattern 9 as a mask, and polycrystalline Si pattern 10 is formed. Thus, from pattern 9 and 10, ultra- thin metallic film pattern 10 is formed.
JP3521080A 1980-03-19 1980-03-19 Forming method of pattern of metallic film Pending JPS56131933A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3521080A JPS56131933A (en) 1980-03-19 1980-03-19 Forming method of pattern of metallic film

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3521080A JPS56131933A (en) 1980-03-19 1980-03-19 Forming method of pattern of metallic film

Publications (1)

Publication Number Publication Date
JPS56131933A true JPS56131933A (en) 1981-10-15

Family

ID=12435475

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3521080A Pending JPS56131933A (en) 1980-03-19 1980-03-19 Forming method of pattern of metallic film

Country Status (1)

Country Link
JP (1) JPS56131933A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5884432A (en) * 1981-10-28 1983-05-20 ウエスターン・エレクトリック・カムパニー・インコーポレーテッド Method of forming submicron pattern

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5884432A (en) * 1981-10-28 1983-05-20 ウエスターン・エレクトリック・カムパニー・インコーポレーテッド Method of forming submicron pattern

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