GB1522958A - Fabrication of semiconductor devices - Google Patents

Fabrication of semiconductor devices

Info

Publication number
GB1522958A
GB1522958A GB36831/75A GB3683175A GB1522958A GB 1522958 A GB1522958 A GB 1522958A GB 36831/75 A GB36831/75 A GB 36831/75A GB 3683175 A GB3683175 A GB 3683175A GB 1522958 A GB1522958 A GB 1522958A
Authority
GB
United Kingdom
Prior art keywords
region
groove
base
vertical
epitaxial layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB36831/75A
Other languages
English (en)
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fairchild Semiconductor Corp
Original Assignee
Fairchild Camera and Instrument Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fairchild Camera and Instrument Corp filed Critical Fairchild Camera and Instrument Corp
Publication of GB1522958A publication Critical patent/GB1522958A/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/73—Bipolar junction transistors
    • H01L29/735—Lateral transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76205—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76213—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose
    • H01L21/76216—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose introducing electrical active impurities in the local oxidation region for the sole purpose of creating channel stoppers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76213—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose
    • H01L21/76216—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose introducing electrical active impurities in the local oxidation region for the sole purpose of creating channel stoppers
    • H01L21/76218—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose introducing electrical active impurities in the local oxidation region for the sole purpose of creating channel stoppers introducing both types of electrical active impurities in the local oxidation region for the sole purpose of creating channel stoppers, e.g. for isolation of complementary doped regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8222—Bipolar technology
    • H01L21/8226—Bipolar technology comprising merged transistor logic or integrated injection logic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/053—Field effect transistors fets
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/085—Isolated-integrated
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/087—I2L integrated injection logic
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/096—Lateral transistor
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/106—Masks, special
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/117—Oxidation, selective

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Bipolar Integrated Circuits (AREA)
  • Bipolar Transistors (AREA)
  • Element Separation (AREA)
GB36831/75A 1974-10-29 1975-09-08 Fabrication of semiconductor devices Expired GB1522958A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/518,445 US3962717A (en) 1974-10-29 1974-10-29 Oxide isolated integrated injection logic with selective guard ring

Publications (1)

Publication Number Publication Date
GB1522958A true GB1522958A (en) 1978-08-31

Family

ID=24063967

Family Applications (1)

Application Number Title Priority Date Filing Date
GB36831/75A Expired GB1522958A (en) 1974-10-29 1975-09-08 Fabrication of semiconductor devices

Country Status (12)

Country Link
US (1) US3962717A (US06633600-20031014-M00021.png)
JP (1) JPS5726417B2 (US06633600-20031014-M00021.png)
BE (1) BE834962A (US06633600-20031014-M00021.png)
BR (1) BR7506172A (US06633600-20031014-M00021.png)
CA (1) CA1030274A (US06633600-20031014-M00021.png)
CH (1) CH594288A5 (US06633600-20031014-M00021.png)
DE (1) DE2545892A1 (US06633600-20031014-M00021.png)
FR (1) FR2290037A1 (US06633600-20031014-M00021.png)
GB (1) GB1522958A (US06633600-20031014-M00021.png)
HK (1) HK9582A (US06633600-20031014-M00021.png)
IT (1) IT1047337B (US06633600-20031014-M00021.png)
NL (1) NL186608C (US06633600-20031014-M00021.png)

Families Citing this family (43)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS561783B2 (US06633600-20031014-M00021.png) * 1974-12-27 1981-01-16
DE2510593C3 (de) * 1975-03-11 1982-03-18 Siemens AG, 1000 Berlin und 8000 München Integrierte Halbleiter-Schaltungsanordnung
CA1056513A (en) * 1975-06-19 1979-06-12 Benjamin J. Sloan (Jr.) Integrated logic circuit and method of fabrication
DE2532608C2 (de) * 1975-07-22 1982-09-02 Deutsche Itt Industries Gmbh, 7800 Freiburg Planardiffusionsverfahren zum Herstellen einer monolithisch integrierten Schaltung
JPS5247383A (en) * 1975-10-13 1977-04-15 Toshiba Corp Semiconductor device
JPS5261977A (en) * 1975-11-18 1977-05-21 Matsushita Electric Ind Co Ltd Semiconductor integrated circuit device and its production
US4084174A (en) * 1976-02-12 1978-04-11 Fairchild Camera And Instrument Corporation Graduated multiple collector structure for inverted vertical bipolar transistors
US4143455A (en) * 1976-03-11 1979-03-13 Siemens Aktiengesellschaft Method of producing a semiconductor component
US4137109A (en) * 1976-04-12 1979-01-30 Texas Instruments Incorporated Selective diffusion and etching method for isolation of integrated logic circuit
JPS52141587A (en) * 1976-05-20 1977-11-25 Matsushita Electric Ind Co Ltd Semiconductor device and its process
US4066473A (en) * 1976-07-15 1978-01-03 Fairchild Camera And Instrument Corporation Method of fabricating high-gain transistors
JPS5367383A (en) * 1976-08-08 1978-06-15 Fairchild Camera Instr Co Method of producing small ic implantation logic semiconductor
US4149177A (en) * 1976-09-03 1979-04-10 Fairchild Camera And Instrument Corporation Method of fabricating conductive buried regions in integrated circuits and the resulting structures
JPS5338276A (en) * 1976-09-20 1978-04-08 Toshiba Corp Semiconductor device
JPS5252378A (en) * 1976-10-01 1977-04-27 Sony Corp Semiconductor device
US4115797A (en) * 1976-10-04 1978-09-19 Fairchild Camera And Instrument Corporation Integrated injection logic with heavily doped injector base self-aligned with injector emitter and collector
JPS5368990A (en) * 1976-12-01 1978-06-19 Fujitsu Ltd Production of semiconductor integrated circuit
GB1597536A (en) * 1977-03-18 1981-09-09 Texas Instruments Inc High performance integrated injection logic gate utilizing p-type schottky input diodes
JPS53121485A (en) * 1977-03-30 1978-10-23 Mitsubishi Electric Corp Semiconductor logic circuit device of electrostatic induction type
NL7703941A (nl) * 1977-04-12 1978-10-16 Philips Nv Werkwijze ter vervaardiging van een halfgelei- derinrichting en inrichting, vervaardigd door toepassing van de werkwijze.
US4168999A (en) * 1978-12-26 1979-09-25 Fairchild Camera And Instrument Corporation Method for forming oxide isolated integrated injection logic semiconductor structures having minimal encroachment utilizing special masking techniques
DE3020609C2 (de) * 1979-05-31 1985-11-07 Tokyo Shibaura Denki K.K., Kawasaki, Kanagawa Verfahren zum Herstellen einer integrierten Schaltung mit wenigstens einem I↑2↑L-Element
US4338622A (en) * 1979-06-29 1982-07-06 International Business Machines Corporation Self-aligned semiconductor circuits and process therefor
JPS556899A (en) * 1979-07-06 1980-01-18 Toshiba Corp Semiconductor device
US4322882A (en) * 1980-02-04 1982-04-06 Fairchild Camera & Instrument Corp. Method for making an integrated injection logic structure including a self-aligned base contact
JPS5610959A (en) * 1980-03-17 1981-02-03 Toshiba Corp Manufacture of semiconductor device
US4512075A (en) * 1980-08-04 1985-04-23 Fairchild Camera & Instrument Corporation Method of making an integrated injection logic cell having self-aligned collector and base reduced resistance utilizing selective diffusion from polycrystalline regions
JPS5658870U (US06633600-20031014-M00021.png) * 1980-10-02 1981-05-20
JPS5792858A (en) * 1980-12-01 1982-06-09 Hitachi Ltd Semiconductor integrated circuit device and manufacture thereof
US4373252A (en) * 1981-02-17 1983-02-15 Fairchild Camera & Instrument Method for manufacturing a semiconductor structure having reduced lateral spacing between buried regions
US4374011A (en) * 1981-05-08 1983-02-15 Fairchild Camera & Instrument Corp. Process for fabricating non-encroaching planar insulating regions in integrated circuit structures
JPS58206171A (ja) * 1982-05-26 1983-12-01 Nec Corp 半導体集積回路装置
JPS5957471A (ja) * 1982-09-28 1984-04-03 Toshiba Corp 半導体装置
US5166094A (en) * 1984-09-14 1992-11-24 Fairchild Camera & Instrument Corp. Method of fabricating a base-coupled transistor logic
US4925806A (en) * 1988-03-17 1990-05-15 Northern Telecom Limited Method for making a doped well in a semiconductor substrate
US5289024A (en) * 1990-08-07 1994-02-22 National Semiconductor Corporation Bipolar transistor with diffusion compensation
US5047117A (en) * 1990-09-26 1991-09-10 Micron Technology, Inc. Method of forming a narrow self-aligned, annular opening in a masking layer
JPH0785476B2 (ja) * 1991-06-14 1995-09-13 インターナショナル・ビジネス・マシーンズ・コーポレイション エミッタ埋め込み型バイポーラ・トランジスタ構造
US5573837A (en) * 1992-04-22 1996-11-12 Micron Technology, Inc. Masking layer having narrow isolated spacings and the method for forming said masking layer and the method for forming narrow isolated trenches defined by said masking layer
JPH10303291A (ja) * 1997-04-25 1998-11-13 Nippon Steel Corp 半導体装置及びその製造方法
JP2001217317A (ja) * 2000-02-07 2001-08-10 Sony Corp 半導体装置およびその製造方法
ES2275039T3 (es) 2003-04-24 2007-06-01 Goldschmidt Gmbh Procedimiento para la produccion de revestimientos laminares desprendibles, repelentes de la suciedad y del agua.
TR201906951A2 (tr) * 2019-05-09 2019-05-21 Ankara Ueniversitesi Rektoerluegue Enzimatik İşlemlerle Nar Suyu Kusurlarının Giderilmesi İçin Yöntem

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3386865A (en) * 1965-05-10 1968-06-04 Ibm Process of making planar semiconductor devices isolated by encapsulating oxide filled channels
GB1153497A (en) * 1966-07-25 1969-05-29 Associated Semiconductor Mft Improvements in and relating to Semiconductor Devices
DE2021824C3 (de) * 1970-05-05 1980-08-14 Ibm Deutschland Gmbh, 7000 Stuttgart Monolithische Halbleiterschaltung
US3648125A (en) * 1971-02-02 1972-03-07 Fairchild Camera Instr Co Method of fabricating integrated circuits with oxidized isolation and the resulting structure
NL173110C (nl) * 1971-03-17 1983-12-01 Philips Nv Werkwijze ter vervaardiging van een halfgeleiderinrichting, waarbij op een oppervlak van een halfgeleiderlichaam een uit ten minste twee deellagen van verschillend materiaal samengestelde maskeringslaag wordt aangebracht.
JPS5528229B1 (US06633600-20031014-M00021.png) * 1971-03-19 1980-07-26
NL170901C (nl) * 1971-04-03 1983-01-03 Philips Nv Werkwijze voor het vervaardigen van een halfgeleiderinrichting.
US3873989A (en) * 1973-05-07 1975-03-25 Fairchild Camera Instr Co Double-diffused, lateral transistor structure
US3904450A (en) * 1974-04-26 1975-09-09 Bell Telephone Labor Inc Method of fabricating injection logic integrated circuits using oxide isolation
NL7413264A (nl) * 1974-10-09 1976-04-13 Philips Nv Geintegreerde schakeling.

Also Published As

Publication number Publication date
NL186608B (nl) 1990-08-01
DE2545892A1 (de) 1976-05-13
JPS5726417B2 (US06633600-20031014-M00021.png) 1982-06-04
NL186608C (nl) 1991-01-02
BR7506172A (pt) 1976-08-17
IT1047337B (it) 1980-09-10
NL7512333A (nl) 1976-05-04
HK9582A (en) 1982-03-12
FR2290037B1 (US06633600-20031014-M00021.png) 1980-05-16
BE834962A (fr) 1976-02-16
CA1030274A (en) 1978-04-25
AU8607775A (en) 1977-05-05
US3962717A (en) 1976-06-08
CH594288A5 (US06633600-20031014-M00021.png) 1978-01-13
FR2290037A1 (fr) 1976-05-28
JPS5154379A (US06633600-20031014-M00021.png) 1976-05-13

Similar Documents

Publication Publication Date Title
GB1522958A (en) Fabrication of semiconductor devices
GB1330790A (en) Semiconductor devices
GB1507061A (en) Semiconductors
US4311532A (en) Method of making junction isolated bipolar device in unisolated IGFET IC
GB1524592A (en) Bipolar type semiconductor devices
GB1314355A (en) Semiconductor device
GB1402376A (en) Zener diode structure
US3445734A (en) Single diffused surface transistor and method of making same
GB1263127A (en) Integrated circuits
GB1470211A (en) Semiconductor devices
US5091336A (en) Method of making a high breakdown active device structure with low series resistance
GB1169188A (en) Method of Manufacturing Semiconductor Devices
US4180827A (en) NPN/PNP Fabrication process with improved alignment
GB1505103A (en) Semiconductor device having complementary transistors and method of manufacturing same
GB1303236A (US06633600-20031014-M00021.png)
GB1455260A (en) Semiconductor devices
GB1296562A (US06633600-20031014-M00021.png)
GB1154049A (en) Improvements in or relating to Avalanche Diodes.
GB1244508A (en) Zener diode semiconductor devices
GB1452882A (en) Zener diode for integrated circuits
GB1337906A (en) Integrated semiconductor structure
GB1194752A (en) Transistor
GB1514578A (en) Semiconductor devices
GB1245765A (en) Surface diffused semiconductor devices
GB899919A (en) Improvements in semi-conductive devices

Legal Events

Date Code Title Description
PS Patent sealed [section 19, patents act 1949]
PE20 Patent expired after termination of 20 years

Effective date: 19950907