JPS5610959A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS5610959A
JPS5610959A JP3265380A JP3265380A JPS5610959A JP S5610959 A JPS5610959 A JP S5610959A JP 3265380 A JP3265380 A JP 3265380A JP 3265380 A JP3265380 A JP 3265380A JP S5610959 A JPS5610959 A JP S5610959A
Authority
JP
Japan
Prior art keywords
type
layers
layer
substrate
lateral
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3265380A
Other languages
Japanese (ja)
Inventor
Masanori Nakai
Shintaro Ito
Seiya Tokumaru
Junichi Nakamura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP3265380A priority Critical patent/JPS5610959A/en
Publication of JPS5610959A publication Critical patent/JPS5610959A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8222—Bipolar technology
    • H01L21/8226—Bipolar technology comprising merged transistor logic or integrated injection logic

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Bipolar Transistors (AREA)
  • Bipolar Integrated Circuits (AREA)

Abstract

PURPOSE:To contrive the improvement in the current amplification factor of both lateral and longitudinal type transistors in a semiconductor device by forming the emitter of the lateral transistor of a P<+>-type layer and the effective base of the longitudinal transistor of an N<->-type layer in an II device. CONSTITUTION:An N<->-type epitaxial layer 12 and an SiO2 film 101 are laminated on an N<+>-type Si substrate 11, and ion is implanted so selectively form P<+>-type layers 13, 14 thereon. A resist mask 202 is coated, and ion is implanted to form P<->- type layers 161, 162 thereon. The mask is removed therefrom, the substrate is then treated at low temperature, and is coated with an SiO2 film 102. The substrate is then treated at high temperature to diffuse the layers 13, 14, and N<+>-type layers 151, 152 and P-type layers 161, 162 are laminated from the surface of the layers 161, 162 surrounded by the layer 14 toward the deep portion. Then, N<+>-type layers 171, 172 making contact with the layers 161, 162 are formed directly under the layers 161, 162 by an ion implantation, and the side surface is contacted with the layer 14. Subsequently, electrodes are formed as prescribed to complete the configuration. This configuration can extremely increase the emitter injection efficiency of the lateral and longitudinal transistors to increase the current amplification factor and to accelerate the operating velocity thereof.
JP3265380A 1980-03-17 1980-03-17 Manufacture of semiconductor device Pending JPS5610959A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3265380A JPS5610959A (en) 1980-03-17 1980-03-17 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3265380A JPS5610959A (en) 1980-03-17 1980-03-17 Manufacture of semiconductor device

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP8491879A Division JPS556899A (en) 1979-07-06 1979-07-06 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS5610959A true JPS5610959A (en) 1981-02-03

Family

ID=12364817

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3265380A Pending JPS5610959A (en) 1980-03-17 1980-03-17 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5610959A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63394A (en) * 1986-06-04 1988-01-05 ユニリ−バ−　ナ−ムロ−ゼ　ベンノ−トシヤ−プ Fractionation of fat compound

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5154379A (en) * 1974-10-29 1976-05-13 Fairchild Camera Instr Co
JPS5183479A (en) * 1975-01-20 1976-07-22 Tokyo Shibaura Electric Co

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5154379A (en) * 1974-10-29 1976-05-13 Fairchild Camera Instr Co
JPS5183479A (en) * 1975-01-20 1976-07-22 Tokyo Shibaura Electric Co

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63394A (en) * 1986-06-04 1988-01-05 ユニリ−バ−　ナ−ムロ−ゼ　ベンノ−トシヤ−プ Fractionation of fat compound

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