GB1597536A - High performance integrated injection logic gate utilizing p-type schottky input diodes - Google Patents
High performance integrated injection logic gate utilizing p-type schottky input diodes Download PDFInfo
- Publication number
- GB1597536A GB1597536A GB8531/78A GB853178A GB1597536A GB 1597536 A GB1597536 A GB 1597536A GB 8531/78 A GB8531/78 A GB 8531/78A GB 853178 A GB853178 A GB 853178A GB 1597536 A GB1597536 A GB 1597536A
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- Prior art keywords
- collector
- schottky
- transistor
- regions
- resistivity
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- 238000002347 injection Methods 0.000 title claims description 15
- 239000007924 injection Substances 0.000 title claims description 15
- 239000004065 semiconductor Substances 0.000 claims description 29
- 239000010410 layer Substances 0.000 claims description 17
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 13
- 229910052796 boron Inorganic materials 0.000 claims description 13
- 239000000758 substrate Substances 0.000 claims description 13
- 239000007943 implant Substances 0.000 claims description 12
- 238000004519 manufacturing process Methods 0.000 claims description 11
- 238000002513 implantation Methods 0.000 claims description 10
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 claims description 8
- 239000002019 doping agent Substances 0.000 claims description 7
- 230000004888 barrier function Effects 0.000 claims description 6
- 150000002500 ions Chemical class 0.000 claims description 6
- 229910052785 arsenic Inorganic materials 0.000 claims description 4
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 4
- 239000011159 matrix material Substances 0.000 claims description 4
- 229910052697 platinum Inorganic materials 0.000 claims description 4
- 230000000295 complement effect Effects 0.000 claims description 3
- 239000002344 surface layer Substances 0.000 claims description 3
- ZXEYZECDXFPJRJ-UHFFFAOYSA-N $l^{3}-silane;platinum Chemical compound [SiH3].[Pt] ZXEYZECDXFPJRJ-UHFFFAOYSA-N 0.000 claims description 2
- 229910052782 aluminium Inorganic materials 0.000 claims description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 2
- 229910001439 antimony ion Inorganic materials 0.000 claims description 2
- 229910052751 metal Inorganic materials 0.000 claims description 2
- 239000002184 metal Substances 0.000 claims description 2
- 230000003647 oxidation Effects 0.000 claims description 2
- 238000007254 oxidation reaction Methods 0.000 claims description 2
- 230000001590 oxidative effect Effects 0.000 claims description 2
- 229910021339 platinum silicide Inorganic materials 0.000 claims description 2
- MAKDTFFYCIMFQP-UHFFFAOYSA-N titanium tungsten Chemical compound [Ti].[W] MAKDTFFYCIMFQP-UHFFFAOYSA-N 0.000 claims description 2
- 238000000034 method Methods 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000001934 delay Effects 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
- H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28537—Deposition of Schottky electrodes
-
- H01L21/8226—
-
- H01L27/0233—
-
- H01L27/075—
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- High Energy & Nuclear Physics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Electrodes Of Semiconductors (AREA)
- Bipolar Integrated Circuits (AREA)
- Bipolar Transistors (AREA)
- Logic Circuits (AREA)
Description
(54) HIGH PERFORMANCE INTEGRATED INJECTION LOGIC GATE
UTILIZING P-TYPE SCHOTTKY INPUT DIODES
(71) We, TEXAS INSTRUMENTS INCOR
PORATED. a Corporation organized according to the laws of the State of Delaware, United
States of America, of 13500 North Central
Expressway, Dallas, Texas, United States of
America; do hereby declare the invention, for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the following statement:- This invention relates to integrated semiconductor circuits and, more particularly, to an integrated injection logic gate utilizing ptype Schottky input diodes, and to methods for its fabrication. Specifically, the gate is fabricated on n-type epitaxial semiconductor material, and preferably with the use of ion implantation to prepare a suitable p-type surface for fabrication of the Schottky contacts.
An integrated injection logic (I2L) gate consists essentially of an inverted, multiplecollector, bipolar transistor, integrated such that the emitter of the inverted transistor is electrically common with the base of the lateral transistor and such that the collector of the lateral transistor is electrically common with the base of the inverted transistor.
The use of Schottky diodes in conjunction with an integrated injection logic gate for the purpose of reducing propagation delays has received considerable attention. See, for example, Berger and Wiedman "Schottky
Transistor Logic," ISSCC Digest of Technical Papers, Pages 172-73, February 1975, and U.S. Patents 3,922,565 and 3,961,351.
Practical implementation of Schottky diodes has been impeded by several factors. For example, it has been difficult to fabricate low-leakage Schottky junctions on p-type silicon. Also, a Schottky junction can be a very effective transistor collector, but is not practical as an emitter. Still further, the formation of additional junctions adjacent to an 12L gate frequently results in parasitic transistor action, which degrades the performance of the circuit.
According to a first aspect of the present invention there is provided an integrated injection logic gate comprising a low-resistivity semiconductor substrate of n-type conductivity type and a high-resistivity epitaxial layer thereon of the same conductivity type, said layer including an inverted, multiplecollector bipolar transistor and a complementary lateral bipolar transistor, the emitter of the former being electrically connected to the base of the latter, and the base of the former being electrically connected to the collector of the latter; including one or more of Schottky input diodes, the semiconductor portion of which has p-type conductivity, and is electrically connected to the base of said inverted transistor.
According to a second aspect of the present invention there is provided a method of fabricating an integrated injection logic gate structure having Schottky input diodes, including the steps of: forming a matrix of separate, high-resistivity semiconductor regions in the epitaxial layer of monocrystalline semiconductor of n-type conductivity on a low-resistivity semiconductor substrate region of the same type; forming within each of said selected regions first and second semiconductor regions of p-type conductivity, spaced apart sufficiently close to form the emitter and collector of a lateral bipolar transistor, said collector having a repeated pattern of segments which define and sepa rate a plurality of surface regions within said surface layer; selectively implanting a dopant of p-type conductivity within at least one of said separate surface regions with sufficient energy to place substantially all the dopant below the semiconductor surface and form therein a subsurface doped region electrically connected to said collector of the lateral bipolar transistor and having such a thickness that it is capable of functioning as the base of an inverted, multiple-collector bipolar transistor, the collector and base of which are formed by the surface region remaining substantially unchanged above and below the subsurface region respectively; selectively doping at least one other of said separate regions to reverse the conductivity type thereof at the surface and thereby form a region contacting said lateral transistor collector and having a resistivity suitable to serve as the semiconductor portion of a
Schottky diode; and forming conductive contacts to the emitter of said lateral transistor, and the collectors of said inverted transistor; and a Schottky contact to said other of said separate surface regions, thereby completing the gate structure.
The Schottky diodes not only increase circuit speed, but also provide significantly more logic flexibility by facilitating the design of gates having multiple inputs with a single output; multiple outputs from a single input; and intermediate combinations. Such flexibility can reduce the number of gates required to perform a given logic function.
An embodiment of the invention will now be described by way of example only making reference to the accompanying drawings in which:
FIGURE 1 is a schematic perspective view, partially in cross-section, showing the junction geometry of an 12L gate embodying the invention;
FIGURE 2 is a circuit diagram illustrating the electrical commonality of the semiconductor portion of the Schottky input diodes with the base of the inverted multiplecollector transistor;
FIGUREs 3 through 7 are enlarged crosssectional views of a semiconductor wafer, illustrating the sequence of process steps employed to fabricate the device of Figure 1.
As seen in Figure 1, the gate structure includes n-type substrate 11 having thereon an epitaxial layer 12 of the same conductivity type, wherein an array of regions is defined by oxide matrix 13. A single cell of the array is illustrated, including injector or emitter 14 and collector 15 of a lateral bipolar transistor. The collector includes a repeated pattern of segments that define and separate a first plurality of regions wherein base 19 and n + collector regions 20 are located, and a second plurality of regions wherein the p-type
Schottky diodes are located, including semiconductor zones 21, doped surface 22, and
Schottky contacts 25. Ohmic contacts 23 and 24 are the injector and inverted collector terminals, respectively.
As shown in Figure 2, the lateral transistor T1 is integrated with inverted multiple collector transistor T2 such that the base of the former and the emitter of the latter are common; and such that the collector of the former is connected to the base of the latter.
The Schottky input diodes include anodes that are also connected to the base of T2.
Referring now to Figure 3, fabrication of the gate typically begins with an n-type silicon substrate 11 having a resistivity of about 0.01 ohm-centimeter, for example, having an n-type epitaxial layer 12 thereon about 1.41. thick, for example, the resistivity of which is about 2 ohm-centimeters, for example. An oxide guard ring 13 is provided in layer 12 to separate adjacent logic cells. Instead of oxide region 13 an n+ guard ring may be employed for the same purpose. The depth of the n+ guard ring or oxide guard ring need not be as great as in the illustrated embodiment, and need not touch substrate 11. The depth is dependent on the amount of electrical cross-talk between cells which can be tolerated.
As shown in Figure 4, a p+ diffusion or implantation step is then carried out to form the emitter 14 and collector 15 for the lateral pnp transistor. It will be apparent that the spacing between emitter region 14 and the nearest portion 15a of collector region 15 must be sufficiently close to permit transistor action, in combination with that portion 16 of layer 12 therebetween which functions as the transistor base. For example, a suitable base width in the mask pattern is about 0.15--0.20 mils. The remaining geometry of region 15 includes a repeated pattern of segments 15b, 15c etc., which define and separate a plurality of surface regions within layer 12. One such region 17 represents a location wherein a single active base region and collector are to be fabricated as a portion of the inverted, multiple-collector transistor
T2 illustrated in Figure 2. It will be apparent that each cell includes one or more additional regions identical to region 17. Similarly, region 18 represents a single location for the fabrication of one of the Schottky diodes to be electrically connected to the base of transistor T2. In practice there will typically be two or more such diode locations within each of selected cells.
As shown in Figure 5 the next step of the process is a high energy implantation of a ptype dopant such as boron, for example, within region 17 to form a subsurface band 19 having a thickness suitable to function as a transistor base in combination with the unchanged portions of layer 12 thereabove and therebelow which function as collector and emitter. respectively, of the inverted npn device. An implant energy of about 400 KeV and a dosage of 1-2 x 1012 cm2 is suitable.
for example. Subsequently, following oxidation, windows are cut to selectively expose an area within region 17 for the completion of n+ collector regions 20, which may be achieved, for example, by an arsenic implantation dosage of about 5 x 10'5 ions per square centimeter at 100 KeV. The implants are then annealed in an oxidizing ambient.
As shown in Figure 6 the fabrication of
Schottky diodes at locations 18 is then completed. This entails, first of all, a selective removal of oxide from such locations, followed by a selective implantation of boron to form region 21, for example, with a dosage of about 1 to 5 x 10s4 ions per square centimeter at an energy of 400 KeV to prevent transistor action between the n+ substrate and the
Schottky junction. A second light boron implant (typically 1 X 1012 ions per square centimeter at 100 KeV) is used to more accurately control the surface boron concentration. These two boron implantation steps may be replaced by a single boron implantation to simultaneously kill transistor action and to control surface boron concentration.
It will be apparent that this alternative embodiment requires a more careful control of dosage and energy.
Finally, a low-dosage, low-energy antimony ion implant 22 or low-energy arsenic implant (typically 5 to 30 KeV) is used to adjust the barrier height of the Schottky junction, thereby preventing excessive leakage currents. More information regarding the adjustment of barrier heights in this manner may be obtained from Shannon, Applied
Physics Letters, Volume 25, No. 1, pages 75-7, 1 July 1974.
A thin oxide is then deposited and the implants are annealed. The oxide is then removed from ohmic contact locations to emitter 14 and to the n+ collector regions 20.
Platinum is deposited and sintered, forming platinum silicide in these windows. After removing the residual platinum the oxide is removed from the Schottky contacts and a barrier metal system such as titanium-tungsten and aluminum is deposited and defined over the slice, forming p-Schottky contacts 25 as well as ohmic contacts 23 and 24. The completed structure is then annealed at a temperature of about 450 to 5004 C.
WHAT WE CLAIM IS:
1. An integrated injection logic gate comprising a low-resistivity semiconductor substrate of n-type conductivity type and a high-resistivity epitaxial layer thereon of the same conductivity type, said layer including an inverted, multiple-collector bipolar transistor and a complementary lateral bipolar transistor, the emitter of the former being electrically connected to the base of the latter, and the base of the former being electrically connected to the collector of the latter; including one or more of Schottky input diodes, the semiconductor portion of which has p-type conductivity, and is electrically connected to the base of said inverted transistor.
2. A logic gate as in claim 1 wherein said substrate has a resistivity of about 0.01 ohmcm and the epitaxial layer has a resistivity of about 2 ohm-cm.
3. A method of fabricating an integrated injection logic gate structure having Schottky input diodes, including the steps of:
forming a matrix of separate, high-resistivity semiconductor regions in an epitaxial layer of monocrystalline semiconductor of ntype conductivity on a low-resistivity semiconductor substrate region of the same type;
forming within each of said selected regions first and second semiconductor regions of p-type conductivity, spaced apart sufficiently close to form the emitter and collector of a lateral bipolar transistor, said collector having a repeated pattern of segments which define and separate a plurality of surface regions within said surface layer;
selectively implanting a dopant of p-type conductivity within at least one of said separate surface regions with sufficient energy to place substantially all the dopant below the semiconductor surface and form therein a subsurface doped region electrically connected to said collector of the lateral bipolar transistor and having such a thickness that it is capable of functioning as the base of an inverted, multiple-collector bipolar transistor, the collector and base of which are formed by the surface region remaining substantially unchanged above and below the subsurface region respectively;
selectively doping at least one other of said separate regions to reverse the conductivity type thereof at the surface and thereby form a region contacting said lateral transistor collector and having a resistivity suitable to serve as the semiconductor portion of a
Schottky diode; and
forming conductive contacts to the emitter of said lateral transistor, and the collectors of said inverted transistor; and a Schottky contact to said other of said separate surface regions, thereby completing the gate structure.
4. An integrated injection logic gate substantially as herein described with reference to the accompanying drawings.
5. A method of fabricating an integrated injection logic gate substantially as herein described with reference to the accompanying drawings.
**WARNING** end of DESC field may overlap start of CLMS **.
Claims (5)
1. An integrated injection logic gate comprising a low-resistivity semiconductor substrate of n-type conductivity type and a high-resistivity epitaxial layer thereon of the same conductivity type, said layer including an inverted, multiple-collector bipolar transistor and a complementary lateral bipolar transistor, the emitter of the former being electrically connected to the base of the latter, and the base of the former being electrically connected to the collector of the latter; including one or more of Schottky input diodes, the semiconductor portion of which has p-type conductivity, and is electrically connected to the base of said inverted transistor.
2. A logic gate as in claim 1 wherein said substrate has a resistivity of about 0.01 ohmcm and the epitaxial layer has a resistivity of about 2 ohm-cm.
3. A method of fabricating an integrated injection logic gate structure having Schottky input diodes, including the steps of:
forming a matrix of separate, high-resistivity semiconductor regions in an epitaxial layer of monocrystalline semiconductor of ntype conductivity on a low-resistivity semiconductor substrate region of the same type;
forming within each of said selected regions first and second semiconductor regions of p-type conductivity, spaced apart sufficiently close to form the emitter and collector of a lateral bipolar transistor, said collector having a repeated pattern of segments which define and separate a plurality of surface regions within said surface layer;
selectively implanting a dopant of p-type conductivity within at least one of said separate surface regions with sufficient energy to place substantially all the dopant below the semiconductor surface and form therein a subsurface doped region electrically connected to said collector of the lateral bipolar transistor and having such a thickness that it is capable of functioning as the base of an inverted, multiple-collector bipolar transistor, the collector and base of which are formed by the surface region remaining substantially unchanged above and below the subsurface region respectively;
selectively doping at least one other of said separate regions to reverse the conductivity type thereof at the surface and thereby form a region contacting said lateral transistor collector and having a resistivity suitable to serve as the semiconductor portion of a
Schottky diode; and
forming conductive contacts to the emitter of said lateral transistor, and the collectors of said inverted transistor; and a Schottky contact to said other of said separate surface regions, thereby completing the gate structure.
4. An integrated injection logic gate substantially as herein described with reference to the accompanying drawings.
5. A method of fabricating an integrated injection logic gate substantially as herein described with reference to the accompanying drawings.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US77941977A | 1977-03-18 | 1977-03-18 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| GB1597536A true GB1597536A (en) | 1981-09-09 |
Family
ID=25116383
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB8531/78A Expired GB1597536A (en) | 1977-03-18 | 1978-03-03 | High performance integrated injection logic gate utilizing p-type schottky input diodes |
Country Status (4)
| Country | Link |
|---|---|
| JP (1) | JPS53136979A (en) |
| DE (1) | DE2811102A1 (en) |
| GB (1) | GB1597536A (en) |
| NL (1) | NL7802950A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE3205950A1 (en) * | 1981-10-22 | 1983-05-05 | Robert Bosch Gmbh, 7000 Stuttgart | BIPOLAR INTEGRATED INVERST TRANSISTOR LOGIC |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3962717A (en) * | 1974-10-29 | 1976-06-08 | Fairchild Camera And Instrument Corporation | Oxide isolated integrated injection logic with selective guard ring |
| CA1056513A (en) * | 1975-06-19 | 1979-06-12 | Benjamin J. Sloan (Jr.) | Integrated logic circuit and method of fabrication |
-
1978
- 1978-03-03 GB GB8531/78A patent/GB1597536A/en not_active Expired
- 1978-03-14 DE DE19782811102 patent/DE2811102A1/en not_active Ceased
- 1978-03-17 JP JP3001678A patent/JPS53136979A/en active Pending
- 1978-03-17 NL NL7802950A patent/NL7802950A/en not_active Application Discontinuation
Also Published As
| Publication number | Publication date |
|---|---|
| NL7802950A (en) | 1978-09-20 |
| DE2811102A1 (en) | 1978-09-28 |
| JPS53136979A (en) | 1978-11-29 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PS | Patent sealed | ||
| PCNP | Patent ceased through non-payment of renewal fee |