FR2709207A1 - Procédé de métallisation d'un circuit intégré. - Google Patents

Procédé de métallisation d'un circuit intégré.

Info

Publication number
FR2709207A1
FR2709207A1 FR9402273A FR9402273A FR2709207A1 FR 2709207 A1 FR2709207 A1 FR 2709207A1 FR 9402273 A FR9402273 A FR 9402273A FR 9402273 A FR9402273 A FR 9402273A FR 2709207 A1 FR2709207 A1 FR 2709207A1
Authority
FR
France
Prior art keywords
integrated circuit
metallic layer
opening
metallization process
contact
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
FR9402273A
Other languages
English (en)
Other versions
FR2709207B1 (fr
Inventor
Kuang-Chao Chen
Shaw Tzeng Hsia
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Industrial Technology Research Institute ITRI
Original Assignee
Industrial Technology Research Institute ITRI
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Industrial Technology Research Institute ITRI filed Critical Industrial Technology Research Institute ITRI
Publication of FR2709207A1 publication Critical patent/FR2709207A1/fr
Application granted granted Critical
Publication of FR2709207B1 publication Critical patent/FR2709207B1/fr
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76855—After-treatment introducing at least one additional element into the layer
    • H01L21/76858—After-treatment introducing at least one additional element into the layer by diffusing alloying elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
    • H01L21/743—Making of internal connections, substrate contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53214—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being aluminium
    • H01L23/53223—Additional layers associated with aluminium layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Physical Vapour Deposition (AREA)

Abstract

Procédé de métallisation d'un circuit intégré consistant à fournir une couche isolante sur la surface d'un substrat de semi-conducteur, fournir au moins une ouverture pour contact à travers ladite couche isolante vers ledit substrat de semi-conducteur, déposer une couche métallique de connexion sur la surface dudit substrat et à l'intérieur de ladite ouverture pour contact dans laquelle la plus grande partie dudit métal de connexion est dépmosée sur le fond de ladite ouverture pour contact plutôt que sur les côtés de ladite ouverture; pulvériser à froid une couche métallique sur ladite couche métallique de connexion, et pulvériser à chaud une couche métallique sur ladite couche métallique pulvérisée à froid, dans lequel ladite pulvérisation à chaud et à froid sont des opérations continues pour réaliser ladite métallisation dudit circuit intégré.
FR9402273A 1993-08-19 1994-02-28 Procédé de métallisation d'un circuit intégré. Expired - Fee Related FR2709207B1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/108,224 US5356836A (en) 1993-08-19 1993-08-19 Aluminum plug process

Publications (2)

Publication Number Publication Date
FR2709207A1 true FR2709207A1 (fr) 1995-02-24
FR2709207B1 FR2709207B1 (fr) 1996-10-25

Family

ID=22320980

Family Applications (1)

Application Number Title Priority Date Filing Date
FR9402273A Expired - Fee Related FR2709207B1 (fr) 1993-08-19 1994-02-28 Procédé de métallisation d'un circuit intégré.

Country Status (5)

Country Link
US (1) US5356836A (fr)
JP (1) JPH0766205A (fr)
KR (1) KR100291284B1 (fr)
DE (1) DE4400726A1 (fr)
FR (1) FR2709207B1 (fr)

Families Citing this family (52)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2598335B2 (ja) * 1990-08-28 1997-04-09 三菱電機株式会社 半導体集積回路装置の配線接続構造およびその製造方法
EP0499433B1 (fr) * 1991-02-12 1998-04-15 Matsushita Electronics Corporation Dispositif semi-conducteur ayant un cablage à fonctionnement amélioré, et procédé pour sa fabrication
JP3401843B2 (ja) * 1993-06-21 2003-04-28 ソニー株式会社 半導体装置における多層配線の形成方法
US5747360A (en) * 1993-09-17 1998-05-05 Applied Materials, Inc. Method of metalizing a semiconductor wafer
JPH07130852A (ja) * 1993-11-02 1995-05-19 Sony Corp 金属配線材料の形成方法
JP2797933B2 (ja) * 1993-11-30 1998-09-17 日本電気株式会社 半導体装置の製造方法
JPH07161813A (ja) * 1993-12-08 1995-06-23 Nec Corp 半導体装置の製造方法
US5585308A (en) * 1993-12-23 1996-12-17 Sgs-Thomson Microelectronics, Inc. Method for improved pre-metal planarization
US5599749A (en) * 1994-10-21 1997-02-04 Yamaha Corporation Manufacture of micro electron emitter
US5449639A (en) * 1994-10-24 1995-09-12 Taiwan Semiconductor Manufacturing Company Ltd. Disposable metal anti-reflection coating process used together with metal dry/wet etch
US5523259A (en) * 1994-12-05 1996-06-04 At&T Corp. Method of forming metal layers formed as a composite of sub-layers using Ti texture control layer
US5580823A (en) * 1994-12-15 1996-12-03 Motorola, Inc. Process for fabricating a collimated metal layer and contact structure in a semiconductor device
US6285082B1 (en) * 1995-01-03 2001-09-04 International Business Machines Corporation Soft metal conductor
JPH08191104A (ja) * 1995-01-11 1996-07-23 Hitachi Ltd 半導体集積回路装置およびその製造方法
JP2953340B2 (ja) * 1995-03-29 1999-09-27 ヤマハ株式会社 配線形成法
EP0793268A3 (fr) * 1995-05-23 1999-03-03 Texas Instruments Incorporated Procédé de remplissage d'une cavité d'un dispositif semiconducteur
KR0179827B1 (ko) * 1995-05-27 1999-04-15 문정환 반도체 소자의 배선 형성방법
TW298674B (fr) * 1995-07-07 1997-02-21 At & T Corp
US5604155A (en) * 1995-07-17 1997-02-18 Winbond Electronics Corp. Al-based contact formation process using Ti glue layer to prevent nodule-induced bridging
SG42438A1 (en) * 1995-09-27 1997-08-15 Motorola Inc Process for fabricating a CVD aluminium layer in a semiconductor device
US5633199A (en) * 1995-11-02 1997-05-27 Motorola Inc. Process for fabricating a metallized interconnect structure in a semiconductor device
US5776831A (en) * 1995-12-27 1998-07-07 Lsi Logic Corporation Method of forming a high electromigration resistant metallization system
US5804251A (en) * 1995-12-29 1998-09-08 Intel Corporation Low temperature aluminum alloy plug technology
US5851923A (en) * 1996-01-18 1998-12-22 Micron Technology, Inc. Integrated circuit and method for forming and integrated circuit
JP2891161B2 (ja) * 1996-02-15 1999-05-17 日本電気株式会社 配線形成方法
US5677238A (en) * 1996-04-29 1997-10-14 Chartered Semiconductor Manufacturing Pte Ltd Semiconductor contact metallization
US6083823A (en) * 1996-06-28 2000-07-04 International Business Machines Corporation Metal deposition process for metal lines over topography
US5883002A (en) * 1996-08-29 1999-03-16 Winbond Electronics Corp. Method of forming contact profile by improving TEOS/BPSG selectivity for manufacturing a semiconductor device
US5985746A (en) * 1996-11-21 1999-11-16 Lsi Logic Corporation Process for forming self-aligned conductive plugs in multiple insulation levels in integrated circuit structures and resulting product
JPH10172969A (ja) * 1996-12-06 1998-06-26 Nec Corp 半導体装置の製造方法
US6162729A (en) * 1996-12-12 2000-12-19 Asahi Kasei Kogyo Kabushiki Kaisha Method of manufacturing multiple aluminum layer in a semiconductor device
US6395629B1 (en) 1997-04-16 2002-05-28 Stmicroelectronics, Inc. Interconnect method and structure for semiconductor devices
KR100241506B1 (ko) * 1997-06-23 2000-03-02 김영환 반도체 소자의 금속 배선 형성 방법
US5994206A (en) * 1997-10-06 1999-11-30 Advanced Micro Devices, Inc. Method of forming a high conductivity metal interconnect using metal gettering plug and system performing the method
US6365514B1 (en) 1997-12-23 2002-04-02 Intel Corporation Two chamber metal reflow process
US6307267B1 (en) * 1997-12-26 2001-10-23 Kabushiki Kaisha Toshiba Semiconductor device and manufacturing method thereof
US5994213A (en) * 1998-02-09 1999-11-30 Taiwan Semiconductor Manufacturing Company, Ltd. Aluminum plug process
US6130156A (en) * 1998-04-01 2000-10-10 Texas Instruments Incorporated Variable doping of metal plugs for enhanced reliability
KR20000004358A (ko) * 1998-06-30 2000-01-25 김영환 반도체 소자의 배선 구조
US6274486B1 (en) * 1998-09-02 2001-08-14 Micron Technology, Inc. Metal contact and process
US6207568B1 (en) * 1998-11-27 2001-03-27 Taiwan Semiconductor Manufacturing Company Ionized metal plasma (IMP) method for forming (111) oriented aluminum containing conductor layer
TW409356B (en) * 1999-03-11 2000-10-21 United Microelectronics Corp Manufacture method of inner connects
US6627542B1 (en) * 1999-07-12 2003-09-30 Applied Materials, Inc. Continuous, non-agglomerated adhesion of a seed layer to a barrier layer
US6080657A (en) * 1999-07-16 2000-06-27 Taiwan Semiconductor Manufacturing Company Method of reducing AlCu hillocks
KR100434188B1 (ko) * 2001-08-28 2004-06-04 삼성전자주식회사 장벽 금속층 적층 방법
US6943105B2 (en) * 2002-01-18 2005-09-13 International Business Machines Corporation Soft metal conductor and method of making
KR100455380B1 (ko) * 2002-02-27 2004-11-06 삼성전자주식회사 다층 배선 구조를 구비한 반도체 소자 및 그 제조 방법
US7056820B2 (en) * 2003-11-20 2006-06-06 International Business Machines Corporation Bond pad
JP2011091242A (ja) * 2009-10-23 2011-05-06 Elpida Memory Inc 半導体装置の製造方法
US9941160B2 (en) * 2013-07-25 2018-04-10 Globalfoundries Singapore Pte. Ltd. Integrated circuits having device contacts and methods for fabricating the same
KR101550526B1 (ko) * 2014-02-21 2015-09-04 에스티에스반도체통신 주식회사 클러스터형 반도체 제조장치 및 이를 이용한 반도체 소자 제조방법
JP2017183396A (ja) * 2016-03-29 2017-10-05 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0430403A2 (fr) * 1989-11-30 1991-06-05 STMicroelectronics, Inc. Méthode de fabrication des contacts intercalés
EP0483669A2 (fr) * 1990-10-24 1992-05-06 Sumitomo Metal Industries, Ltd. Procédé de formation d'une couche mince et dispositifs semiconducteurs
EP0488628A2 (fr) * 1990-11-30 1992-06-03 STMicroelectronics, Inc. Méthode de fabrication d'un trou de liaison/contact empilées en aluminium pour des interconnexions à multi-couches
EP0499241A1 (fr) * 1991-02-12 1992-08-19 Applied Materials, Inc. Procédé de pulvérisation d'une couche d'aluminium sur des plaquettes échelonnées
EP0512296A1 (fr) * 1991-04-19 1992-11-11 Siemens Aktiengesellschaft Procédé de dépôt, à haute temperature, de conducteurs dans des trous plus profonds que larges
EP0514103A1 (fr) * 1991-05-14 1992-11-19 STMicroelectronics, Inc. Procédé de fabrication d'une barrière en métal pour contacts sous-micromiques

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH069199B2 (ja) * 1984-07-18 1994-02-02 株式会社日立製作所 配線構造体およびその製造方法
US4960732A (en) * 1987-02-19 1990-10-02 Advanced Micro Devices, Inc. Contact plug and interconnect employing a barrier lining and a backfilled conductor material
EP0319347B1 (fr) * 1987-12-04 1994-08-03 Research Development Corporation of Japan Dispositif de dépôt sous vide
JPH01160036A (ja) * 1987-12-17 1989-06-22 Oki Electric Ind Co Ltd 半導体装置
US4837183A (en) * 1988-05-02 1989-06-06 Motorola Inc. Semiconductor device metallization process
FR2634317A1 (fr) * 1988-07-12 1990-01-19 Philips Nv Procede pour fabriquer un dispositif semiconducteur ayant au moins un niveau de prise de contact a travers des ouvertures de contact de petites dimensions
US4994162A (en) * 1989-09-29 1991-02-19 Materials Research Corporation Planarization method
US5108951A (en) * 1990-11-05 1992-04-28 Sgs-Thomson Microelectronics, Inc. Method for forming a metal contact
US5240880A (en) * 1992-05-05 1993-08-31 Zilog, Inc. Ti/TiN/Ti contact metallization

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0430403A2 (fr) * 1989-11-30 1991-06-05 STMicroelectronics, Inc. Méthode de fabrication des contacts intercalés
EP0483669A2 (fr) * 1990-10-24 1992-05-06 Sumitomo Metal Industries, Ltd. Procédé de formation d'une couche mince et dispositifs semiconducteurs
EP0488628A2 (fr) * 1990-11-30 1992-06-03 STMicroelectronics, Inc. Méthode de fabrication d'un trou de liaison/contact empilées en aluminium pour des interconnexions à multi-couches
EP0499241A1 (fr) * 1991-02-12 1992-08-19 Applied Materials, Inc. Procédé de pulvérisation d'une couche d'aluminium sur des plaquettes échelonnées
EP0512296A1 (fr) * 1991-04-19 1992-11-11 Siemens Aktiengesellschaft Procédé de dépôt, à haute temperature, de conducteurs dans des trous plus profonds que larges
EP0514103A1 (fr) * 1991-05-14 1992-11-19 STMicroelectronics, Inc. Procédé de fabrication d'une barrière en métal pour contacts sous-micromiques

Also Published As

Publication number Publication date
DE4400726A1 (de) 1995-02-23
KR950006997A (ko) 1995-03-21
KR100291284B1 (ko) 2001-11-30
FR2709207B1 (fr) 1996-10-25
JPH0766205A (ja) 1995-03-10
US5356836A (en) 1994-10-18

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