FR2375720A1 - Procede de fabrication de circuits integres - Google Patents
Procede de fabrication de circuits integresInfo
- Publication number
- FR2375720A1 FR2375720A1 FR7739314A FR7739314A FR2375720A1 FR 2375720 A1 FR2375720 A1 FR 2375720A1 FR 7739314 A FR7739314 A FR 7739314A FR 7739314 A FR7739314 A FR 7739314A FR 2375720 A1 FR2375720 A1 FR 2375720A1
- Authority
- FR
- France
- Prior art keywords
- stripper
- windows
- manufacturing process
- integrated circuits
- grooves
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/764—Air gaps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
- H01L21/76205—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region
- H01L21/7621—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region the recessed region having a shape other than rectangular, e.g. rounded or oblique shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
- H01L21/76213—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose
- H01L21/76216—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose introducing electrical active impurities in the local oxidation region for the sole purpose of creating channel stoppers
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
- Semiconductor Integrated Circuits (AREA)
- Weting (AREA)
- Drying Of Semiconductors (AREA)
- Bipolar Transistors (AREA)
Abstract
Ce procédé est caractérisé en ce qu'on dispose un masque résistant au décapant 22 dans lequel sont ménagées des fenêtres 24, 30 sur une surface 14 d'un corps semiconducteur et on forme par décapage des rainures d'isolation 32 dans le corps en mettant un décapant anisotrope en contact avec des parties de la surface exposée par les fenêtres afin de former des rainures componant des parois latérales 34 qui coupent la surface suivant des angles aigus et en mettant un decapant isotrope en contact avec les parois des rainures décapées qui sont exposées par les fenêtres afin d'enlever par décapage des parties du corps semiconducteur qui sont situées en dessous du masque résistant.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US75472376A | 1976-12-27 | 1976-12-27 |
Publications (2)
Publication Number | Publication Date |
---|---|
FR2375720A1 true FR2375720A1 (fr) | 1978-07-21 |
FR2375720B1 FR2375720B1 (fr) | 1982-07-30 |
Family
ID=25036034
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR7739314A Granted FR2375720A1 (fr) | 1976-12-27 | 1977-12-27 | Procede de fabrication de circuits integres |
Country Status (7)
Country | Link |
---|---|
US (1) | US4155783A (fr) |
JP (1) | JPS5383585A (fr) |
CA (1) | CA1090006A (fr) |
DE (1) | DE2758283C2 (fr) |
FR (1) | FR2375720A1 (fr) |
GB (1) | GB1548778A (fr) |
IT (1) | IT1090820B (fr) |
Families Citing this family (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5572052A (en) * | 1978-11-27 | 1980-05-30 | Fujitsu Ltd | Preparation of semiconductor device |
US4677456A (en) * | 1979-05-25 | 1987-06-30 | Raytheon Company | Semiconductor structure and manufacturing method |
US4289550A (en) * | 1979-05-25 | 1981-09-15 | Raytheon Company | Method of forming closely spaced device regions utilizing selective etching and diffusion |
US4255212A (en) * | 1979-07-02 | 1981-03-10 | The Regents Of The University Of California | Method of fabricating photovoltaic cells |
GB2115609B (en) * | 1982-02-25 | 1986-04-30 | Raytheon Co | Semiconductor structure manufacturing method |
JPH073858B2 (ja) * | 1984-04-11 | 1995-01-18 | 株式会社日立製作所 | 半導体装置の製造方法 |
US4824795A (en) * | 1985-12-19 | 1989-04-25 | Siliconix Incorporated | Method for obtaining regions of dielectrically isolated single crystal silicon |
JPS6327188U (fr) * | 1986-08-05 | 1988-02-23 | ||
US5399901A (en) * | 1994-04-20 | 1995-03-21 | General Instrument Corp. | Semiconductor devices having a mesa structure and method of fabrication for improved surface voltage breakdown characteristics |
US6822332B2 (en) * | 2002-09-23 | 2004-11-23 | International Business Machines Corporation | Fine line circuitization |
TWI404136B (zh) * | 2010-04-13 | 2013-08-01 | Univ Nat Taipei Technology | 製作底切蝕刻微結構的製程方法 |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3725160A (en) * | 1970-12-30 | 1973-04-03 | Texas Instruments Inc | High density integrated circuits |
US3801390A (en) * | 1970-12-28 | 1974-04-02 | Bell Telephone Labor Inc | Preparation of high resolution shadow masks |
US3901737A (en) * | 1974-02-15 | 1975-08-26 | Signetics Corp | Method for forming a semiconductor structure having islands isolated by moats |
US3920482A (en) * | 1974-03-13 | 1975-11-18 | Signetics Corp | Method for forming a semiconductor structure having islands isolated by adjacent moats |
US3966514A (en) * | 1975-06-30 | 1976-06-29 | Ibm Corporation | Method for forming dielectric isolation combining dielectric deposition and thermal oxidation |
US3986200A (en) * | 1974-01-02 | 1976-10-12 | Signetics Corporation | Semiconductor structure and method |
US4056413A (en) * | 1975-10-06 | 1977-11-01 | Hitachi, Ltd. | Etching method for flattening a silicon substrate utilizing an anisotropic alkali etchant |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3716425A (en) * | 1970-08-24 | 1973-02-13 | Motorola Inc | Method of making semiconductor devices through overlapping diffusions |
US3748187A (en) * | 1971-08-03 | 1973-07-24 | Hughes Aircraft Co | Self-registered doped layer for preventing field inversion in mis circuits |
US3796612A (en) * | 1971-08-05 | 1974-03-12 | Scient Micro Syst Inc | Semiconductor isolation method utilizing anisotropic etching and differential thermal oxidation |
JPS4984380A (fr) * | 1972-12-19 | 1974-08-13 | ||
US4047195A (en) * | 1973-11-12 | 1977-09-06 | Scientific Micro Systems, Inc. | Semiconductor structure |
JPS5289484A (en) * | 1975-04-25 | 1977-07-27 | Toyo Dengu Seisakushiyo Kk | Semiconductor ic device |
US3961999A (en) * | 1975-06-30 | 1976-06-08 | Ibm Corporation | Method for forming recessed dielectric isolation with a minimized "bird's beak" problem |
DE2529598C3 (de) * | 1975-07-02 | 1978-05-24 | Siemens Ag, 1000 Berlin Und 8000 Muenchen | Verfahren zur Herstellung einer monolithisch integrierten Halbleiterschaltung mit bipolaren Transistoren |
US4066473A (en) * | 1976-07-15 | 1978-01-03 | Fairchild Camera And Instrument Corporation | Method of fabricating high-gain transistors |
-
1977
- 1977-12-02 CA CA292,266A patent/CA1090006A/fr not_active Expired
- 1977-12-12 GB GB51660/77A patent/GB1548778A/en not_active Expired
- 1977-12-16 IT IT52255/77A patent/IT1090820B/it active
- 1977-12-27 FR FR7739314A patent/FR2375720A1/fr active Granted
- 1977-12-27 DE DE2758283A patent/DE2758283C2/de not_active Expired
- 1977-12-27 JP JP15855677A patent/JPS5383585A/ja active Granted
-
1978
- 1978-05-08 US US05/903,433 patent/US4155783A/en not_active Expired - Lifetime
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3801390A (en) * | 1970-12-28 | 1974-04-02 | Bell Telephone Labor Inc | Preparation of high resolution shadow masks |
US3725160A (en) * | 1970-12-30 | 1973-04-03 | Texas Instruments Inc | High density integrated circuits |
US3986200A (en) * | 1974-01-02 | 1976-10-12 | Signetics Corporation | Semiconductor structure and method |
US3901737A (en) * | 1974-02-15 | 1975-08-26 | Signetics Corp | Method for forming a semiconductor structure having islands isolated by moats |
US3920482A (en) * | 1974-03-13 | 1975-11-18 | Signetics Corp | Method for forming a semiconductor structure having islands isolated by adjacent moats |
US3966514A (en) * | 1975-06-30 | 1976-06-29 | Ibm Corporation | Method for forming dielectric isolation combining dielectric deposition and thermal oxidation |
US4056413A (en) * | 1975-10-06 | 1977-11-01 | Hitachi, Ltd. | Etching method for flattening a silicon substrate utilizing an anisotropic alkali etchant |
Also Published As
Publication number | Publication date |
---|---|
DE2758283A1 (de) | 1978-07-06 |
FR2375720B1 (fr) | 1982-07-30 |
GB1548778A (en) | 1979-07-18 |
JPS6123657B2 (fr) | 1986-06-06 |
JPS5383585A (en) | 1978-07-24 |
DE2758283C2 (de) | 1986-06-12 |
CA1090006A (fr) | 1980-11-18 |
US4155783A (en) | 1979-05-22 |
IT1090820B (it) | 1985-06-26 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
ST | Notification of lapse |