ES2191689T3 - Entrelazador convolucional con requisitos reducidos de memoria, y generador de direcciones para este. - Google Patents

Entrelazador convolucional con requisitos reducidos de memoria, y generador de direcciones para este.

Info

Publication number
ES2191689T3
ES2191689T3 ES95106635T ES95106635T ES2191689T3 ES 2191689 T3 ES2191689 T3 ES 2191689T3 ES 95106635 T ES95106635 T ES 95106635T ES 95106635 T ES95106635 T ES 95106635T ES 2191689 T3 ES2191689 T3 ES 2191689T3
Authority
ES
Spain
Prior art keywords
cell
cells
symbol
symbols
location
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
ES95106635T
Other languages
English (en)
Inventor
Zheng Huang
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Arris Technology Inc
Original Assignee
Arris Technology Inc
General Instrument Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Arris Technology Inc, General Instrument Corp filed Critical Arris Technology Inc
Application granted granted Critical
Publication of ES2191689T3 publication Critical patent/ES2191689T3/es
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
    • H03M13/2782—Interleaver implementations, which reduce the amount of required interleaving memory
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
    • H03M13/2732—Convolutional interleaver; Interleavers using shift-registers or delay lines like, e.g. Ramsey type interleaver
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
    • H03M13/276—Interleaving address generation

Landscapes

  • Physics & Mathematics (AREA)
  • Probability & Statistics with Applications (AREA)
  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Error Detection And Correction (AREA)
  • Detection And Correction Of Errors (AREA)
  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Detection And Prevention Of Errors In Transmission (AREA)

Abstract

UN INTERCALADOR CONVOLUCIONAL Y ESQUEMA DE LOCALIZACION. HASTA B SIMBOLOS CONSECUTIVOS QUE CONTIENEN ERRORES PUEDEN SER INTERCALADOS DE MANERA QUE SEAN SEPARADOS ENTRE SI POR, AL MENOS, N SIMBOLOS INVOLUCRADOS. UNA MEMORIA, COMO RAM, ES CONFIGURADA PARA PROPORCIONAR CELULAS (B-1) DE TAMAÑO CRECIENTE PARA ALMACENAR SIMBOLOS DE UNA FLUJO DE DATOS. UNA PRIMERA DE LAS CELULAS (CELULA 1) TIENE LOCALIZACIONES DE ALMACENAMIENTO ADAPTADAS PARA ALMACENAR M SIMBOLOS. CADA UNA DE LAS CELULAS SUCESIVAS (CELULA 2, CELULA 3) TIENE M LOCALIZACIONES DE ALMACENAMIENTO MAS QUE LA CELULA INMEDIATAMENTE PRECEDENTE PARA ALMACENAR M SIMBOLOS MAS QUE LA CELULA INMEDIATAMENTE PRECEDENTE, DONDE M = N/B. LAS CELULAS SON LOCALIZADAS SUCESIVAMENTE PARA REGISTRAR UN SIMBOLO SIGUIENTE DEL FLUJO A UNA LOCALIZACION DE SIMBOLOS DE REGISTRO SIGUIENTE EN UNA CELULA ACTUALMENTE LOCALIZADA Y PARA LEER UN SIMBOLO DE LOCALIZACION DE LA CELULA ACTUALMENTE LOCALIZADA, SIGUIENDO INMEDIATAMENTE LA LOCALIZACION DE SIMBOLO DE REGISTROSIGUIENTE. SE ACCEDE A LAS LOCALIZACIONES EN UNA PRIMERA MANERA DE ROTACION, DE FORMA QUE LA ULTIMA LOCALIZACION EN LA CELULA ES SEGUIDA POR LA PRIMERA LOCALIZACION EN ESA CELULA. LAS CELULAS SON LOCALIZADAS EN UNA SEGUNDA FORMA ROTATORIA DE MANERA QUE LA CELULA (B-1) , ES SEGUIDA POR UNA PRIMERA CELULA O VICEVERSA. UN PASO DE TRANSFERENCIA INVOLUCRADA, PUEDE SER PROPORCIONADO DENTRO DE EL RAM ENTRE LA CELULA (B-1) LA PRIMERA CELULA PARA TRANSFERIR DIRECTAMENTE EL SIGUIENTE SIMBOLO A LA SALIDA DEL INTERCALADOR. CADA SIMBOLO CONSECUTIVO DEL FLUJO ES REGISTRADO EN UNA DE LAS CELULAS CONSECUTIVAS SIGUIENTES. SE PROPORCIONA UN DESINTERCALADOR QUE TIENE LA MISMA ESTRUCTURA.
ES95106635T 1994-05-04 1995-05-03 Entrelazador convolucional con requisitos reducidos de memoria, y generador de direcciones para este. Expired - Lifetime ES2191689T3 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/238,259 US5537420A (en) 1994-05-04 1994-05-04 Convolutional interleaver with reduced memory requirements and address generator therefor

Publications (1)

Publication Number Publication Date
ES2191689T3 true ES2191689T3 (es) 2003-09-16

Family

ID=22897141

Family Applications (1)

Application Number Title Priority Date Filing Date
ES95106635T Expired - Lifetime ES2191689T3 (es) 1994-05-04 1995-05-03 Entrelazador convolucional con requisitos reducidos de memoria, y generador de direcciones para este.

Country Status (12)

Country Link
US (1) US5537420A (es)
EP (1) EP0681373B1 (es)
JP (1) JP3634004B2 (es)
KR (1) KR100362090B1 (es)
AT (1) ATE232337T1 (es)
AU (1) AU683355B2 (es)
CA (1) CA2148199C (es)
DE (1) DE69529546T2 (es)
DK (1) DK0681373T3 (es)
ES (1) ES2191689T3 (es)
NO (1) NO315886B1 (es)
TW (1) TW245862B (es)

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KR100248396B1 (ko) * 1997-10-24 2000-03-15 정선종 병렬 길쌈 부호화기를 사용한 채널 부호기 설계방법
KR100556469B1 (ko) * 1998-01-12 2006-04-21 엘지전자 주식회사 인터리브/디인터리브 장치
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US6178530B1 (en) 1998-04-24 2001-01-23 Lucent Technologies Inc. Addressing scheme for convolutional interleaver/de-interleaver
EP1304810B1 (en) * 1998-04-27 2007-02-28 Matsushita Electric Industrial Co., Ltd. Convolutional interleaving method
JP4081875B2 (ja) * 1998-09-08 2008-04-30 ソニー株式会社 符号化装置および方法、復号装置および方法、並びに提供媒体
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US6278715B1 (en) * 1998-11-05 2001-08-21 Qualcom Incorporated System and method for reducing deinterleaver memory requirements through chunk allocation
KR100306282B1 (ko) * 1998-12-10 2001-11-02 윤종용 통신시스템의인터리빙/디인터리빙장치및방법
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Also Published As

Publication number Publication date
AU1784995A (en) 1995-11-09
NO315886B1 (no) 2003-11-03
KR950035112A (ko) 1995-12-30
DK0681373T3 (da) 2003-05-26
US5537420A (en) 1996-07-16
CA2148199A1 (en) 1995-11-05
NO951715D0 (no) 1995-05-03
NO951715L (no) 1995-11-06
TW245862B (en) 1995-04-21
KR100362090B1 (ko) 2003-02-05
EP0681373B1 (en) 2003-02-05
JP3634004B2 (ja) 2005-03-30
EP0681373A3 (en) 1996-10-16
DE69529546T2 (de) 2004-02-19
ATE232337T1 (de) 2003-02-15
CA2148199C (en) 2000-11-21
AU683355B2 (en) 1997-11-06
EP0681373A2 (en) 1995-11-08
DE69529546D1 (de) 2003-03-13
JPH0865177A (ja) 1996-03-08

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