ES2143862T3 - Disposicion de circuito con un circuito de prueba. - Google Patents

Disposicion de circuito con un circuito de prueba.

Info

Publication number
ES2143862T3
ES2143862T3 ES97920550T ES97920550T ES2143862T3 ES 2143862 T3 ES2143862 T3 ES 2143862T3 ES 97920550 T ES97920550 T ES 97920550T ES 97920550 T ES97920550 T ES 97920550T ES 2143862 T3 ES2143862 T3 ES 2143862T3
Authority
ES
Spain
Prior art keywords
bln
group
wlm
blm
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
ES97920550T
Other languages
English (en)
Inventor
Thomas Zettler
Diether Sommer
Georg Georgakos
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Original Assignee
Siemens AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG filed Critical Siemens AG
Application granted granted Critical
Publication of ES2143862T3 publication Critical patent/ES2143862T3/es
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS

Abstract

LA INVENCION ESTA RELACIONADA CON UN DISPOSITIVO DE CIRCUITO CON UN NUMERO PREDETERMINADO DE LINEAS EN GRUPO (WLO, ..., WLM, BLO, ..., BLM) CONFIGURADAS PARALELA Y REGULARMENTE EN UN SUBSTRATO SEMICONDUCTOR (26), EN LAS QUE SE CONECTAN UN GRAN NUMERO DE CIRCUITOS ELEMENTALES ELECTRONICOS (7) CONFIGURADOS EN EL SUBSTRATO SEMICONDUCTOR (26) Y, FUNDAMENTALMENTE, DEL MISMO TIPO, ESTANDO PREVISTO UN CIRCUITO DE PRUEBA PARA LA COMPROBACION DEL FUNCIONAMIENTO ELECTRONICO DE LOS CIRCUITOS ELEMENTALES (7) Y/O DE LAS LINEAS EN GRUPO (WLO, ..., WLM, BLO, ..., BLM) QUE TAMBIEN SE REALIZA INTEGRADO EN EL SUBSTRATO SEMICONDUCTOR (26) DE LA DISPOSICION DE CIRCUITO Y QUE PRESENTA UN DISPOSITIVO DE CONEXION (30) ASIGNADO A LAS LINEAS EN GRUPO (WLO, ..., WLM, BLO, ..., BLM), POR MEDIO DEL CUAL ES POSIBLE SOLICITAR, AL MENOS UNA LINEA EN GRUPO PREDETERMINADA (WLN, BLN) CON UNA PRIMERA SEÑAL DE PRUEBA Y OTRA LINEA EN GRUPO (WLN'', BLN'', N''=N-1, N''=N+1) DISPUESTA DIRECTAMENTE ADYACENTE FRENTE A LA LINEA EN GRUPO(WLN, BLN) PREDETERMINADA CON UNA SEGUNDA SEÑAL DE PRUEBA QUE, FRENTE A LA PRIMERA SEÑAL DE PRUEBA, PRESENTA UN NIVEL DE PRUEBA DIFERENTE, Y ESTANDO PREVISTO UN DISPOSITIVO DE DETECCION (31) ASIGNADO A LAS LINEAS EN GRUPO (WLO, ..., WLM, BLO, ..., BLM) QUE REGISTRA UNA SEÑAL DE SALIDA DERIVADA DE LAS LINEAS EN GRUPO (WLN, BLN O WLN'', BLN'') SOMETIDAS A LA PRIMERA O LA SEGUNDA SEÑAL DE PRUEBA.
ES97920550T 1996-03-28 1997-03-26 Disposicion de circuito con un circuito de prueba. Expired - Lifetime ES2143862T3 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19612441A DE19612441C2 (de) 1996-03-28 1996-03-28 Schaltungsanordnung mit einer Testschaltung

Publications (1)

Publication Number Publication Date
ES2143862T3 true ES2143862T3 (es) 2000-05-16

Family

ID=7789784

Family Applications (1)

Application Number Title Priority Date Filing Date
ES97920550T Expired - Lifetime ES2143862T3 (es) 1996-03-28 1997-03-26 Disposicion de circuito con un circuito de prueba.

Country Status (10)

Country Link
EP (1) EP0891623B1 (es)
JP (1) JP3267301B2 (es)
KR (1) KR20000005054A (es)
CN (1) CN1218572A (es)
AT (1) ATE189849T1 (es)
BR (1) BR9708454A (es)
DE (2) DE19612441C2 (es)
ES (1) ES2143862T3 (es)
RU (1) RU2183361C2 (es)
WO (1) WO1997037357A1 (es)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE69937559T2 (de) 1999-09-10 2008-10-23 Stmicroelectronics S.R.L., Agrate Brianza Nicht-flüchtige Speicher mit Erkennung von Kurzschlüssen zwischen Wortleitungen
DE50106894D1 (de) 2000-03-10 2005-09-01 Infineon Technologies Ag Test-schaltungsanordnung und verfahren zum testen einer vielzahl von elektrischen komponenten
DE10245152B4 (de) * 2002-09-27 2013-10-10 Infineon Technologies Ag Integrierte Testschaltungsanordnung und Testverfahren
JP2009076176A (ja) * 2007-09-25 2009-04-09 Toshiba Corp 不揮発性半導体記憶装置
JP5651292B2 (ja) * 2008-04-24 2015-01-07 ピーエスフォー ルクスコ エスエイアールエルＰＳ４ Ｌｕｘｃｏ Ｓ．ａ．ｒ．ｌ． 半導体記憶装置及びそのテスト方法
JP5635924B2 (ja) * 2011-02-22 2014-12-03 ピーエスフォー ルクスコ エスエイアールエルＰＳ４ Ｌｕｘｃｏ Ｓ．ａ．ｒ．ｌ． 半導体装置及びその試験方法
CN102768815B (zh) * 2012-07-23 2015-04-08 京东方科技集团股份有限公司 Dds检测结构及检测方法
CN109932633A (zh) * 2017-12-18 2019-06-25 致伸科技股份有限公司 电路板的测试系统

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4595875A (en) * 1983-12-22 1986-06-17 Monolithic Memories, Incorporated Short detector for PROMS
JPS62157400A (ja) * 1985-12-27 1987-07-13 Fujitsu Ltd 半導体記憶回路
JPH0752597B2 (ja) * 1989-10-30 1995-06-05 三菱電機株式会社 半導体メモリ装置
US5181205A (en) * 1990-04-10 1993-01-19 National Semiconductor Corporation Short circuit detector circuit for memory arrays
JP2647546B2 (ja) * 1990-10-11 1997-08-27 シャープ株式会社 半導体記憶装置のテスト方法
KR950000305Y1 (ko) * 1991-12-23 1995-01-16 금성일렉트론 주식회사 메모리 장치의 테스트 모드회로
JP2978329B2 (ja) * 1992-04-21 1999-11-15 三菱電機株式会社 半導体メモリ装置及びそのビット線の短絡救済方法

Also Published As

Publication number Publication date
DE59701136D1 (de) 2000-03-23
BR9708454A (pt) 1999-04-13
EP0891623A1 (de) 1999-01-20
CN1218572A (zh) 1999-06-02
RU2183361C2 (ru) 2002-06-10
WO1997037357A1 (de) 1997-10-09
JPH11507166A (ja) 1999-06-22
DE19612441C2 (de) 1998-04-09
JP3267301B2 (ja) 2002-03-18
KR20000005054A (ko) 2000-01-25
DE19612441A1 (de) 1997-10-02
EP0891623B1 (de) 2000-02-16
ATE189849T1 (de) 2000-03-15

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