ES2123543T3 - Procedimiento de fabricacion de una ventana de contacto auto-alineable en circuitos integrados. - Google Patents

Procedimiento de fabricacion de una ventana de contacto auto-alineable en circuitos integrados.

Info

Publication number
ES2123543T3
ES2123543T3 ES92311252T ES92311252T ES2123543T3 ES 2123543 T3 ES2123543 T3 ES 2123543T3 ES 92311252 T ES92311252 T ES 92311252T ES 92311252 T ES92311252 T ES 92311252T ES 2123543 T3 ES2123543 T3 ES 2123543T3
Authority
ES
Spain
Prior art keywords
self
integrated circuits
manufacturing procedure
contact window
aligning contact
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
ES92311252T
Other languages
English (en)
Spanish (es)
Inventor
Kuo-Hua Lee
Chen-Hua Douglas Yu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
AT&T Corp
Original Assignee
AT&T Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by AT&T Corp filed Critical AT&T Corp
Application granted granted Critical
Publication of ES2123543T3 publication Critical patent/ES2123543T3/es
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
ES92311252T 1991-12-30 1992-12-10 Procedimiento de fabricacion de una ventana de contacto auto-alineable en circuitos integrados. Expired - Lifetime ES2123543T3 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/815,316 US5880022A (en) 1991-12-30 1991-12-30 Self-aligned contact window

Publications (1)

Publication Number Publication Date
ES2123543T3 true ES2123543T3 (es) 1999-01-16

Family

ID=25217437

Family Applications (1)

Application Number Title Priority Date Filing Date
ES92311252T Expired - Lifetime ES2123543T3 (es) 1991-12-30 1992-12-10 Procedimiento de fabricacion de una ventana de contacto auto-alineable en circuitos integrados.

Country Status (5)

Country Link
US (1) US5880022A (cg-RX-API-DMAC7.html)
EP (1) EP0550174B1 (cg-RX-API-DMAC7.html)
JP (1) JPH05259182A (cg-RX-API-DMAC7.html)
DE (1) DE69227438T2 (cg-RX-API-DMAC7.html)
ES (1) ES2123543T3 (cg-RX-API-DMAC7.html)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6103612A (en) * 1998-09-02 2000-08-15 Micron Technology, Inc. Isolated interconnect studs and method for forming the same
US6767797B2 (en) 2002-02-01 2004-07-27 Agere Systems Inc. Method of fabricating complementary self-aligned bipolar transistors
JP2004200400A (ja) * 2002-12-18 2004-07-15 Toshiba Corp 半導体装置およびその製造方法
US7169676B1 (en) * 2005-05-23 2007-01-30 Advanced Micro Devices, Inc. Semiconductor devices and methods for forming the same including contacting gate to source

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57130461A (en) * 1981-02-06 1982-08-12 Hitachi Ltd Semiconductor memory storage
JP2681887B2 (ja) * 1987-03-06 1997-11-26 シ−メンス、アクチエンゲゼルシヤフト ３次元１トランジスタメモリセル構造とその製法
US4844776A (en) * 1987-12-04 1989-07-04 American Telephone And Telegraph Company, At&T Bell Laboratories Method for making folded extended window field effect transistor
US4944682A (en) * 1988-10-07 1990-07-31 International Business Machines Corporation Method of forming borderless contacts
US5026666A (en) * 1989-12-28 1991-06-25 At&T Bell Laboratories Method of making integrated circuits having a planarized dielectric
US4981810A (en) * 1990-02-16 1991-01-01 Micron Technology, Inc. Process for creating field effect transistors having reduced-slope, staircase-profile sidewall spacers
US4996167A (en) * 1990-06-29 1991-02-26 At&T Bell Laboratories Method of making electrical contacts to gate structures in integrated circuits
US5037777A (en) * 1990-07-02 1991-08-06 Motorola Inc. Method for forming a multi-layer semiconductor device using selective planarization
KR920003461A (ko) * 1990-07-30 1992-02-29 김광호 접촉영역 형성방법 및 그를 이용한 반도체장치의 제조방법
US4997790A (en) * 1990-08-13 1991-03-05 Motorola, Inc. Process for forming a self-aligned contact structure
US5049517A (en) * 1990-11-07 1991-09-17 Micron Technology, Inc. Method for formation of a stacked capacitor
US5114879A (en) * 1990-11-30 1992-05-19 Texas Instruments Incorporated Method of forming a microelectronic contact
US5084405A (en) * 1991-06-07 1992-01-28 Micron Technology, Inc. Process to fabricate a double ring stacked cell structure
EP0540276B1 (en) * 1991-10-31 1997-09-24 STMicroelectronics, Inc. A self-aligned contact process
US5200358A (en) * 1991-11-15 1993-04-06 At&T Bell Laboratories Integrated circuit with planar dielectric layer

Also Published As

Publication number Publication date
DE69227438D1 (de) 1998-12-03
HK1003460A1 (en) 1998-10-30
EP0550174B1 (en) 1998-10-28
JPH05259182A (ja) 1993-10-08
EP0550174A3 (cg-RX-API-DMAC7.html) 1994-01-12
EP0550174A2 (en) 1993-07-07
US5880022A (en) 1999-03-09
DE69227438T2 (de) 1999-05-06

Similar Documents

Publication Publication Date Title
ES8704036A1 (es) Procedimiento para la produccion de un contacto electrico a una region subyacente en dispositivos semiconductores
KR940016837A (ko) 반도체 기억장치 및 그의 제조방법
KR840006873A (ko) 반도체 메모리
EP0315229A3 (en) Method of manufacturing a semiconductor device with insulated-gate structure
KR890011110A (ko) 집적회로 제조방법
KR960024604A (ko) 이중 채널 박막트랜지스터 및 그 제조방법
KR900019234A (ko) 반도체기억장치
KR860008617A (ko) 자기정합된 바이폴라 트랜지스터의 제조방법
KR900003967A (ko) 반도체 장치 및 그 제조 방법
ES2123543T3 (es) Procedimiento de fabricacion de una ventana de contacto auto-alineable en circuitos integrados.
ES8800512A1 (es) Procedimiento para hacer un dispositivo transistor mos.
KR970072204A (ko) 적어도 하나의 mos 트랜지스터를 가지는 회로 장치 및 그것의 제조방법
KR910008861A (ko) 집적회로소자
KR920008938A (ko) 스택캐패시터 및 그제조방법
GB2016803A (en) Thin film transistor construction and manufacturing method of the same
KR970054180A (ko) 반도체소자 및 제조방법
KR870009475A (ko) 반도체 소자 제조방법
KR840005929A (ko) Mos 트랜지스터 집적회로
BE788894A (fr) Couche electriquement conductrice sur base de forte resistivite, procede de fabrication et application d'une telle couchecomme resistance electrique
JPS6457671A (en) Semiconductor device and manufacture thereof
JPS54143076A (en) Semiconductor device and its manufacture
IT979053B (it) Circuito integrato con strati di materiale semiconduttore su un substrato isolante
KR910010748A (ko) 적층형 캐패시터 및 제조방법
KR890004433A (ko) 이중 캐페시터 절연형 디 램 셀의 제조방법
JPS5291382A (en) Insulating gate type field effect transistor

Legal Events

Date Code Title Description
FG2A Definitive protection

Ref document number: 550174

Country of ref document: ES