Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
  • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
  • H01L21/76—Making of isolation regions between components
  • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
  • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
  • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
  • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
  • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering

Definitions

• the invention relates to the production and processing of a structure comprising a Germanium layer on a substrate, such as a Germanium-on-insulator structure (also called “GeOI” structure, of the acronym “Germanium- On-Insulator "), intended for applications in microelectronics (MOS production for example) and / or in optoelectronics (photodetectors for example) and / or photovoltaic applications (solar cells for example) ...
• a GeOI structure comprises said layer of Ge on a layer of electrical insulation on a substrate.
• Germanium has more interesting electrical characteristics than those of silicon, among other things because of a greater mobility of the charges within this material (theoretical mobility of holes at 1900 cm 2 V " V 1 , mobility of electrons, 3900 CmV 1 S '1). it is desirable to realize such a layer of Ge having a good crystal quality, electrical and morphological over the entire surface of the layer based on future applications, to thereafter form therein e.g. transistors or integrated detectors.
• the documents US 6,833,195 and US 2005/0042842 each disclose a GeOI structure manufacturing method, comprising the epitaxy of a Ge layer on a first substrate, the formation of a SiO 2 film on the epitaxial layer of Ge, an ion implantation under the Ge layer to create a zone of weakening, a bonding with a second substrate, then a detachment of the Ge layer at the weakening zone, to finally obtain a GeOI structure (this technique detachment is also known as "Smart Cut ® ").
• the process according to these documents also discloses a strengthening of the bonding (ie a densification of the bonding layer) by heat treatment before detachment at temperatures of 100-150 ° C. for 1 to 60 hours, and a final step of finishing the surface. by using polishing, wet chemical treatment, or etching to correct inhomogeneities and surface roughness.
• Germanium oxide which adversely affects the electrical properties of the Ge layer. This oxidation can in particular take place at the level of the Ge / SiO 2 interface.
• a step of densification of SiO 2 is often necessary.
• the step of densification of the oxide is usually done at about 900 ° C. for transferred Si layers, and can only be partially achieved for the transferred Ge layer (or for periods inconsistent with the requirements of industrial production).
• a second problem encountered in heterostructures with a transferred Ge layer is the need for the transfer to limited temperatures, germanium oxide quickly becoming very volatile (not stable oxidized form) and its melting temperature being relatively low (937 ° C). The temperatures used are thus rapidly limited.
• the thickness damaged after ion implantation of Smart-Cut ® is much larger than in the case of silicon. This is why a heat treatment allowing the crystalline reconstruction (healing of the residual defects of implantation) would be desirable.
• An object of the invention is to obtain a structure comprising a Ge upper layer and an interface with a support substrate both having good crystalline and morphological quality.
• Another object of the invention is to improve the electrical properties of the Ge layer.
• Another objective of the invention is to optimize the electrical quality of the GeOI substrate at the Ge / insulator interface.
• one objective is to maintain good quality electrical, morphological and / or crystalline characteristics for the Ge layer, for microelectronics applications (manufacturing MOS for example), optoelectronics, and / or photovoltaics, etc.
• the invention provides, in a first aspect, a method of processing a structure comprising a thin layer of Ge on a substrate, said layer having been previously bonded to the substrate.
• the method comprises a treatment for improving the electrical properties of the layer and / or the interface of the Ge layer with the underlying layer, characterized in that said treatment is a heat treatment implemented at a temperature between 500 ° C. and 600 ° C. for not more than 3 hours, or more particularly between 525 ° C. and 575 ° C., or more particularly between 525 ° C. and 550 ° C., or more particularly at a temperature of about 550 ° C.
• the heat treatment may also more particularly last about 1 hour and / or be carried out under an inert atmosphere.
• the transferred thin film may have a thickness of less than 1.5 micrometers, preferably between about 50 and about 200 nanometers, and / or the substrate be silicon.
• the Ge layer is the upper layer of the structure, and this upper layer is bonded directly or by the only intermediate of a bonding layer.
• the structure is a GeOI structure, that is to say that it further comprises a layer of electrical insulating material between the thin layer and the substrate.
• the insulating layer may be an oxide, a nitride or an oxynitride or composed of a juxtaposition of different layers of different types.
• the inventors have shown (see below) that the use of such a heat treatment according to the invention not only allows the substantial cure of the Ge layer of existing defects, but also increases the electrical quality of the layer and / or the Ge / insulator interface, in particular by reaching values of "density of traps at the interface" (also called “Dit”, acronym for "Density of Interface Traps"). Acceptable).
• a simple heat treatment could therefore be sufficient to increase the electrical and / or optical quality of a Ge interface, without systematically providing a passivation layer and / or an interfacial layer as disclosed in EP 04292742 (deposit number).
• the structure comprises a passivation layer adjacent to the thin layer and / or an interfacial layer between the thin layer and the rest of the structure, the interfacial layer being made of a material allowing to improve the electrical and / or optical properties at the interface with the Ge.
• the invention provides a method for producing a structure comprising a layer of Ge, the method comprising a bonding between a donor substrate comprising at least in its upper part a thin layer of Ge and a receiving substrate, characterized in that it comprises the following steps:
• the donor substrate can be a solid substrate of Ge or a composite structure comprising at the surface of said epitaxial layer of Ge.
• the receiving substrate may be of any type of material (it may for example comprise solid Si, SiC, SiGe, SiGeC, Ge, GeC, quartz, glass, alloy materials H1-V or H -Vl, etc.).
• the method further comprises, before step (a), the formation of a passivation layer on said Ge layer;
• the passivation layer may be GeOxNy, formed inter alia by one of the following techniques: superficial oxidation of Ge and nitriding of Ge oxide; heat treatment ; plasma treatment using the precursor NH 3 , N 2 , O 2 or an N 2 + O 2 mixture.
• the method further comprises, before step (a), the deposition of an interfacial layer on said Ge layer (or on the passivation layer if there is one), with a material intended to improve the electrical and / or optical properties at the Ge interface, such as epitaxial Si, a high-k (high-k) material, HfO 2 , AlN;
• a material intended to improve the electrical and / or optical properties at the Ge interface such as epitaxial Si, a high-k (high-k) material, HfO 2 , AlN;
• the method further comprises, before step (a), a step of forming an electrical insulator layer on the donor substrate and / or on the receiving substrate, constituted at least in large part by a material such as oxide, SiO 2 , HfO 2 , SrTiO 3 , Ta 2 O 5 , TiO 2 , ZrO 2 , Al 2 O 3 , or Y 2 O 3 , or a nitride or an oxynitride, for example Al, Ge or Si; in the preceding case where the insulating layer is made of SiO 2 , it is formed by one of the following techniques: PECVD deposition for example from silane or from TEOS, thermal oxidation of a Si layer previously deposited on the Ge layer and / or the Si surface of the receiving substrate;
• PECVD deposition for example from silane or from TEOS, thermal oxidation of a Si layer previously deposited on the Ge layer and / or the Si surface of the receiving substrate;
• the formation of the insulating layer is carried out at a temperature of about 500 ° C or less, then optionally a densification step of the insulating layer is implemented by heat treatment below 600 0 C;
• step (b) of the process is carried out by one of the following techniques, taken alone or in combination: polishing, grinding, etching;
• the method further comprises: before step (a), a step of implanting atomic species in the donor substrate so as to form an embrittlement zone at a depth close to the thickness of said layer of Ge; step (b) comprises a supply of energy to break the fragile bonds present at the zone of weakening; the method further comprises, after step (b), a step of finishing the Ge layer so as to improve its thickness homogeneity and its surface roughness, the latter can thus be between about 1 and about 5 RMS angstroms.
• the invention proposes a Ge-on-insulator structure comprising a Ge layer bonded to a substrate via an SiO 2 bonding layer having a trap density at the Ge / SiO interface.
• the structure further comprises a passivation layer and / or interface between the Ge layer and the SiO 2 layer.
• FIGS. 1a to 1g represent different steps of a method of forming a GeOI structure according to the invention.
• FIGS. 2a to 2c respectively represent three photos taken by scanning electron microscopy of three transferred layers of germanium over insulation, after heat treatments at temperatures of 500 ° C., 550 ° C. and 600 ° C., respectively.
• FIGS. 3a and 3b are two diagrams representative of drain-source currents (in Ampere) measured on GeOI structures, as a function of the voltage (in Volts) applied to the support substrate, during a Pseudo-MOS type test - each curve being obtained for an annealing temperature of the different GeOI structure.
• the process for producing a germanium on insulator thin film comprises various steps which will be described precisely below.
• the donor substrate 10 may be a solid Ge substrate, the germanium layer being thus included in the bulk material.
• the donor support 10 is a silicon substrate covered with an epitaxial layer of Ge 15.
• the donor support 10 is a composite structure covered with an epitaxial Ge layer 15.
• the donor substrate 10 may for example be a structure having a solid monocrystalline silicon substrate on which has been formed by epitaxy a buffer structure comprising successive SiGe layers having progressively increasing Ge concentrations at a distance from the substrate, up to the Ge layer.
• the donor substrate 10 may also have, for example, alternations of
• a receiving substrate 20 intended to be subsequently bonded to the donor substrate 10. It may be of any type of material (it may for example comprise solid Si, silicon oxide,
• a layer of electrically insulating material 30 is deposited on the donor substrate 10 and / or on the receiving substrate 20.
• a specific preparation of the germanium can be implemented before the deposition of the insulating layer 30.
• the surface can thus be cleaned with, for example, a solution of HF and / or ozone optionally followed by brushing.
• a passivation of the layer 15 may be made to improve the quality of the interface between the germanium and the insulator with which the layer 15 will be in contact.
• This passivation may optionally have a "hook layer” function to any material subsequently deposited.
• this passivation may be a formation of a thin GeO x Ny layer on the surface of the layer 15, so that the
• Ge is air stable, and to improve the interface qualities.
• This layer is for example formed according to the following different techniques, taken alone or in combination:
• the heat treatments can be conventional treatments, more or less long treatments depending on the thickness involved, but also rapid RTO treatments (from the English acronym “Rapid Thermal Oxidation” meaning “rapid thermal oxidation”), RTN (the English acronym “Rapid Thermal Nitruration” meaning “rapid thermal nitriding”); treatment with plasma using the precursor NH 3 , N 2 , O 2 or an N 2 + O 2 mixture.
• a so-called “interfacial” layer can also be optionally deposited, directly or via the passivation layer, on the germanium layer 15, before the insulating layer 30.
• this interfacial layer are chosen so as to make it possible to improve the quality of the Ge / insulator interface from an electrical, optical, mechanical or other point of view depending on the intended end application. It may be thin or thick, and may consist for example of epitaxially grown silicon, or of a layer with a high dielectric coefficient ("high-k" layer), of a layer of HfO 2 , or of a layer of AlN. Its thickness can thus typically vary from a few ⁇ to a few hundred ⁇ .
• This layer may be formed before or after the implantation step (see FIG. 1d).
• the preparation of the surface of the layer 15 may also be a layer whose composition would be a combination of a material that would be used for a passivation layer and a material that would be used for an interfacial layer.
• the insulating layer 30 is formed on the donor substrate 10 and / or on the receiving substrate 20.
• the insulating layer 30 is formed on the receiving substrate 20.
• an insulating thermal oxide layer may be formed at temperatures typically exceeding 1000 ° C.
• this insulating layer 30 is made on the donor substrate 10, it is advantageously formed at low temperature (less than or equal to approximately 600 ° C., or even less than or equal to approximately 500 ° C.) because of the physical characteristics of the discussed previously.
• layers of deposited silicon oxide for example in the vapor phase, with SiH 4 or TEOS (tetraethylorthosilicate), but also to form layers of different types, namely SiO 2 , HfO 2 , SrTi ⁇ 3 , Ta 2 O 5 , TiO 2 , ZrO 2 , Al 2 O 31 Y 2 O 3 .
• SiH 4 or TEOS tetraethylorthosilicate
• the insulating layer 30 may also be a nitride or oxynitride layer of Al, Ge, Si, or other elements.
• These layers can be deposited on germanium for example by LPCVD (Low Pressure Chemical Vapor Deposition) or by PECVD (Plasma Enhanced Chemical Vapor Deposition).
• the insulating layer thus deposited then advantageously undergoes densification, making it possible to freeze it.
• the densification temperature is a critical temperature because it is limiting. Indeed, all the future steps of the process should not significantly exceed this densification temperature in order to avoid that the structure evolves: a step at a higher temperature could lead to the creation of new constraints in the layer, or a new densification of the layer, or possibly degassing of this layer. This densification temperature is therefore to be taken into account for the rest of the process.
• the deposition temperatures vary from 300 ° C. to 400 ° C.
• the densification which follows the deposition TEOS will be done by heating the structure at about 600 0 C maximum under neutral gas (Ar, N 2 ).
• the densification temperature will be limited by the unstable character of the underlying Ge. This temperature will thus be limited to about 600 ° C.
• a heat treatment for healing the Ge interface may also be performed, before the deposition of the insulating layer, before bonding with the receiving substrate or after the implantation step. This treatment will make it possible to improve the quality of the layer itself but above all to improve the quality of the interface between the interfacial layer and the insulating layer. Cleaning as well as passivation and / or interfacial layer formation can also be envisaged at this point in the process.
• an implantation of atomic species is carried out through a face of the donor substrate 10 in order to create an embrittlement zone 12 in or under the germanium layer 15, preferentially within the Germanium layer.
• the implanted species are rather chosen as being light, such as hydrogen, or helium.
• Co-implantation can also be done by implanting at least two different species.
• the doses applied can vary from 4e16 at / cm 2 to 7e16 at / cm 2 .
• energy it can vary from 40 keV to 250 keV depending on the thickness of germanium that one wants to transfer (between about 1000 A and 1.5 microns) according to the Smart Cut ® process .
• the doses used can vary from 7e16 at / cm 2 to 2e16 at / cm 2 for hydrogen and 3e16 at / cm 2 at 0.5e16 at / cm 2 for helium.
• the ion energy it can vary from 40 to 250 keV, preferably from 70 to 90 keV for hydrogen and from 60 to 250 keV, preferentially from 120 to 140 keV for helium.
• a protective layer (not shown in FIG. 1d) of the layer 15 is preferably formed.
• the protective layer is arranged to be easily removable, and this selectively, with respect to the layer on which it rests.
• an SiO 2 protective layer may be used on an insulating layer of HfO 2 to produce it. This protective layer can then be removed after implantation.
• the donor substrate 10 is bonded to the receiving substrate 20 through the insulating layer 30.
• the insulating layer 30 may also act as a bonding layer. This is particularly the case if an insulating layer 30 made of SiO 2 is used .
• the cleaning of the insulating layer 30 or substrates can be carried out on wet benches, or on single-plate cleaning machines with adaptable chemistry, by liquid chemistry.
• One or more surface preparation treatments for molecular bonding may also be carried out, such as chemical cleaning, chemical mechanical planarization (or CMP), plasma activation, or brushing, or a combination of these treatments.
• a plasma activation can be particularly adapted to the situation since it allows a good bonding without necessarily resorting to high bonding temperatures.
• Such plasma treatment can be done on the receiving substrate 20 before or after cleaning.
• the bonding is done between the donor substrate 10 and the receiving substrate 2.
• Different cases of figures are then presented:
• the bonding interface can be reinforced at temperatures below the detachment temperature, that is to say below 300 0 C (for a conventional hydrogen implantation).
• the layer 15 is detached from the donor substrate 10, bringing enough energy to break the fragile bonds at the weakening zone 12.
• detachment temperatures is closely related to the implantation conditions used (dose, energy, nature of implanted ions, etc.).
• the transfer can be done by heat treatment (advantageously if the layer 15 is an initially epitaxial layer) or by a heat treatment coupled to a mechanical opening (advantageously if the layer 15 is a layer initially comprised in a solid donor substrate).
• the temperatures used for the detachment can vary from 250 0 C to 380 0 C for a period of 15 min to 3h, more particularly 30 min and 1 h, with a ramp of 5 to 10 0 C / min.
• the temperature and the conditions can be adapted according to the conditions of implantation and the nature of the materials to obtain a detachment time compatible with an industrial use.
• a damaged zone 16 remains on the upper part of the layer 15.
• polishing alone or in combination with chemical etching may also be performed.
• a final stage of CMP is advantageously implemented in order to reduce the final roughness of the layer 15.
• the damaged area 16 can be removed by CMP polishing, in order to arrive at a layer of thickness ranging from 500 A to 2000 A and to obtain a final roughness around a few A RMS, typically less than ⁇ A RMS.
• Cleaning can be carried out with for example a solution of HF at 1 - 5
• a GeOI final structure comprising the Ge layer, the insulating layer 30 and the receiving substrate 20, is then obtained.
• an annealing heat treatment of the structure 40 is then carried out, between about 500.degree. 600 ° C., more particularly between 525 ° C. and 575 ° C., more particularly between 525 ° C. and 550 ° C., more particularly about 550 ° C., for 3 hours or less, more particularly for about 1 hour, possibly under a neutral atmosphere (argon or nitrogen), in order to find good electrical and / or optical and crystalline characteristics of the superficial layer 15 of germanium, and in particular good electrical quality at the interface.
• argon or nitrogen argon or nitrogen
• FIGS. 2a to 2c respectively, three photos taken in transmission electron microscopy in layers transferred on a receiving substrate 20, after having undergone said annealing at temperatures of 500 ° C. and 550 ° C. respectively, are represented. and 600 ° C.
• FIGS. 3a to 3b respectively show curves obtained according to the Pseudo-MOS method, for different final annealing temperatures (between 500 ° and 650 ° C.) on respectively two final structure samples 40 obtained by Smart Cut ® , presenting the evolution of the drain-source current (in Ampere) in the layer 15 as a function of the voltage (in volts) applied on the rear face of the substrate 20.
• the Pseudo-MOS method is described in particular in "A Review of the Pseudo-MOS Transistor in SOI Wafers: Operation, Parameter Extraction, and Applications” by S. Cristoloveanu et al. ; IEEE Transactions on Electron Devices, Vol. 47, No. 5, May 2000).
• This method makes it possible to make a rapid evaluation of the electronic properties of a semiconductor-on-insulator plate before any CMOS component fabrication.
• the Ge layer would represent the body of the transistor and the buried insulating layer would then serve as a gate insulator.
• the thick Si substrate plays the role of the gate and is then polarized by a metal support, inducing a conductive channel at the interface between the layer 15 and the insulator 30. According to the polarization of the gate (positive or negative ), an inversion or accumulation channel can be activated.
• the source and drain are formed by applying pressure-controlled probes to the surface of layer 15.
• the temperatures tested for the first sample are 500 ° C., 550 ° C., 600 ° C., 650 ° C.
• the temperatures tested for the second sample are 525 ° C., 550 ° C., 575 ° C., 600 ° C.
• results that can be considered relatively satisfactory have been obtained for temperatures between 500 ° C. and 600 ° C., slightly better between 525 ° C. and 575 ° C., a little better. best between 525 ° C and 550 0 C. The best result was obtained for a temperature of about 525 ° C, but we can extrapolate the fact that an optimal result would be reached for a temperature between 525 0 C and 55O 0 C.
• Table 1 refers to said first sample ( Figure 3a)
• Table 2 refers to said second sample ( Figure 3b).
• the structure is of good quality both at the level of the oxide at the level of the interface.
• the insulation layer and the interface are of lower quality.
• the insulation layer and the interface are of poor quality.
• the Ge layer 15 is then at least partially healed and has improved electrical interface quality.
• a deoxidation step on the rear face of the substrate 20 is carried out. It can be done in liquid phase with a front panel protection or using a single-sided machine. Finally, a final cleaning can be implemented, for example using
• the present invention is not limited to a substrate 10 and 20 of materials IV or IV-IV presented above, but also extends to other types of materials belonging to the atomic families II, III, IV, V or VI and to alloys belonging to the atomic families IV-IV, H1-V, N-VI, on which a layer 15 Ge can be epitaxied (for the donor substrate 10) or glued (for the receiving substrate 20).
• the substrate 10 and / or 20 may comprise intermediate layers of non-conductive or non-semiconductive materials, such as dielectric materials.
• the selected alloys can be binary, ternary, quaternary or higher degree.

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• 2005
  • 2005-10-19 FR FR0510636A patent/FR2892230B1/fr not_active Expired - Fee Related
• 2006
  • 2006-10-17 EP EP06820227A patent/EP1949430A1/fr not_active Withdrawn
  • 2006-10-17 CN CNA2006800388843A patent/CN101292342A/zh active Pending
  • 2006-10-17 JP JP2008536082A patent/JP2009513009A/ja not_active Withdrawn
  • 2006-10-17 WO PCT/FR2006/002332 patent/WO2007045759A1/fr active Application Filing
  • 2006-10-17 US US12/090,318 patent/US20080268615A1/en not_active Abandoned
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