EP1925151A2 - Image pixel reset through dual conversion gain gate - Google Patents

Image pixel reset through dual conversion gain gate

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Publication number
EP1925151A2
EP1925151A2 EP06800856A EP06800856A EP1925151A2 EP 1925151 A2 EP1925151 A2 EP 1925151A2 EP 06800856 A EP06800856 A EP 06800856A EP 06800856 A EP06800856 A EP 06800856A EP 1925151 A2 EP1925151 A2 EP 1925151A2
Authority
EP
European Patent Office
Prior art keywords
diffusion region
photo
charge
generated charge
conversion gain
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
EP06800856A
Other languages
German (de)
English (en)
French (fr)
Inventor
Jeffrey A. Mckee
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Aptina Imaging Corp
Original Assignee
Micron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Publication of EP1925151A2 publication Critical patent/EP1925151A2/en
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/77—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/50—Control of the SSIS exposure
    • H04N25/57—Control of the dynamic range
    • H04N25/59—Control of the dynamic range by controlling the amount of charge storable in the pixel, e.g. modification of the charge conversion ratio of the floating node capacitance
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14643—Photodiode arrays; MOS imagers
    • H01L27/14654—Blooming suppression
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/77—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
    • H04N25/771—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising storage means other than floating diffusion
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors

Definitions

  • the invention relates generally to imaging devices and more particularly to increasing the fill factor and charge storage capacity of an imaging device and to resetting image pixels.
  • a digital imager array typically includes a focal plane array of pixel cells, each one of the cells including a photosensor, e.g. a photogate, photoconductor, or a photodiode.
  • a readout circuit is connected to each pixel cell, which typically includes a source follower output transistor.
  • the photosensor converts photons to electrons, which are typically transferred to a floating diffusion region connected to the gate of the source follower output transistor.
  • a charge transfer device e.g., transistor
  • imager pixel cells typically have a transistor for resetting the floating diffusion region to a predetermined charge level prior to charge transference.
  • the output of the source follower transistor is gated as a pixel output signal by a row select transistor.
  • CMOS imaging circuits processing steps thereof, and detailed descriptions of the functions of various CMOS elements of an imaging circuit are described, for example, in U.S. Patent No. 6,140,630, U.S. Patent No. 6,376,868, U.S. Patent No. 6,310,366, U.S. Patent No. 6,326,652, U.S. Patent No. 6,204,524, and U.S. Patent No. 6,333,205, each assigned to Micron Technology, Inc, which are hereby incorporated by reference in their entirety.
  • FIGS. 1 and 2 which respectively illustrate a top-down and a cross-sectional view of a conventional CMOS imager pixel cell 100
  • incident light 187 strikes the surface of a photodiode photosensor 120
  • electron/hole pairs are generated in the p-n junction of the photodiode (represented at the boundary of n- accumulation region 122 and p+ surface layer 123).
  • the generated electrons (photo-charges) are collected in the n-type accumulation region 122 of the photodiode 120.
  • the photo-charges move from the initial charge accumulation region 122 to a floating diffusion region 110 via a transfer transistor 106.
  • the charge at the floating diffusion region 110 is typically converted to a pixel output voltage by a source follower transistor 108 and subsequently output on a column output line 111 via a row select transistor 109.
  • CMOS imager designs such as that shown in FIG. 1 for pixel cell 100, provide approximately a fifty percent fill factor, meaning only half of the pixel 100 is utilized in converting light to charge carriers.
  • a small portion of the cell 100 comprises a photosensor (photodiode) 120.
  • the remainder of the pixel cell 100 includes isolation regions 102, shown as STI regions in a substrate 101, the floating diffusion region 110 coupled to a transfer gate 106' of the transfer transistor 106, and source/drain regions 115 for reset 107, source follower 108, and row select 109 transistors having respective gates 107', 108', 109'.
  • the invention provides an efficient pixel cell array architecture that has an improved fill factor and charge storage capacity.
  • each pixel has a dual conversion gain element coupled between two floating diffusion regions.
  • the dual conversion gain element switches in a storage element to increase the charge storage capacity of the pixel.
  • Pixel reset circuitry is coupled to the second floating diffusion region. In order to reset the first floating diffusion region and the storage element, the dual conversion gain element is activated during the reset operation.
  • the invention also provides shared pixel configurations where the dual conversion gain element, storage element and reset and readout components are shared by two or more pixels to increase pixel fill factor in addition to increasing pixel charge storage capacity.
  • FIG. 1 illustrates a conventional CMOS imager pixel cell
  • FIG. 2 is a cross-sectional view of the CMOS imager pixel cell illustrated in FIG. 1;
  • FIG.3 illustrates an exemplary CMOS imager pixel cell constructed in accordance with an embodiment of the invention
  • FIG. 4 is a timing diagram illustrating an exemplary operation of the pixel cell illustrated in FIG.3;
  • FIG. 5 illustrates an exemplary four-way shared CMOS imager pixel circuit constructed in accordance with an embodiment of the invention
  • FIG. 6 is a timing diagram illustrating an exemplary operation of the pixel circuit illustrated in FIG. 5;
  • FIG. 7 illustrates an exemplary two-way shared CMOS imager pixel circuit constructed in accordance with an embodiment of the invention
  • FIG. 8 shows an imager constructed in accordance with an embodiment of the invention.
  • FIG. 9 shows a processor system incorporating at least one imager constructed in accordance with an embodiment of the invention.
  • FIG. 3 illustrates an exemplary CMOS imager pixel cell 200 constructed in accordance with an embodiment of the invention.
  • the pixel cell 200 is similar to the conventional pixel cell 100 (FIG. 1) in that the cell 200 includes a photosensor 220 (illustrated as a photodiode), transfer transistor 206, reset transistor 207, source follower transistor 208, row select transistor 209 and a floating diffusion region FDj.
  • the illustrated cell 200 also includes a dual conversion gain (DCG) transistor 234, capacitor 236, second floating diffusion region FD2 and a high dynamic range (HDR) transistor 232.
  • DCG dual conversion gain
  • HDR high dynamic range
  • the pixel cell 200 is connected as follows.
  • the HDR transistor 232 (if included within the cell 200) is connected between the photosensor 220 and a pixel supply voltage Vaa-pix.
  • the gate terminal of the HDR transistor 232 is connected to receive a high dynamic range control signal HDR.
  • the HDR transistor 232 is activated, which allows excess charge to be drained away from the photosensor 220.
  • the HDR transistor 232 is an optional component that is not necessary to practice the invention (as described below). That is, in another embodiment of the pixel cell 200, the HDR transistor 232 is not included.
  • the transfer transistor 206 is connected between the photosensor 220 and the first floating diffusion region FD ⁇ and is controllable by a transfer gate control signal TX. When the transfer gate control signal TX is generated, the transfer transistor 206 is activated, which allows charge from the photosensor 220 to flow to the first floating diffusion region FDj.
  • the gate of the source follower transistor 208 is connected to the first floating diffusion region FDj.
  • a source/drain terminal of the source follower transistor 208 is connected to the array pixel supply voltage Vaa- pix.
  • the row select transistor 209 is connected between the source follower transistor 208 and a pixel array column line 211.
  • the reset transistor 207 is connected between the array pixel supply voltage Vaa-pix and the second floating diffusion region FD2.
  • the capacitor 236 is connected across the reset transistor 207.
  • the DCG transistor 234 is connected between the first floating diffusion region FD ⁇ and the second floating diffusion region FD2.
  • the gate terminal of the DCG transistor 234 is connected to a dual conversion gain control signal DCG.
  • the DCG transistor 234 When the dual conversion gain control signal DCG is generated, the DCG transistor 234 is activated, which connects the storage capacitance C of the capacitor 236, and the second floating diffusion region FD2, to the first floating diffusion region FDj .
  • This increases the storage capability of the pixel cell 200 beyond the capacity of the first floating diffusion region FD ⁇ , which is desirable and mitigates the leakage problems of the conventional pixel cell 100 (FIG. 1). That is, the pixel 200 contains a first conversion gain based solely on the storage capacity of the first floating diffusion region FDj, which is beneficial for low light conditions, and a second conversion gain based on the storage capacities of the first floating diffusion region FDj and the capacitor 236 (connected at the second floating diffusion region FD2), which is beneficial for bright light conditions.
  • FIG. 4 is a timing diagram illustrating an exemplary operation of the pixel cell 200 illustrated in FIG. 3.
  • the timing diagram illustrates three periods T a , T ⁇ , T c .
  • the row select signal ROW is applied to the gate of the row select transistor 209 (shown as being active low in FIG. 4).
  • FIG. 4 is an example timing diagram and that it is immaterial whether a signal is illustrated as being active low or high in FIG.4. All that is required to practice the invention is for the illustrated control signal to activate the component the signal is controlling.
  • the first floating diffusion region FDj of the pixel circuit 200 is reset by asserting the dual conversion gain control signal DCG (shown as being active low in FIG. 4) and the reset control signal RST (shown as being active low in FIG. 4) at the same time.
  • This causes the array pixel supply voltage Vaa-pix to be applied to the first floating diffusion region FDi (through the reset and DCG transistors 207, 234).
  • the array pixel supply voltage Vaa-pix is also applied to the second floating diffusion region FD2 and the capacitor 236.
  • the reset signal voltage Vrst associated with the reset first floating diffusion region FDx (as output by the source follower transistor 208 and activated row select transistor 209) is applied to column line 211 and is sampled and held by a sample and hold circuit 761 (FIG. 8) coupled to the column line 211 by the pulsing of a sample and hold reset signal SHR, which activates the sample and hold circuit.
  • the sample and hold circuit 761 is described in greater detail below with reference to FIG. 8.
  • charge accumulating in the photosensor 220 is transferred to the first floating diffusion region FDj when the transfer gate control signal TX is asserted (shown as being active low in FIG.4) and activates the transfer transistor 206.
  • the pixel signal voltage Vsigl associated with the pixel signal charge stored in the first floating diffusion region FD ⁇ (as output by the source follower transistor 208 and activated row select transistor 209) is applied to column line 211 and is sampled and held by a sample and hold circuit 761 (FIG. 8) coupled to the column line 211 by the pulsing of a sample and hold pixel signal SHS, which activates the sample and hold circuit.
  • the following operations are performed during the third time period T c .
  • the following third time period T c operations may be performed for every readout operation or only when needed to avoid the over capacity condition described above (i.e., when a controller or image processor (described below in more detail with respect to FIG. 8) determines that the amount of incident light will result in the first floating diffusion region FDj being saturated).
  • the dual conversion gain control signal DCG is applied (shown as being active low in FIG. 4). This causes the DCG transistor 234 to become active, which connects the first floating diffusion region FDj to the second floating diffusion region FD2. The charge within the first floating diffusion region FDi * s shared with the second floating diffusion region FD2 and is then stored in the capacitor 226.
  • the transfer gate control signal is applied (shown as being active low in FIG. 4) to activate the transfer transistor 206.
  • the new charged collected in the photosensor 220 is stored in the first floating diffusion region FDx and the second floating diffusion region FD2.
  • the new pixel signal voltage Vsig2 associated with the new pixel signal charge stored in the first floating diffusion region FDj and the second floating diffusion region FD2 (as output by the source follower transistor 208 and activated row select transistor 209) is applied to column line 211 and is sampled and held by a sample and hold circuit 761 (FIG. 8) coupled to the column line 211 by the pulsing of a third sample and hold signal (shown as SHD in FIG.4), which activates the sample and hold circuit.
  • the three sampled and held signals Vrst, Vsigl, Vsig2 may then undergo a correlated sampling operation to obtain the actual pixel signal level.
  • the high dynamic range control signal HDR would be applied throughout all three time periods T a , T ⁇ , T c to ensure that the HDR transistor 232 remains active during the readout operations. This prevents blooming and other phenomena from occurring during the readout process.
  • the pixel signal voltage Vsig associated with the remaining pixel signal charge stored in the first floating diffusion region FD ⁇ (as output by the source follower transistor 208 and activated row select transistor 209) is then sampled and held by the pixel signal sample and hold pixel signal SHS.
  • FIG. 5 illustrates an exemplary four-way shared CMOS imager pixel circuit 300 constructed in accordance with an embodiment of the invention.
  • the pixel circuit 300 shares reset and readout circuitry among four pixel cells 300 a , 300b, 3 OOo 300 ⁇ .
  • the four pixel cells 300 a , 300b, 300 c , 300 ⁇ share first and second floating diffusion regions FDj, FD2, a DCG transistor 334, reset transistor 307, storage capacitor 336, source follower transistor 308 and a row select transistor 309.
  • the first pixel cell 300 a includes a first photosensor 320 a (illustrated as a photodiode) and a first transfer transistor 306 a .
  • a first high dynamic range (HDR) transistor 332 a may also be part of the pixel cell 300 a if desired.
  • the first HDR transistor 332 a (if included) is connected between the first photosensor 320 a and the pixel supply voltage Vaa-pix.
  • the gate terminal of the first HDR transistor 332 a is connected to receive a first high dynamic range control signal HDR ⁇ 0>. In operation, when the first high dynamic range control signal HDR ⁇ 0> is generated, the HDR transistor 332 a is activated, which allows charge to be drained away from the photosensor 320 a .
  • the first transfer transistor 306 a is connected between the first photosensor 320 a and the shared first floating diffusion region FDj and is controllable by a first even column transfer gate control signal TX_EV ⁇ N ⁇ 0>.
  • TX_EVEN ⁇ 0> When the first even column transfer gate control signal TX_EVEN ⁇ 0> is generated, the first transfer transistor 306 a is activated, which allows charge from the first photosensor 320 a to flow to the first floating diffusion region FDj.
  • the second pixel cell 300 ⁇ includes a second photosensor 320 ⁇ (illustrated as a photodiode) and a second transfer transistor 306 ⁇ .
  • a second HDR transistor 332 ⁇ may also be part of the second pixel cell 30Oj-, if desired.
  • the second HDR transistor 332 ⁇ (if included) is connected between the second photosensor 320 ⁇ , and the pixel supply voltage Vaa- pix.
  • the gate terminal of the second HDR transistor 332 ⁇ is connected to receive a second high dynamic range control signal HDR ⁇ 1>. In operation, when the second high dynamic range control signal HDR ⁇ 1> is generated, the second HDR transistor 332 ⁇ is activated, which allows charge to be drained away from the second photosensor 32%.
  • the second transfer transistor 306 ⁇ is connected between the second photosensor 320t ⁇ and the shared first floating diffusion region FD ⁇ and is controllable by a second even column transfer gate control signal TX_EVEN ⁇ 1>.
  • TX_EVEN ⁇ 1> When the second even column transfer gate control signal TX_EVEN ⁇ 1> is generated, the second transfer transistor 306 ⁇ is activated, which allows charge from the second photosensor 320 ⁇ to flow to the first floating diffusion region FD ⁇ .
  • the third pixel cell 300 c includes a third photosensor 320 c (illustrated as a photodiode) and a third transfer transistor 306 c .
  • a third HDR transistor 332 C may also be part of the third pixel cell 300 c if desired.
  • the third HDR transistor 332 C (if included) is connected between the third photosensor 320 c and the pixel supply voltage Vaa-pix.
  • the gate terminal of the third HDR transistor 332 C is connected to receive the first high dynamic range control signal HDR ⁇ 0>. In operation, when the first high dynamic range control signal HDR ⁇ 0> is generated, the third HDR transistor 332 C is activated, which allows charge to be drained away from the third photosensor 320 c .
  • the third transfer transistor 306 c is connected between the third photosensor 320 c and the shared first floating diffusion region FDj and is controllable by a first odd column transfer gate control signal
  • TX_ODD ⁇ 0> When the first odd column transfer gate control signal TX_ODD ⁇ 0> is generated, the third transfer transistor 306 c is activated, which allows charge from the third photosensor 320 c to flow to the first floating diffusion region FD ⁇ .
  • the fourth pixel cell 300 ⁇ includes a fourth photosensor 320 ( j (illustrated as a photodiode) and a fourth transfer transistor 306 ⁇ .
  • a fourth HDR transistor 332 ( J may also be part of the fourth pixel cell 300 ( j if desired.
  • the fourth HDR transistor 332 ( J (if included) is connected between the fourth photosensor 320 ( j and the pixel supply voltage Vaa- pix.
  • the gate terminal of the fourth HDR transistor 332 ( j is connected to receive a second high dynamic range control signal HDR ⁇ 1>. In operation, when the second high dynamic range control signal HDR ⁇ 1> is generated, the fourth HDR transistor 332 ( j is activated, which allows charge to be drained away from the fourth photosensor 320 ( j.
  • the fourth transfer transistor 306 ( j is connected between the fourth photosensor 320 ( j and the shared first floating diffusion region FDj and is controllable by a second odd column transfer gate control signal TX_ODD ⁇ 1>.
  • TX_ODD ⁇ 1> When the second odd column transfer gate control signal TX_ODD ⁇ 1> is generated, the fourth transfer transistor 306 ( j is activated, which allows charge from the fourth photosensor 320 ( j to flow to the first floating diffusion region FDj.
  • the gate of the source follower transistor 308 is connected to the first floating diffusion region FD ⁇ .
  • a source/drain terminal of the source follower transistor 308 is connected to the array pixel supply voltage Vaa- pix.
  • the row select transistor 309 is connected between the source follower transistor 308 and a column line 311.
  • the reset transistor 307 is connected between the array pixel supply voltage Vaa-pix and the second floating diffusion region FD2.
  • the capacitor 336 is connected across the reset transistor 307.
  • the DCG transistor 334 is connected between the first floating diffusion region FDj and the second floating diffusion region FD2.
  • the gate terminal of the DCG transistor 334 is connected to a dual conversion gain control signal DCG.
  • the DCG transistor 334 When the dual conversion gain control signal DCG is generated, the DCG transistor 334 is activated, which connects the storage capacitance C of the capacitor 336, and the second floating diffusion region FD2, to the first floating diffusion region FDj. This increases the storage capability of the pixel circuit 300 beyond the capacity of the first floating diffusion region FDj, which is desirable and mitigates the leakage problems of the conventional pixel cell 100 (FIG. 1).
  • the pixel circuit 300 contains a first conversion gain based solely on the storage capacity of the first floating diffusion region FDj, which is beneficial for low light conditions, and a second conversion gain based on the storage capacities of the first floating diffusion region FDi an( ⁇ tne capacitor 336 (connected at the second floating diffusion region FD2), which is beneficial for bright light conditions.
  • FIG. 6 is a timing diagram illustrating an exemplary operation of a portion of the pixel circuit 300 illustrated in FIG. 5.
  • the timing diagram illustrates the operation of the first pixel cell 300 a .
  • the operation of the circuit 300 would repeat the following steps for the operation of the remaining pixels 30%, 300 c , 30O 0 J. Since the operation of the first row is essentially the same (with the below noted exceptions), a detailed description of the operation of the remaining pixels 300 ⁇ , 300 c , 300 ⁇ is not provided.
  • FIG. 6 illustrates the row select signal ROW as being toggled high and low at certain instances. It should be appreciated that the row select signal ROW could remain applied during all three time periods T a , T] 3 , T c if desired.
  • the timing diagram illustrates three periods T a , Tt ⁇ , T c .
  • the row select signal ROW is applied to the gate of the row select transistor 309 (shown as being active low in FIG. 6).
  • FIG. 6 is an example timing diagram and that it is immaterial whether a signal is illustrated as being active low or high in FIG. 6. All that is required to practice the invention is for the illustrated signal to activate the component the signal is controlling.
  • the first floating diffusion region FDj of the pixel circuit 300 is reset by asserting the dual conversion gain control signal DCG (shown as being active low in FIG. 6) and the reset control signal RST (shown as being active low in FIG. 6) at the same time. This causes the array pixel supply voltage Vaa-pix to be applied to the first floating diffusion region FDi (through the reset and DCG transistors 307, 334). The array pixel supply voltage Vaa-pix is also applied to the second floating diffusion region FD2.
  • the reset signal voltage Vrst associated with the reset first floating diffusion region FD ⁇ (as output by the source follower transistor 308 and activated row select transistor 309) is applied to the column line 311 and then sampled and held by the sample and hold circuit 761 (FIG. 8), for the first pixel cell 300 a , by the pulsing of a sample and hold reset signal SHR.
  • charge accumulating in the first photosensor 320 a is transferred to the first floating diffusion region FDj when the first even column transfer gate control signal TX_EVEN ⁇ 0> is asserted (shown as being active low in FIG. 6) and activates the first transfer transistor 306 a .
  • the pixel signal voltage Vsigl associated with the first pixel cell's 300 a pixel signal charge stored in the first floating diffusion region FDj (as output by the source follower transistor 308 and activated row select transistor 309) is then sampled and held by the sample and hold circuit 761 (FIG. 8) by the pulsing of a sample and hold pixel signal SHS.
  • the following operations are performed during the third time period T c .
  • the following third time period T c operations may be performed for every readout operation or only when needed to avoid the over capacity condition described above (i.e., when a controller or image processor (described below in more detail with respect to FIG. 8) determines that the amount of incident light will result in the first floating diffusion region FDj being saturated).
  • the dual conversion gain control signal DCG is applied (shown as being active low in FIG. 6). This causes the DCG transistor 334 to become active, which connects the first floating diffusion region FD ⁇ to the second floating diffusion region FD2.
  • the full charge within the first floating diffusion region FDj flows to the second floating diffusion region FD2 and is stored in the capacitor 326.
  • the first even column transfer gate control signal TX_EVEN ⁇ 0> is applied (shown as being active low in FIG. 6) to activate the first transfer transistor 306 a .
  • the remaining excess charge from the first photosensor 320 a is stored in the first floating diffusion region FD ⁇ .
  • the new pixel signal voltage Vsig2 associated with the excess pixel signal charge stored in the first floating diffusion region FDj (as output by the source follower transistor 308 and activated row select transistor 309) is applied to a column line 311 connected to a sample and hold circuitry 761 (FIG.
  • Vrst, Vsigl, Vsig2 may then undergo a correlated sampling operation to obtain the actual pixel signal level for each conversion gain (e.g., Vrst-Vsigl, Vrst-Vsig2).
  • HDR transistors 332 a , 332b, 332 C 332 d are used in the pixel circuit 300, then the high dynamic range control signals HDR ⁇ 0>, HDR ⁇ 1> would be applied throughout all three time periods T a , Tb, T c to ensure that the HDR transistors 332 a , 332b, 332 C , 332 ( j remain active during the readout operations. This prevents blooming and other phenomena from occurring during the readout process by draining some charge away from the photosensors 320 a/ 32O] 3 , 320 C/ 320(j.
  • the pixel signal voltage Vsig associated with the remaining pixel signal charge stored in the first floating diffusion region FDj (as output by the source follower transistor 308 and activated row select transistor 309) is then sampled and held by the pixel signal sample and hold pixel signal SHS.
  • FIG. 7 illustrates an exemplary two-way shared CMOS imager pixel circuit 400 constructed in accordance with an embodiment of the invention.
  • the pixel circuit 400 shares reset and readout circuitry between two pixel cells 400 a , 400 ⁇ .
  • the pixel cells 400 a , 40O] 0 share first and second floating diffusion regions FDj, FD2, a DCG transistor 434, reset transistor 407, storage capacitor 436, source follower transistor 408 and a row select transistor 409.
  • the first pixel cell 400 a includes a first photosensor 420 a (illustrated as a photodiode) and a first transfer transistor 406 a .
  • a first high dynamic range (HDR) transistor 432 a may also be part of the first pixel cell 400 a if desired.
  • the first HDR transistor 432 a (if included) is connected between the first photosensor 420 a and the pixel supply voltage Vaa-pix.
  • the gate terminal of the first HDR transistor 432 a is connected to receive a first high dynamic range control signal HDR ⁇ 0>. In operation, when the first high dynamic range control signal HDR ⁇ 0> is generated, the first HDR transistor 432 a is activated, which allows charge to be drained away from the first photosensor 420 a .
  • the first transfer transistor 406 a is connected between the first photosensor 420 a and the shared first floating diffusion region FDj and is controllable by a first transfer gate control signal TX ⁇ 0>.
  • the first transfer gate control signal TX ⁇ 0> is generated, the first transfer transistor 406 a is activated, which allows charge from the first photosensor 420 a to flow to the first floating diffusion region FD ⁇ .
  • the second pixel cell 400 ⁇ includes a second photosensor 420 ⁇ (illustrated as a photodiode) and a second transfer transistor 406 ⁇ .
  • a second HDR transistor 432 ⁇ may also be part of the second pixel cell 400t ⁇ if desired.
  • the second HDR transistor 432t ⁇ (if included) is connected between the second photosensor 420t ⁇ and the pixel supply voltage Vaa- pix.
  • the gate terminal of the second HDR transistor 432 ⁇ is connected to receive a second high dynamic range control signal HDR ⁇ 1>. In operation, when the second high dynamic range control signal HDR ⁇ 1> is generated, the second HDR transistor 432 ⁇ is activated, which allows charge to be drained away from the second photosensor 42%.
  • the second transfer transistor 406 ⁇ is connected between the second photosensor 32Oj 2 , and the shared first floating diffusion region FDj and is controllable by a second transfer gate control signal TX ⁇ 1>.
  • the second transfer gate control signal TX ⁇ 1> is generated, the second transfer transistor 406t ⁇ is activated, which allows charge from the second photosensor 42% to flow to the first floating diffusion region FDj.
  • the gate of the source follower transistor 408 is connected to the first floating diffusion region FDj.
  • a source/drain terminal of the source follower transistor 408 is connected to the array pixel supply voltage Vaa- pix.
  • the row select transistor 409 is connected between the source follower transistor 408 and a column line 411.
  • the reset transistor 407 is connected between the array pixel supply voltage Vaa-pix and the second floating diffusion region FD2.
  • the capacitor 436 is connected across the reset transistor 407 and the second floating diffusion region FD2.
  • the DCG transistor 434 is connected between the first floating diffusion region FD ⁇ and the second floating diffusion region FD2.
  • the gate terminal of the DCG transistor 434 is connected to a dual conversion gain control signal DCG ⁇ 0>.
  • the DCG transistor 434 When the dual conversion gain control signal DCGO is generated, the DCG transistor 434 is activated, which connects the storage capacitance C of the capacitor 436, and the second floating diffusion region FD2, to the first floating diffusion region FD ⁇ .
  • This increases the storage capability of the pixel circuit 400 beyond the capacity of the first floating diffusion region FDj, which is desirable and mitigates the leakage problems of the conventional pixel cell 100 (FIG. 1). That is, the pixel circuit 400 contains a first conversion gain based solely on the storage capacity of the first floating diffusion region FDj, which is beneficial for low light conditions, and a second conversion gain based on the storage capacities of the first floating diffusion region FDj and the capacitor 436, which is beneficial for bright light conditions.
  • FIG. 8 illustrates an exemplary imager 700 that may utilize any of the embodiments of the invention.
  • the Imager 700 has a pixel array 705 comprising pixels constructed and operated as described above with respect to FIGS. 3-7. Row lines are selectively activated by a row driver 710 in response to row address decoder 720. A column driver 760 and column address decoder 770 are also included in the imager 700.
  • the imager 700 is operated by the timing and control circuit 750, which controls the address decoders 720, 770.
  • the control circuit 750 also controls the row and column driver circuitry 710, 760 in accordance with an embodiment of the invention (e.g., FIGS. 4 and 6).
  • a sample and hold circuit 761 associated with the column driver 760 reads the pixel reset signal Vrst and the two pixel image signals Vsigl, Vsig2 for the selected pixel which may then undergo a correlated sampling operation to obtain the actual pixel signal level (e.g., Vrst- Vsigl, Vrst-Vsig2).
  • the correlated signals are amplified by amplifier 762 for each pixel and are digitized by analog-to-digital converter 775 (ADC).
  • ADC analog-to-digital converter 775 supplies the digitized pixel signals to an image processor 780 which forms a digital image.
  • FIG. 9 shows a system 1000, a typical processor system modified to include an imaging device 1008 (such as the imaging device 700 illustrated in FIG. 8) of the invention.
  • the processor system 1000 is exemplary of a system having digital circuits that could include image sensor devices. Without being limiting, such a system could include a computer system, camera system, scanner, machine vision, vehicle navigation, video phone, surveillance system, auto focus system, star tracker system, motion detection system, image stabilization system, and data compression system, and other systems employing an imager.
  • System 1000 for example a camera system, generally comprises a central processing unit (CPU) 1002, such as a microprocessor, that communicates with an input/output (I/O) device 1006 over a bus 1020.
  • Imaging device 1008 also communicates with the CPU 1002 over the bus 1020.
  • the processor-based system 1000 also includes random access memory (RAM)1004, and can include removable memory 1014, such as flash memory, which also communicate with the CPU 1002 over the bus 1020.
  • the imaging device 1008 may be combined with a processor, such as a CPU, digital signal processor, or microprocessor, with or without memory storage on a single integrated circuit or on a different chip than the processor.

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EP06800856A 2005-08-10 2006-08-08 Image pixel reset through dual conversion gain gate Ceased EP1925151A2 (en)

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US11/200,052 US20070035649A1 (en) 2005-08-10 2005-08-10 Image pixel reset through dual conversion gain gate
PCT/US2006/030668 WO2007021626A2 (en) 2005-08-10 2006-08-08 Image pixel reset through dual conversion gain gate

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JP (1) JP2009505498A (zh)
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CN (1) CN101273619B (zh)
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CN101273619A (zh) 2008-09-24
WO2007021626A3 (en) 2007-08-02
KR20080038398A (ko) 2008-05-06
KR100940708B1 (ko) 2010-02-08
JP2009505498A (ja) 2009-02-05
WO2007021626A2 (en) 2007-02-22
CN101273619B (zh) 2012-02-15
US20070035649A1 (en) 2007-02-15
TW200731788A (en) 2007-08-16

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