EP1655771B1 - Method for forming film, method for manufacturing semiconductor device, semiconductor device and substrate treatment system - Google Patents

Method for forming film, method for manufacturing semiconductor device, semiconductor device and substrate treatment system Download PDF

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Publication number
EP1655771B1
EP1655771B1 EP04747870A EP04747870A EP1655771B1 EP 1655771 B1 EP1655771 B1 EP 1655771B1 EP 04747870 A EP04747870 A EP 04747870A EP 04747870 A EP04747870 A EP 04747870A EP 1655771 B1 EP1655771 B1 EP 1655771B1
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Prior art keywords
film
doped carbon
carbon film
plasma
forming
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German (de)
English (en)
French (fr)
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EP1655771A4 (en
EP1655771A1 (en
Inventor
Kenichi 3600-332 Tsukure NISHIZAWA
Yasuhiro Terai
Akira 2214 703 Kawashiri ASANO
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Tokyo Electron Ltd
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Tokyo Electron Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02118—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer carbon based polymeric organic or inorganic material, e.g. polyimides, poly cyclobutene or PVC
    • H01L21/0212—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer carbon based polymeric organic or inorganic material, e.g. polyimides, poly cyclobutene or PVC the material being fluoro carbon compounds, e.g.(CFx) n, (CHxFy) n or polytetrafluoroethylene
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
    • C23C16/26—Deposition of carbon only
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/56—After-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02337—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour
    • H01L21/0234—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour treatment by exposure to a plasma
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76826—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by contacting the layer with gases, liquids or plasmas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76855—After-treatment introducing at least one additional element into the layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02115—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material being carbon, e.g. alpha-C, diamond or hydrogen doped carbon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]

Definitions

  • the present invention generally relates to method of forming insulation films and more particularly to a film forming method of a F (fluorine)-doped carbon film, fabrication method of a semiconductor device that uses such a film formation method of fluorine-doped carbon film, a semiconductor device formed with such a method, and a substrate processing system for fabricating such a semiconductor device.
  • a film forming method of a F (fluorine)-doped carbon film fabrication method of a semiconductor device that uses such a film formation method of fluorine-doped carbon film, a semiconductor device formed with such a method, and a substrate processing system for fabricating such a semiconductor device.
  • multilayer interconnection structure In recent miniaturized semiconductor devices, so-called multilayer interconnection structure is used for electrically interconnecting a vast number of semiconductor elements formed on a substrate.
  • a multilayer interconnection structure a large number of interlayer insulation films, each burying therein an interconnection pattern, are laminated, and an interconnection pattern of one layer is connected to an interconnection pattern of an adjacent layer or a diffusion region in the substrate via a contact hole formed in the interlayer insulation film.
  • a copper interconnection pattern is used as the interconnection layer constituting the multilayer interconnection structure, and a F-doped silicon oxide film (SiOF film) having a specific dielectric constant of 3- 3.5 is used for the interlayer insulation film in place of conventional silicon oxide film (SiO 2 film) having the specific dielectric constant of about 4.
  • SiOF film F-doped silicon oxide film having a specific dielectric constant of 3- 3.5
  • low dielectric (low-K) insulation film having a low specific dielectric constant.
  • an interlayer insulation film used for the multilayer interconnection structure is required not only to have a low specific dielectric constant but also high mechanical strength and high stability against thermal anneal processing.
  • a F-doped carbon (CF) film is a promising material for the low dielectric constant insulation film for use in ultra fast semiconductor devices of the next generation in view of its sufficient mechanical strength and its capability of achieving low specific dielectric constant of 2.5 or less.
  • a F-doped carbon film has a chemical formula represented by C n F m . It is reported that such an F-doped carbon film can be formed by a parallel-plate type plasma processing apparatus or an ECR type plasma processing apparatus.
  • Patent Reference 1 obtains a F-doped carbon film by using a fluorocarbon compound such as CF 4 , C 2 F 6 , C 3 F 8 , C 4 F 8 , or the like, in a parallel-plate type plasma processing apparatus as a source gas.
  • Patent Reference 2 obtains a F-doped carbon film by using a fluorinated gas such as CF 4 , C 2 F 6 , C 3 F 8 , C 4 F 8 , or the like, in an ECR-type plasma processing apparatus.
  • a film forming method is described, in which a first F-doped carbon film is formed using a C 5 F 8 /Ar/CO plasma, where CO gas functions as a scavenger gas for physically absorbing fluorine in the plasma. Consecutively, a second film is deposited with the same plasma components but with a smaller number of fluorine ions in the plasma. Thereafter, the second F-doped carbon film is exposed to an Ar plasma such as to densify the same.
  • an F-doped carbon film is used frequently in a multilayer interconnection structure as an interlayer insulation film in combination with copper interconnection patterns.
  • a multilayer interconnection structure that uses a copper interconnection pattern, it is essential to cover the sidewall surfaces of the interconnection grooves or via-holes, in which the interconnection patterns are formed, by a barrier metal film typically of Ta, or the like, in order to block the diffusion of Cu from the interconnection patterns.
  • a Ta barrier metal film is deposited on the surface of the F-doped carbon film, however, there occurs a reaction between F in the F-doped carbon film and Ta in the barrier metal film and there is formed a volatile compound of TaF. It should be noted that such formation of TaF occurs particularly on the sidewall surface of the via-holes where the F-doped carbon film is exposed, while formation of TaF causes degradation in the adherence and deteriorates the reliability or lifetime of the multilayer interconnection structure.
  • the F-doped carbon film constituting the interlayer insulation film 2 On the sidewall surface of the via-hole 2A, there is exposed the F-doped carbon film constituting the interlayer insulation film 2, wherein the foregoing sidewall surface is covered with a Ta film 4 deposited on the hard mask pattern 3 so as to cover the via-hole 2A.
  • a contact structure With such a contact structure, a large amount of hydrogen is contained in the film as explained before, and there is a concern that F constituting the film causes a reaction with the hydrogen to form HF of corrosive nature.
  • Also described herein is a method of fabricating a semiconductor device, comprising the steps of:
  • F atoms existing on the film surface are removed according to the present invention, and it becomes possible to suppress formation of volatile fluoride film at the interface, even in the case a barrier metal film, or the like, is formed on such a film surface. Thereby, it becomes possible to realize a reliable electric contact.
  • a plasma CVD process that uses a microwave and characterized by low electron temperature at the time of formation of the F-doped carbon film, and further by using a source gas having an F/C ratio, defined as a ratio of F to C in the molecule, larger than 1 but less than 2, it becomes possible to achieve deposition of the desired F-doped carbon film without adding a hydrogen gas.
  • the F-doped carbon film thus formed does not contain hydrogen substantially in the film, and there occurs no problem of causing corrosion in the interconnection layer or other insulation layer when used for a multilayer interconnection structure. Further, because the F-doped carbon film of the present invention is substantially free from hydrogen, the film does not undergo etching when the foregoing modification processing is conducted by using nitrogen radicals. Thereby, it becomes possible to conduct the desired modification processing stably and with good reproducibility.
  • FIGS 2A and 2B are diagrams showing the construction of a microwave plasma processing apparatus 100 used with the first embodiment of the present invention, wherein Figure 2A shows the microwave plasma processing apparatus in a cross-sectional view, while Figure 2B shows the construction of a radial line slot antenna.
  • the microwave plasma processing apparatus 100 includes a processing vessel 11 evacuated from plural evacuation ports 11D and a stage 13 is provided in the processing vessel 11 of holding a substrate 12 to be processed.
  • a ring-shaped space 11C around the stage 13.
  • the plural evacuation ports 11D are formed in communication with the space 11C with a uniform interval, and hence in axial symmetry to the substrate to be processed. Thereby, it becomes possible to evacuate the processing vessel 11 uniformly via the space 11C and the evacuation ports 11D.
  • a ceramic cover plate of low-loss dielectric in the location corresponding to the substrate 12 held on the stage 13 for processing, via a seal ring 16A as a part of the outer wall of the processing vessel 11, such that the ceramic cover plate 17 faces the substrate 12 to be processed.
  • the cover plate 17 is seated upon a ring-shaped member provided on the processing vessel via the foregoing seal ring 16A, while the ring-shaped member 14 is provided with a ring-shaped plasma gas passage 14B corresponding to the ring-shaped member 14 in communication with a plasma gas supply port 14A. Further, the ring-shaped member 14 is formed with plural plasma gas inlets 14C communicating with the plasma gas passage 14B in axial symmetry to the substrate 12 to be processed.
  • the plasma gas such as Ar, Kr, Xe, H 2 , and the like, supplied to the plasma gas supply port 14A, are supplied to the inlets 14C via the plasma gas passage 14B and is released from the inlets 14C to a space 11A right underneath the cover plate 17 inside the processing vessel 11.
  • a radial line slot antenna 30 having a radiation plane shown in Figure 2B with a separation of 4 - 5mm from the cover plate 17.
  • the radial line slot antenna 30 is seated upon the ring-shaped member 14 via a seal ring 16B and is connected to an external microwave source (not shown) via a coaxial waveguide 21. Thereby, the radial line slot antenna excites the plasma gas released to the space 11A by the microwave from the microwave source.
  • the radial line slot antenna 30 comprises a flat, disk-shaped antenna body 22 connected to an outer waveguide 21A of the coaxial waveguide 21 and a radiation plate 18 formed on an opening of the antenna body 22 and formed with a large number of slots 18a and slots 18b perpendicular thereto as showing in Figure 2B , wherein a phase retardation plate 19 of a dielectric plate of constant thickness is inserted between the antenna body 22 and the radiation plate 18. Further, a central conductor 21B of the coaxial waveguide 21 is connected to the radiation plate 18, and a cooling block 20 including a coolant passage 20A is provided on the antenna body 22.
  • the microwave fed from the coaxial waveguide 21 spreads as it is propagated in the radial direction between the disk-shaped antenna body 22 and the radiation plate 18 and thereby experiences wavelength compression as a result of the action of the phase retardation plate 19.
  • the slots 18a and 18b in a concentric manner in correspondence to the wavelength of the microwave propagating in the radial direction, it becomes possible to radiate a plane wave of circular polarization in a direction substantially perpendicular to the radiation plate 18.
  • a conductive structure 24 inside the processing vessel 11 between the cover plate 17 and the substrate 12 to be processed such that the conductive structure is formed with a large number of nozzles 24B that release a processing gas supplied from an external processing gas source (not shown) via the processing gas passages 23 and 24A formed in the processing vessel 11, where each of the nozzles 24B releases the processing gas thus supplied to a space 11B between the conductive structure 24 and the substrate 12 to be processed.
  • the conductive structure 24 functions as a processing gas supplying part.
  • the conductive structure 24 constituting the processing gas supplying part is formed with openings 24C between adjacent nozzles 24B and 24B as shown in Figure 3 with a size that allows efficient passage of the plasma formed in the space 11A to the space 11B by way of diffusion.
  • the nozzles 24B are formed at the side of the processing gas supplying part 24 facing the substrate 12, not in the side that faces the cover plate 17.
  • the processing gas released from the processing gas supplying part 24 to the space 11B in the plasma processing apparatus 100 of Figures 2A and 2B via the nozzles 24B is excited by the high density plasma formed in the space 11A, and a uniform plasma processing is conducted on the substrate 12 to be processed efficiently at high speed, without damaging the substrate and the device structure on the substrate, and without contaminating the substrate.
  • the microwave radiated from the radial line slot antenna 30 is blocked by the processing gas supplying part 24 of a conductive body and there occurs no damaging of the substrate 12 to be processed by the microwave thus emitted from the radial line slot antenna 30.
  • the spaces 11A and 11B constitutes the processing space, wherein, in the case the processing gas supplying part 24 of Figure 3 is provided, excitation of plasma occurs primarily in the space 11A and film formation by the processing gas takes place primarily in the space 11B.
  • Figure 4A shows the distribution of the electron temperature formed in the processing space of the plasma processing apparatus of Figures 2A and 2B that includes the space 11A and 11B, for the case the processing pressure in the processing vessel 11 is set to about 67Pa (0.5 Torr) by introducing an Ar gas from the plasma gas inlet 14C and by feeding a microwave of 2.45GHz or 8.3 GHz to the radial line slot antenna 30 with the power density of 1.27W/cm 2 .
  • the vertical axis represents the electron temperature while the horizontal axis represents the distance as measured from the bottom surface of the cover plate.
  • the electron temperature becomes maximum in the region immediately underneath the cover plate 17 and takes the value of about 2.0eV in the case the microwave frequency is 2.45GHz and the value of about 1.8eV in the case the microwave frequency is 8.3GHz, while, in the so-called diffusion plasma region separated from the cover plate 17 by 20mm or more, it can be seen that the electron temperature is generally constant and takes the value of 1.0 - 1.1eV.
  • microwave plasma processing apparatus 100 it is possible to form the plasma of extremely low electron temperature, and it becomes possible to conduct the process that requires low energy by using such plasma of low electron temperature.
  • Figure 4B shows the distribution of the plasma electron density caused in the processing vessel 11 in the plasma processing apparatus 100 of Figures 2A and 2B .
  • the illustrated example is the result for the case the processing pressure in the processing vessel 11 is set to about 67Pa (0.5 Torr) by introducing an Ar gas from the plasma gas inlet 14C and a microwave of 2.45GHz or 8.3GHz is fed to the radial line slot antenna 30 with the power density of 1.27W/cm 2 , wherein it can be seen that a very high plasma density of 1 ⁇ 10 2 cm -2 is realized up to the distance of 60 - 70mm from the bottom surface of the cover plate 17 in any of the case in which the frequency is 2.45GHz and the case in which the frequency is 8.3GHz.
  • a F-doped carbon film on the substrate 12 to be processed by setting the position of the processing gas inlet 24 at the distance within 60mm from the bottom surface of the cover plate 17 such that the foregoing plasma electron density of 1 ⁇ 10 12 cm -2 is realized and further by exciting the plasma in the processing vessel 11A by introducing the Ar gas from the plasma gas inlet 14C and by feeding the microwave of 1 - 10GHz from the antenna, and further by introducing a C 5 F 8 gas to the processing space 11B from the processing gas inlet 24 in this state.
  • Figures 5A - 5H are the diagrams showing the fabrication process of a semiconductor device according to a first embodiment of the present invention.
  • FIG. 5A there is formed a cap layer 43 of an SiN film or SiOC film on the Si substrate 41, on which an insulation film 42 of SiO 2 , SiOC, or other low-K dielectric film is formed, and a F-doped carbon film 44 is formed on the cap layer 43 in the plasma processing apparatus 100 explained with reference to Figures 2A and 2B by introducing a C 5 F 8 source gas to the processing space 11B from the processing gas supplying part 24.
  • Such deposition of the F-doped carbon film 44 can be conducted by setting the substrate temperature to 250°C and by supplying an Ar gas to the space 11A right underneath the cover plate 17 from the plasma gas supplying part 14C under the pressure of about 100Pa and further by supplying the microwave of the frequency of 2.45GHz from the radial line slot antenna 30 with the power density of 2.0W/cm 2 .
  • an interconnection pattern 42A of Cu, or the like, is embedded in the low-K insulation film 42.
  • the F-doped carbon film 44 formed in such a manner is a film substantially free from hydrogen.
  • the step of Figure 5B is conducted next, in which a hard mask film 45 of SiCN, SiN or SiO 2 is formed on the F-doped carbon film 44 by using the same plasma processing apparatus 100. Further, in the step of Figure 5C , a resist pattern 46 having an opening 46A is formed on the hard mask film 45 by an ordinary photolithographic process.
  • trimethyl silane is supplied from the processing gas supplying part 24 to the processing space 11B as a source gas, and plasma containing nitrogen radicals is excited by supplying an Ar gas and a nitrogen gas to the space 11A right underneath the cover plate 17 from the plasma gas supplying part 14C.
  • deposition of such an SiCN film 45 can be conducted by setting the substrate temperature to 350°C and supplying the microwave of the 2.54GHz frequency from the radial line slot antenna 30 under the pressure of about 200Pa with the power density of 1.0W/cm 2 .
  • Figure 5D is introduced again into the plasma processing apparatus 100 of Figures 2A and 2B in the step of Figure 5E , and nitrogen radicals N* are formed by introducing a mixed gas of Ar and nitrogen into the space 11A right underneath the cover plate 17 from the plasma gas inlet 14C.
  • the nitrogen radicals N* thus formed are used to process the substrate 41 in the processing space 11B, such that there is caused decoupling of the F atoms existing on the surface of the F-doped carbon film 44 exposed at the sidewall surface of the opening 44A. Further, as a result of such nitrogen radical processing, there is a possibility that a modified layer is formed on the exposed surface of the F-doped carbon film 44 by coupling of nitrogen.
  • a Ta film 47 is formed on the structure of Figure 5E in the step of Figure 5F with the present embodiment as a barrier metal film, such that the Ta film 47 covers the surface of the hard mask film 45 and the exposed sidewall surface of the F-doped carbon film 44 and the surface of the interconnection pattern exposed at the bottom of the opening 44A continuously.
  • the F-doped carbon film of the present invention is film substantially free from hydrogen, and no such a problem takes place.
  • a Cu layer 48 is formed on the structure of Figure 5D in the step of Figure 5G typically by a seed layer forming process conducted by a CVD process and an electrolytic plating process so as to film the opening 44A. Further, in the step of Figure 5H , a part of the Cu layer 48 including the barrier metal film 47 and the hardmask film 45 is removed, and a structure is obtained such that a Cu pattern 48A constituting a Cu interconnection pattern or plug is formed in the F-doped carbon film 44 via a Ta barrier metal film 47.
  • the cluster-type substrate processing apparatus 60 comprises a vacuum transfer chamber 61 coupled with a load-lock chamber 62 for loading in and out a substrate and provided with a transfer robot therein, a dry etching chamber 63 coupled to the vacuum transfer chamber 61, a modification processing chamber 64 coupled to the vacuum transfer chamber 61 and conducing modification processing of Figure 5E , a sputtering chamber 65 coupled to the vacuum transfer chamber 61 and conducting deposition of Ta film of Figure 5F , and a cleaning chamber 66 coupled to the vacuum transfer chamber 61 and conducting dry cleaning to the structure of Figure 5D , wherein each of the dry etching chamber 63 and the modification chamber 64 is provided with a plasma processing apparatus 100 of the construction identical to the one explained with reference to Figures 2A and 2B .
  • the substrate 41 is introduced, after removing the resist pattern 46 by an ashing process, or the like, from the load-lock chamber 62 to the dry etching chamber 63 via the vacuum transfer chamber 61, and the dry etching process of Figure 5D is conducted.
  • an Ar gas is introduced into the space 11A from the plasma gas inlet 14C and an etching gas such as N 2 +H 2 is introduced into the processing space 11B from the processing part 24 in the plasma processing apparatus 100 provided in the dry etching chamber 63, and the desired dry etching is conducted by introducing a microwave to the space 11A from the radial line slot antenna 30 via the microwave window 17 while applying a high frequency bias to the stage 13 from the high frequency source 13A.
  • an Ar gas and a nitrogen gas are introduced into the space 11A from the plasma gas inlet 14C with the plasma processing apparatus 100 provided in the modification chamber 64, and the modification processing of Figure 5E is conducted by introducing a microwave to the space 11A via the microwave window 17 from the radical line slot antenna 30.
  • the substrate 41 under processing is transferred to the dry cleaning chamber 66 via the vacuum transfer chamber 61, and a dry cleaning processing is conducted by using NF 3 , F 2 , CO 2 or a chlorofluorocarbon family gas.
  • the substrate 41 thus completed with the dry cleaning processing in the processing chamber 66 is further forwarded to the sputtering processing chamber 65 via the vacuum transfer chamber 61, and the Ta barrier metal film 47 is formed by the process of figure 5F .
  • the substrate 41 under processing is returned to the load-lock chamber 62 via the vacuum transfer chamber 61.
  • FIG 7 shows the construction of another cluster-type substrate processing system 80 that is used together with the substrate processing system 60 of Figure 6 for formation of the cap film 43, the F-doped carbon film 44 and the hard mask film 45.
  • the cluster-type substrate processing apparatus 80 comprises a vacuum transfer chamber 81 coupled with a load-lock chamber 82 for loading in and out a substrate and provided with a transfer robot therein, a deposition chamber 83 coupled to the vacuum transfer chamber 81 and used for the formation of the cap film 43, a deposition chamber 84 coupled to the vacuum transfer chamber 81 and used for the formation of the F-doped carbon film 44, and a deposition chamber 85 coupled to the vacuum transfer chamber 81 and used for formation of the hard mask film 45, wherein each of the deposition chambers 83, 84 and 85 is provided with the plasma processing apparatus 100 identical in construction with that explained with reference to Figures 2A and 2B .
  • the substrate 41 under processing is transported to the deposition chamber from the load-lock chamber 82 via the vacuum transfer chamber 81, the cap film 43 is formed on the insulation film 42 by supplying an Ar gas and a nitrogen to the space 11A right underneath the cover plate 17 from the plasma gas supplying part 14C and by supplying a Si-containing gas such as trimethyl silane or SiH4 to the processing space 11B from the processing gas supplying part 24 in the plasma processing apparatus 100 provided in the processing chamber 83, and further by exciting microwave plasma by feeding a microwave to the space 11A from the radial line slot antenna 30 via the cover plate 17.
  • a Si-containing gas such as trimethyl silane or SiH4
  • the substrate 41 under processing is transferred to the deposition chamber 84 from the deposition chamber 83 via the vacuum transfer chamber 81, and in the plasma processing apparatus 100 in the deposition chamber 84, an Ar gas and a nitrogen gas are supplied from the plasma gas supplying part 14C to the space 11A right underneath the cover plate 17, and the F-doped carbon film 44 is formed on the cap layer 43 by supplying a fluorocarbon source gas having the F/C ratio in the molecule larger than 1 but less than 2, such as C 5 F 8 , into the processing space 11B from the processing gas supplying part 24, and further by exciting microwave plasma in the space 11A by supplying a microwave in the space 11A from the radial line slot antenna 30 via the cover plate 17.
  • a fluorocarbon source gas having the F/C ratio in the molecule larger than 1 but less than 2, such as C 5 F 8
  • the substrate 41 under processing is transported to the deposition chamber 85 from the deposition chamber 84 via the vacuum transfer chamber 81, and the hard mask film 45 is formed on the F-doped carbon film in the plasma processing apparatus 100 in the deposition chamber 85 by supplying an Ar gas and a nitrogen gas to the space 11A right underneath the cover plate 17 from the plasma gas supplying part 14C and by supplying a Si-containing source gas such as trimethyl silane or SiH 4 to the processing space 11B from the processing gas supplying part 24, and further exciting microwave plasma in the space 11A by supplying a microwave to the space 11A from the radial line slot antenna via the cover plate 17.
  • a Si-containing source gas such as trimethyl silane or SiH 4
  • the substrate 41 thus formed with the hard mask film 45 is returned to the load-lock chamber via the vacuum transfer chamber 81 and is forwarded to the resist process and photolithographic process of Figure 5C .
  • Figure 8 is a diagram showing the construction of a semiconductor device 120, wherein those parts of Figure 8 explained previously are designated by the same reference numerals and the description thereof will be omitted.
  • the illustrate shows the state after the Ta barrier metal film 47 is formed but before the Cu layer 48 of Figure 5G is formed explained previously with reference to Figure 5F , wherein it should be noted that, with the present embodiment, an Al film 49 is deposited between the surface of the hard mask film 45 or the F-doped carbon film exposed at the opening 44A and the Ta barrier metal film 47.
  • the Ta barrier film 47 is separated from the F-doped carbon film 44 and the problem of formation of volatile TaF as a result of reaction of the barrier film 47 with F is avoided. Because Al forms stable AlF when reacted with F, it can be seen that there is formed an AlF layer in the construction of Figure 8 in the part of the Al film 49 that forms an interface contacting with the F-doped carbon film surface. Further, there is formed an Al-Cu alloy in the part of the Al film 49 that corresponds to the bottom of the opening 44A where contact to the Cu interconnection pattern 42A is to be made.
  • the Al film 49 is typically formed by a sputtering process, while it is also possible to form by an ALD process or CVD process.
  • any metal film that forms a stable compound when reacted with F can be used.
  • the F-doped carbon film 33 it is preferable to form the F-doped carbon film 33 by using the fluorocarbon source in which the F/C ratio is larger than 1 but smaller than 2 for avoiding the formation of corrosive HF and by using the microwave plasma processing apparatus 100 explained with reference to Figures 2A and 2B .
  • modification of the fluorine-doped carbon film of the present invention is not limited to nitrogen or Ar explained before, but it is also possible to conduct by using in the radicals containing any of Kr, C, B and Si.

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EP04747870A 2003-08-15 2004-07-23 Method for forming film, method for manufacturing semiconductor device, semiconductor device and substrate treatment system Expired - Lifetime EP1655771B1 (en)

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EP2284875A3 (en) 2011-08-31
EP2284875A2 (en) 2011-02-16
TWI373073B (enrdf_load_stackoverflow) 2012-09-21
US20100317188A1 (en) 2010-12-16
JP4413556B2 (ja) 2010-02-10
EP1655771A4 (en) 2008-02-27
EP1655771A1 (en) 2006-05-10
JP2005064302A (ja) 2005-03-10
KR100782673B1 (ko) 2007-12-07
WO2005017990A1 (ja) 2005-02-24
CN1836317A (zh) 2006-09-20
US7875549B2 (en) 2011-01-25
US20060223306A1 (en) 2006-10-05
TW200518221A (en) 2005-06-01
US8119518B2 (en) 2012-02-21
KR20060038469A (ko) 2006-05-03

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