JP5700513B2 - 半導体装置の製造方法および半導体装置 - Google Patents
半導体装置の製造方法および半導体装置 Download PDFInfo
- Publication number
- JP5700513B2 JP5700513B2 JP2010228406A JP2010228406A JP5700513B2 JP 5700513 B2 JP5700513 B2 JP 5700513B2 JP 2010228406 A JP2010228406 A JP 2010228406A JP 2010228406 A JP2010228406 A JP 2010228406A JP 5700513 B2 JP5700513 B2 JP 5700513B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- semiconductor device
- wiring layer
- layer
- manufacturing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000004065 semiconductor Substances 0.000 title claims description 74
- 238000004519 manufacturing process Methods 0.000 title claims description 29
- 239000010410 layer Substances 0.000 claims description 148
- 238000000034 method Methods 0.000 claims description 25
- 238000005121 nitriding Methods 0.000 claims description 22
- 238000005498 polishing Methods 0.000 claims description 22
- 230000004888 barrier function Effects 0.000 claims description 21
- 239000011229 interlayer Substances 0.000 claims description 21
- 239000000126 substance Substances 0.000 claims description 7
- 238000009792 diffusion process Methods 0.000 claims description 4
- 239000000463 material Substances 0.000 claims description 4
- 150000004767 nitrides Chemical class 0.000 description 33
- 230000000052 comparative effect Effects 0.000 description 21
- 239000000758 substrate Substances 0.000 description 20
- 239000010949 copper Substances 0.000 description 8
- 230000006866 deterioration Effects 0.000 description 8
- 230000015556 catabolic process Effects 0.000 description 7
- 238000006731 degradation reaction Methods 0.000 description 7
- 239000002002 slurry Substances 0.000 description 7
- 238000005530 etching Methods 0.000 description 6
- NBVXSUQYWXRMNV-UHFFFAOYSA-N fluoromethane Chemical compound FC NBVXSUQYWXRMNV-UHFFFAOYSA-N 0.000 description 6
- 238000002186 photoelectron spectrum Methods 0.000 description 6
- 230000008569 process Effects 0.000 description 6
- 229910052802 copper Inorganic materials 0.000 description 5
- 238000004833 X-ray photoelectron spectroscopy Methods 0.000 description 4
- 230000008859 change Effects 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 4
- 229910010271 silicon carbide Inorganic materials 0.000 description 4
- 230000008901 benefit Effects 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 239000012212 insulator Substances 0.000 description 3
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000003247 decreasing effect Effects 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 238000011156 evaluation Methods 0.000 description 2
- 230000007246 mechanism Effects 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- -1 silicon carbide nitride Chemical class 0.000 description 2
- YBMDPYAEZDJWNY-UHFFFAOYSA-N 1,2,3,3,4,4,5,5-octafluorocyclopentene Chemical compound FC1=C(F)C(F)(F)C(F)(F)C1(F)F YBMDPYAEZDJWNY-UHFFFAOYSA-N 0.000 description 1
- BKGFFXQUCIPKJK-UHFFFAOYSA-N 1-fluorocyclopropene Chemical compound FC1=CC1 BKGFFXQUCIPKJK-UHFFFAOYSA-N 0.000 description 1
- JOYRKODLDBILNP-UHFFFAOYSA-N Ethyl urethane Chemical compound CCOC(N)=O JOYRKODLDBILNP-UHFFFAOYSA-N 0.000 description 1
- KRHYYFGTRYWZRS-UHFFFAOYSA-M Fluoride anion Chemical compound [F-] KRHYYFGTRYWZRS-UHFFFAOYSA-M 0.000 description 1
- 235000012087 Psidium araca Nutrition 0.000 description 1
- 244000233562 Psidium araca Species 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 125000001931 aliphatic group Chemical group 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 238000000354 decomposition reaction Methods 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 239000012776 electronic material Substances 0.000 description 1
- 230000005284 excitation Effects 0.000 description 1
- SKRPCQXQBBHPKO-UHFFFAOYSA-N fluorocyclobutane Chemical class FC1CCC1 SKRPCQXQBBHPKO-UHFFFAOYSA-N 0.000 description 1
- IZZJFOLOOYFYFG-VKHMYHEASA-N fluorocyclopropane Chemical compound F[C@H]1[CH]C1 IZZJFOLOOYFYFG-VKHMYHEASA-N 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 229910052756 noble gas Inorganic materials 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 241000894007 species Species 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
- H01L21/76826—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by contacting the layer with gases, liquids or plasmas
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02118—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer carbon based polymeric organic or inorganic material, e.g. polyimides, poly cyclobutene or PVC
- H01L21/0212—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer carbon based polymeric organic or inorganic material, e.g. polyimides, poly cyclobutene or PVC the material being fluoro carbon compounds, e.g.(CFx) n, (CHxFy) n or polytetrafluoroethylene
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31058—After-treatment of organic layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/32115—Planarisation
- H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
- H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53257—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being a refractory metal
- H01L23/53266—Additional layers associated with refractory-metal layers, e.g. adhesion, barrier, cladding layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/5329—Insulating materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/5329—Insulating materials
- H01L23/53295—Stacked insulating layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Plasma & Fusion (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Inorganic Chemistry (AREA)
- General Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Mechanical Engineering (AREA)
- Metallurgy (AREA)
- Organic Chemistry (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Chemical Vapour Deposition (AREA)
- Formation Of Insulating Films (AREA)
Description
このような多層配線構造においてデバイスの動作の高速化を図るためには、配線間の寄生容量および配線抵抗による遅延抵抗を防ぐ必要がある。
そのため、誘電率の低い層間絶縁膜を設ける場合がある。
まず、第1の実施形態に係る半導体装置1の構造について、図1を参照して説明する。
層間絶縁膜はCFx膜5であり、その表面には窒化層9が形成されている。
なお、図1から明らかなように、半導体装置1は層間絶縁膜上にSiCN(炭化窒化シリコン)またはSiCあるいはSiNなどのキャップ膜は設けられていない。
具体的には、プラズマ処理装置102を用いてプラズマCVDによりCFx膜5を形成する。
まず、プラズマ処理装置102の構造の概略について説明する。
以上がS1の説明である。
まず、CMP装置201の構造の概略について説明する。
まず、キャリア47の下面に被研磨物49としてのS3で得られた試料を、配線層7がパッド43に対向するように保持させる。
以上がS5の詳細である。
このようにして、図1に示す半導体装置1が完成する。
そのため、CMP処理によるCFx膜5の劣化を防止することができる。
第2の実施形態は、第1の実施形態において、凹部11を形成した後にCFx膜5の表面を窒化するものである。
まず、第2の実施形態に係る半導体装置1aの構造について、図6を参照して説明する。
CFx膜5の表面には窒化層9が形成されている。
まず、基板3を用意する。
具体的には、プラズマ処理装置102を用いてプラズマCVDによりCFx膜5を形成する。
このようにして、図6に示す半導体装置1aが完成する。
従って、第1の実施形態と同様の効果を奏する。
第3の実施形態は、第1の実施形態において、配線層7を、主要配線層8aとバリア層8bの2層構造としたものである。
バリア層8bとしては例えばTiN等の金属窒化物が用いられる。
まず、基板3を用意する。
具体的には、プラズマ処理装置102を用いてプラズマCVDによりCFx膜5を形成する。CFx膜5の具体的な形成方法は第1の実施形態と同様であるため、説明を省略する。
このようにして、図9に示す半導体装置1bが完成する。
従って、第1の実施形態と同様の効果を奏する。
そのため、主要配線層8aを構成する材料がCFx膜5に拡散するのを防止できる。
第4の実施形態は、第3の実施形態において、半導体装置1cを、配線層と層間絶縁膜(CFx膜)を積層させた多層配線構造としたものである。
また、第2の配線層7bは、表面に第2の窒化層9bが設けられている。
なお、半導体装置1cの製造方法は半導体装置1bの製造方法と同様である。
従って、第3の実施形態と同様の効果を奏する。
以下の条件にて図9に示す半導体装置1bを図10および図11に示す手順で作製し、リーク電流、誘電率、およびCFx膜5の構造を評価した。具体的な手順は以下の通りである。
(実施例1)
まず、基板3としてシリコン基板を用意し、図4に示すプラズマ処理装置102にてCFx膜5を成膜した。この際の処理条件は以下の通りである。
処理室内圧力:28mTorr(3.73Pa)
ガス種(流量):Ar(70sccm)およびC5F8(200sccm)
マイクロ波出力:1450W
成膜時間:200秒
成膜温度:365℃
膜厚:150nm
処理室内圧力:100mtorr(13.3Pa)
ガス種(流量):N2(80sccm)およびAr(20sccm)
マイクロ波出力:2kW
バイアス電圧: 150V
処理温度:25℃
処理時間:30秒
窒化層厚さ:1〜2nm
パッド:Rohm and Haas Electronic Materials製 Politex(登録商標)
スラリ:日立化成製 HS−815−B1
研磨剤比率:スラリ/H2O2=19.6/0.04
研磨剤流量:300mL/min
研磨圧:1.5PSI(10340Pa)
回転数:パッド/ウェーハ=50rpm/50rpm
過研磨時間:15秒
以上の工程により、試料を作製した。
過研磨時間を20秒とした他は実施例1と同じ条件で試料を作製した。
過研磨時間を30秒とした他は実施例1と同じ条件で試料を作製した。
過研磨時間を0秒とした他は実施例1と同じ条件で試料を作製した。即ち、試料をスラリに浸漬するのみで、研磨を行わなかった。
窒化処理を行わなかった他は実施例1と同じ条件で試料を作製した。
窒化処理を行わず、過研磨時間を20秒とした他は実施例1と同じ条件で試料を作製した。
窒化処理を行わず、過研磨時間を30秒とした他は実施例1と同じ条件で試料を作製した。
窒化処理を行わず、研磨工程を行わなかった他は実施例1と同じ条件で試料を作製した。
窒化処理を行わず、研磨工程では、試料をスラリに浸漬するのみで、研磨時間を0秒とした他は実施例1と同じ条件で試料を作製した。
次に、試料のリーク電流を測定した。
具体的には、まず、各試料において、図13に示すように、パターン61aをアース67に接続して接地し、パターン61bを電源63に接続した。また、電源63とパターン61bの間にはリーク電流測定装置65を接続した。
図14から明らかなように、実施例1、3(窒化あり)は研磨をしなかったもの(比較例5)と同程度のリーク電流だったが、比較例4、5(窒化なし)は、過研磨時間が長くなるに従い、リーク電流が大きくなっていた。
次に、実施例1〜3および比較例1〜4の試料について、リーク電流劣化および誘電率劣化を測定した。
なお、リーク電流劣化および誘電率劣化は以下の式で定義した。
リーク電流劣化=I/Iini
ここで、
I: 過研磨後のリーク電流
Iini:過研磨時間0秒でのリーク電流
誘電率劣化=(k−kini)/kini
ここで、
k: 過研磨後の誘電率
kini:過研磨時間0秒での誘電率
結果を図15に示す。
次に、以下の手順により、各試料のCFx膜5を構成する原子・分子の結合状態を評価した。
まず、試料のC1s光電子スペクトルを取得した。
結果を図18に示す。
図18より、過研磨時間が長くなるにつれて、Fピークの強度が低下していた。
以上の評価により、CFx膜5を窒化することにより、研磨によるCFx膜5の結合状態の変化(組成の変化)を防止でき、リーク電流や誘電率の上昇を防ぐことができることが分かった。
1a……半導体装置
1b……半導体装置
1c……半導体装置
3………基板
4a……下段側回路層
4b……上段側回路層
5………CFx膜
5a……第1のCFx膜
5b……第2のCFx膜
7………配線層
7a……第1の配線層
7b……第2の配線層
8a……主要配線層
8b……バリア層
9………窒化層
9a……第1の窒化層
9b……第2の窒化層
10……外壁
11……凹部
12……アンテナ
13……ガス導入管
14……ウェーハ
21……ラジアルラインスロットアンテナ(RLSA)
22……下段シャワープレート
23……上段シャワープレート
24……処理室
25……RF電源
26……ガス導入管
31……ステージ
41……プレート
43……パッド
45……軸
47……キャリア
49……被研磨物
51……軸
53……供給管
55……スラリ
59……パターン
61a…パターン
61b…パターン
63……電源
65……リーク電流測定装置
67……アース
102…プラズマ処理装置
201…CMP装置
Claims (5)
- CFx膜を含み当該CFx膜上にキャップ膜を有さない層間絶縁膜を成膜する工程(a)と、
前記CFx膜に所定パターンの凹部を形成する工程(b)と、
前記凹部を埋めかつ前記CFx膜上にわたって配線層を設ける工程(c)と、
前記凹部内以外の前記CFx膜上の余剰の配線層をCMP(化学機械研磨)によって除去して前記CFx膜の表面を露出させる工程(d)と、
を有し、
前記工程(b)の前または後で、かつ前記工程(c)の前において、前記CFx膜の表面を窒化する工程(e)を備えたことを特徴とする半導体装置の製造方法。 - 前記工程(a)は、希ガスを用いて発生させたプラズマを用いてCVDにより前記CFx膜を形成する工程であることを特徴とする請求項1記載の半導体装置の製造方法。
- 前記配線層は、
主要配線層と、前記主要配線層の前記CFx膜への拡散を防止するために前記主要配線層の裏面に接して形成されたバリア層とを有し、
前記主要配線層は、前記バリア層よりも導電率の高い材料で構成されていることを特徴とする請求項1または2のいずれか一項に記載の半導体装置の製造方法。 - 前記工程(c)は、
前記CFx膜上に前記バリア層を形成し、前記バリア層上に前記主要配線層を形成する工程であることを特徴とする請求項1〜3のいずれか一項に記載の半導体装置の製造方法。 - 前記工程(e)は、前記CFx膜の表面を1〜5nm窒化する工程であることを特徴とする請求項1〜4のいずれか一項に記載の半導体装置の製造方法。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2010228406A JP5700513B2 (ja) | 2010-10-08 | 2010-10-08 | 半導体装置の製造方法および半導体装置 |
US13/877,540 US8889545B2 (en) | 2010-10-08 | 2011-10-03 | Method of manufacturing a semiconductor device |
PCT/JP2011/072731 WO2012046675A1 (ja) | 2010-10-08 | 2011-10-03 | 半導体装置の製造方法および半導体装置 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2010228406A JP5700513B2 (ja) | 2010-10-08 | 2010-10-08 | 半導体装置の製造方法および半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2012084638A JP2012084638A (ja) | 2012-04-26 |
JP5700513B2 true JP5700513B2 (ja) | 2015-04-15 |
Family
ID=45927671
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2010228406A Expired - Fee Related JP5700513B2 (ja) | 2010-10-08 | 2010-10-08 | 半導体装置の製造方法および半導体装置 |
Country Status (3)
Country | Link |
---|---|
US (1) | US8889545B2 (ja) |
JP (1) | JP5700513B2 (ja) |
WO (1) | WO2012046675A1 (ja) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI627192B (zh) * | 2015-03-13 | 2018-06-21 | 村田製作所股份有限公司 | Atomic layer deposition inhibiting material |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3530073B2 (ja) * | 1999-05-25 | 2004-05-24 | 株式会社東芝 | 半導体装置及びその製造方法 |
JP4413556B2 (ja) * | 2003-08-15 | 2010-02-10 | 東京エレクトロン株式会社 | 成膜方法、半導体装置の製造方法 |
JP4194521B2 (ja) * | 2004-04-07 | 2008-12-10 | 東京エレクトロン株式会社 | 半導体装置の製造方法 |
JP4555143B2 (ja) * | 2004-05-11 | 2010-09-29 | 東京エレクトロン株式会社 | 基板の処理方法 |
US8193642B2 (en) * | 2005-06-20 | 2012-06-05 | Tohoku University | Interlayer insulating film, interconnection structure, and methods of manufacturing the same |
JP5119606B2 (ja) * | 2006-03-31 | 2013-01-16 | 東京エレクトロン株式会社 | 半導体装置及び半導体装置の製造方法 |
JP5120913B2 (ja) * | 2006-08-28 | 2013-01-16 | 国立大学法人東北大学 | 半導体装置および多層配線基板 |
JP5261964B2 (ja) | 2007-04-10 | 2013-08-14 | 東京エレクトロン株式会社 | 半導体装置の製造方法 |
JP2009111251A (ja) * | 2007-10-31 | 2009-05-21 | Tohoku Univ | 半導体装置およびその製造方法 |
-
2010
- 2010-10-08 JP JP2010228406A patent/JP5700513B2/ja not_active Expired - Fee Related
-
2011
- 2011-10-03 US US13/877,540 patent/US8889545B2/en not_active Expired - Fee Related
- 2011-10-03 WO PCT/JP2011/072731 patent/WO2012046675A1/ja active Application Filing
Also Published As
Publication number | Publication date |
---|---|
US20130187283A1 (en) | 2013-07-25 |
WO2012046675A1 (ja) | 2012-04-12 |
JP2012084638A (ja) | 2012-04-26 |
US8889545B2 (en) | 2014-11-18 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP5482881B2 (ja) | 半導体装置、および半導体装置の製造方法 | |
US6350694B1 (en) | Reducing CMP scratch, dishing and erosion by post CMP etch back method for low-k materials | |
JP5671253B2 (ja) | 半導体装置の製造方法 | |
JP5093479B2 (ja) | 多孔質絶縁膜の形成方法 | |
JP5261964B2 (ja) | 半導体装置の製造方法 | |
KR20040068586A (ko) | 다마신 분야에서 유전체 재료를 증착하는 방법 | |
JP2008529296A (ja) | 半導体デバイスの製造方法 | |
KR20030014123A (ko) | 반도체 집적 회로 장치의 제조 방법 | |
JP2011205155A (ja) | 半導体デバイス障壁層 | |
JP5349789B2 (ja) | 多層配線の形成方法 | |
KR101334004B1 (ko) | 반도체 장치 및 다층 배선 기판 | |
JP4492949B2 (ja) | 電子デバイスの製造方法 | |
JP2011155077A (ja) | 半導体装置の製造方法 | |
US9941214B2 (en) | Semiconductor devices, methods of manufacture thereof, and inter-metal dielectric (IMD) structures | |
JP5700513B2 (ja) | 半導体装置の製造方法および半導体装置 | |
JP4854938B2 (ja) | 半導体装置およびその製造方法 | |
JP2005260060A (ja) | レジスト除去装置及びレジスト除去方法、並びにそれを用いて製造した半導体装置 | |
JP5679662B2 (ja) | 誘電体キャップ層 | |
WO2002054483A2 (en) | A dual damascene integration scheme using a bilayer interlevel dielectric | |
JP2006073612A (ja) | レジスト除去方法 | |
EP1282164A2 (en) | Method to improve the adhesion of dielectric layers to copper | |
US20190229063A1 (en) | Semiconductor structure with substantially straight contact profile | |
JP3781290B2 (ja) | 積層絶縁膜の加工方法及び配線構造の形成方法 | |
KR100476707B1 (ko) | 반도체 소자의 제조 방법 | |
JP5925898B2 (ja) | フルオロカーボン用の金属カーバイドバリア層を形成する方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20130906 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20140305 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20141112 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20141224 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20150121 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20150212 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 5700513 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
LAPS | Cancellation because of no payment of annual fees |