EP1606841A2 - Elektronisches bauteil mit halbleiterchip und kunststoffgehäuse und verfahren zur herstellung desselben - Google Patents
Elektronisches bauteil mit halbleiterchip und kunststoffgehäuse und verfahren zur herstellung desselbenInfo
- Publication number
- EP1606841A2 EP1606841A2 EP04718612A EP04718612A EP1606841A2 EP 1606841 A2 EP1606841 A2 EP 1606841A2 EP 04718612 A EP04718612 A EP 04718612A EP 04718612 A EP04718612 A EP 04718612A EP 1606841 A2 EP1606841 A2 EP 1606841A2
- Authority
- EP
- European Patent Office
- Prior art keywords
- semiconductor chip
- edge sides
- electronic component
- plastic
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 113
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 8
- 238000004873 anchoring Methods 0.000 claims abstract description 16
- 210000001787 dendrite Anatomy 0.000 claims description 12
- 238000000034 method Methods 0.000 claims description 7
- 238000000608 laser ablation Methods 0.000 claims description 4
- 239000000126 substance Substances 0.000 claims description 3
- 230000008021 deposition Effects 0.000 claims 1
- 239000000463 material Substances 0.000 abstract description 7
- 150000001875 compounds Chemical class 0.000 description 25
- 230000008901 benefit Effects 0.000 description 5
- 230000032798 delamination Effects 0.000 description 5
- 230000007480 spreading Effects 0.000 description 5
- 238000003892 spreading Methods 0.000 description 5
- 239000011224 oxide ceramic Substances 0.000 description 3
- 229910052574 oxide ceramic Inorganic materials 0.000 description 3
- 238000000926 separation method Methods 0.000 description 3
- 230000003247 decreasing effect Effects 0.000 description 2
- 230000007613 environmental effect Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000003801 milling Methods 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 230000007704 transition Effects 0.000 description 2
- 230000001154 acute effect Effects 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 230000008646 thermal stress Effects 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3142—Sealing arrangements between parts, e.g. adhesion promotors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/183—Connection portion, e.g. seal
- H01L2924/18301—Connection portion, e.g. seal being an anchoring portion, i.e. mechanical interlocking between the encapsulation resin and another package part
Definitions
- the invention relates to an electronic component which has a semiconductor chip with an upper side, with a rear side and with edge sides, and a plastic housing.
- the semiconductor chip is embedded in the plastic housing in such a way that the rear side and the edge sides of the semiconductor chip are surrounded by a plastic compound, while the upper side of the semiconductor chip remains free of plastic compound.
- the invention also relates to a method for producing the electronic component.
- the object of the invention is to provide a reliable electronic component which has a semiconductor chip which is completely surrounded on its rear side and on its edge sides by a plastic compound.
- an electronic component that has a semiconductor chip.
- This semiconductor chip in turn has an upper side, a rear side and edge sides.
- the semiconductor chip is installed in a plastic housing and is surrounded by a plastic compound on the back and the edges.
- the top of the semiconductor chip can then remain partially or completely free of plastic compound and form a flat surface with the top of the plastic housing.
- the edge sides and / or the rear side of the semiconductor chip have at least one anchoring area, via which the semiconductor chip interlocks with the surrounding plastic compound.
- micro-crack formation and spread of micro-cracks in the plastic mass is reduced, which increases reliability.
- shape of the anchoring area can prevent microcracks from spreading towards the surface of the plastic housing.
- the edge sides of the semiconductor chip have a profile which forms an obtuse angle to the top side of the semiconductor chip.
- the edge sides can have a step.
- this step can lie deep within the volume of the plastic housing or can be arranged on the top of the semiconductor chip.
- An arrangement of the step of the edge sides anchoring the semiconductor chip in the depth of the plastic compound has the advantage that microcracks occur due to thermal stress in the depth of the plastic housing and not in the vicinity of the top of the plastic housing.
- the step is arranged in the area of the upper side of the semiconductor chip, so that this step surrounds the semiconductor chip like a plate edge, this has the advantage that microcracks, which arise in the volume of the plastic mass at the bottom of the plate-shaped semiconductor chip, through the edge area of the semiconductor chip is characterized by the level, can not penetrate the top of the electronic component. Rather, the step-shaped edge of the semiconductor chip prevents them from developing microcracks on the upper side of the plastic housing.
- edge sides can be designed such that they have bulges with which they are interlocked with the plastic compound. Because of their rounding, these bulges are suitable for preventing any microcracks from occurring in the plastic material.
- the rounding closest to the surface can be designed such that the plastic mass gradually adapts to the level of the upper side of the semiconductor chip as the thickness decreases.
- a further possibility is to achieve an intensive anchoring between the semiconductor material and the plastic mass by applying dendrites to the upper sides of the semiconductor chip to be embedded. Dendrites not only prevent microcracks from spreading in the plastic compound, but also form an intensive interlocking between the semiconductor chip and the plastic compound.
- the dendrites can be different from the semiconductor chip
- the dendrites can be additionally attached to differently pre-profiled anchoring areas of a semiconductor chip.
- Another way of anchoring is to provide the back of the semiconductor chip with undercuts which form a positive connection between the plastic aces and the semiconductor chip material.
- undercuts can be made in the form of dovetail structures or other step-shaped notches by high-speed milling cutters on the back of the semiconductor chips or by appropriate laser ablation or by under-etching in an etching process.
- a method for producing a semiconductor chip with anchoring areas for a plastic compound surrounding the semiconductor chip has the following method steps.
- a semiconductor wafer which has integrated circuits arranged in rows and columns in a plurality of semiconductor chip positions. This semiconductor wafer is then separated in semiconductor chips by means of a profile saw and / or by means of laser ablation with profiling of the edge sides and / or the rear side of the semiconductor chip. After the semiconductor wafer has been separated into semiconductor chips with profiled edge sides and / or profiled rear sides, a semiconductor chip is embedded in a plastic compound while leaving the top side of the semiconductor chip free. The top of the semiconductor chip and the top of the plastic compound form a common flat surface.
- This method has the advantage that a plurality of semiconductor chips can be provided with anchoring regions simultaneously in a semiconductor chip separation process from a semiconductor wafer. Subsequently, it is possible to incorporate these profiled semiconductor chips into a plate-shaped plastic mass, so that a benefit arises which can now be processed further with firmly anchored semiconductor chips in the plastic plate.
- the above-mentioned step-shaped edge sides or an obtuse angle of the edge sides to the top can be worked out.
- Both profiled semiconductor chips and unprofiled semiconductor chips can be embedded in a plastic or chemical or galvanic compound before the semiconductor chip is embedded Bath are immersed, with dendrites made of oxide ceramics or metal being deposited on the edges and / or on the back of the semiconductor chip. These finely structured dendrites not only improve the form-fit, but also reduce the risk of microcracks in the area of the transition from the semiconductor chip to the plastic compound.
- delaminations and microcracks represent a lack of quality and, depending on the type and environmental conditions, can induce chip breaks and / or breaks in the bond connections and thus lead to the electrical failure of the semiconductor component.
- the roughness that occurs in the manufacturing process, both macroscopically and microscopically, is not sufficient to ensure secure anchoring of the semiconductor chip in the plastic compound for all loads. Due to the enlargement of the interface between the semiconductor chip and the plastic mass according to the invention, the risk of delamination and microcracks occurring and spreading between these two materials is reduced. The spreading along the otherwise rectilinear edge sides of the semiconductor chip is thus hindered and, according to the invention, changing the edge sides and the rear side of the semiconductor chip not only improves chemical interface adhesion, but also mechanical interlocking through undercuts.
- Cracks can thus be completely suppressed by the measures according to the invention, or cracks that occur can be forced to spread more slowly, or the cracks are prevented by a step or bevel from spreading up to the common upper side of the chip surface and plastic housing.
- FIG. 1 shows a cross section through a section of an electronic component of a first embodiment of the invention
- FIG. 2 shows a cross section through a section of an electronic component of a second embodiment of the invention
- FIG. 3 shows a cross section through a section of an electronic component of a third embodiment of the invention
- FIG. 4 shows a cross section through a section of an electronic component of a fourth embodiment of the invention
- FIG. 5 shows a cross section through a section in the edge region of the semiconductor chip of an electronic component of a fifth embodiment of the invention
- Figure 6 shows a cross section through a section in
- Edge side region of the semiconductor chip of an electronic component of a sixth embodiment of the invention is asymmetrical edge side region of the semiconductor chip of an electronic component of a sixth embodiment of the invention.
- FIG. 1 shows a cross section through a section of an electronic component of a first embodiment of the invention.
- the electronic component has a plastic housing 6 with a plastic compound 7, which completely surrounds a semiconductor chip 1 on its rear side 3 and on its edge sides 4 and 5.
- the top 2 of the semiconductor chip 1 is kept free from the plastic compound 7 and forms a common flat surface 9 with the top 8 of the plastic housing 6.
- On the common flat surface 9 can be thin-film structures, such as interconnects and ⁇ other wiring components applied to the contact surfaces, for example, not shown here, which are arranged on the upper side 2 of the semiconductor chip 1, with corresponding, not 'shown here, external contacts on the upper side of the plastic housing to connect.
- the edge sides 4 and 5 of this first embodiment of the invention have a step 11 in an anchoring area 10.
- This step 11 interrupts the smooth edge sides 4 and 5, so that microcracks which arise in the depth of the plastic compound 7 or which run from the component outer surfaces in the direction of the chip also extend through the plate edge-shaped edge sides 4 and 5 to the common area 9 are hindered.
- the thickness of the step 11 is significantly less than the total thickness of the semiconductor chip.
- the stage 11 has a thickness of approximately 20 to 300 ⁇ m, while the thickness of the entire semiconductor chip 1 is between 50 and 750 ⁇ m. Other absolute sizes can also be used if roughly the same proportions are observed.
- the ratio between the thickness of the step and the chip thickness can be approximately 0.1 to 0.3-0.4 or even up to approximately 0.8.
- Figure 2 shows a cross section through a section of an electronic component according to a second embodiment of the invention.
- Components with the same functions as in FIG. 1 are identified by the same reference symbols and are not discussed separately.
- the difference between the embodiment according to FIG. 2 differs from the embodiment according to FIG. 1 in that the step 11 on the edge sides 4 and 5 of the semiconductor chip is not arranged on the top side 2 of the semiconductor chip, but on the rear side 3.
- the arrangement ensures a secure " positive fit " and at the same time ensures that microcracks occur essentially in the area of the rear side 3, that is to say within the plastic mass 7 at the step located there, and spread horizontally and less towards the top side 8 of the plastic housing spread.
- FIG. 3 shows a cross section through a section of an electronic component according to a third embodiment of the invention.
- Components with the same functions as in the previous figures are identified by the same reference symbols and are not discussed separately.
- FIG. 3 shows an embodiment of the invention in which the edge sides 4 and 5 of the semiconductor chip 1 are oriented at an obtuse angle ⁇ to the top side 2 of the semiconductor chip 1.
- ⁇ obtuse angle
- Figure 4 shows a cross section through a section of an electronic component according to a fourth embodiment of the invention.
- the side edges 4 and 5 have been left smooth, but an anchoring area 10 is arranged on the rear side 3 of the semiconductor chip, which has undercuts 14. Microcracks, the anchoring region 10 arranged in this on the rear side 3 of the semiconductor chip 1 do not spread in the direction of the common surface 9.
- One of the- Like form-fitting anchoring 10 of a semiconductor chip 1 in a plastic mass 7 can be reinforced if the side edges 4 and 5 have microscopic structures in the form of dendrites or bulges, as shown in FIGS. 5 and 6.
- FIG. 5 shows a cross section through a section in the edge side region of the semiconductor chip 1 of a component of a fifth embodiment of the invention.
- Bulges 12 are arranged in the edge region. These bulges 12 are rounded off so that microcracks can slide on them.
- FIG. 6 shows a cross section of a detail in the edge side region of the semiconductor chip 1 of a component of a sixth embodiment of the invention. In this case it is
- Edge side 4 provided with dendrites 13, which were deposited on edge side 4, for example in a galvanic bath.
- dendrites 13 ensure an intensive positive fit between the semiconductor chip 1 and the plastic compound 7 and can also be seen on the rear side 3 of the
- Semiconductor chips 1 are applied. These dendrites are deposited in a galvanic bath on the edge side 4 and have oxide ceramics.
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
Description
Claims
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE10310842A DE10310842B4 (de) | 2003-03-11 | 2003-03-11 | Elektronisches Bauteil mit Halbleiterchip und Kunststoffgehäuse |
DE10310842 | 2003-03-11 | ||
PCT/DE2004/000461 WO2004082018A2 (de) | 2003-03-11 | 2004-03-09 | Elektronisches bauteil mit halbleiterchip und kunststoffgehäuse und verfahren zur herstellung desselben |
Publications (1)
Publication Number | Publication Date |
---|---|
EP1606841A2 true EP1606841A2 (de) | 2005-12-21 |
Family
ID=32920753
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP04718612A Withdrawn EP1606841A2 (de) | 2003-03-11 | 2004-03-09 | Elektronisches bauteil mit halbleiterchip und kunststoffgehäuse und verfahren zur herstellung desselben |
Country Status (4)
Country | Link |
---|---|
US (1) | US7508083B2 (de) |
EP (1) | EP1606841A2 (de) |
DE (1) | DE10310842B4 (de) |
WO (1) | WO2004082018A2 (de) |
Families Citing this family (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE102005023949B4 (de) | 2005-05-20 | 2019-07-18 | Infineon Technologies Ag | Verfahren zur Herstellung eines Nutzens aus einer Verbundplatte mit Halbleiterchips und einer Kunststoffgehäusemasse und ein Verfahren zur Herstellung von Halbleiterbauteilen mittels eines Nutzens |
US20070111399A1 (en) * | 2005-11-14 | 2007-05-17 | Goida Thomas M | Method of fabricating an exposed die package |
DE102006060629A1 (de) * | 2006-12-21 | 2008-06-26 | Robert Bosch Gmbh | Elektrisches Bauelement |
JP4525786B2 (ja) * | 2008-03-31 | 2010-08-18 | Tdk株式会社 | 電子部品及び電子部品モジュール |
JP2012199420A (ja) * | 2011-03-22 | 2012-10-18 | Fujitsu Ltd | 半導体装置 |
JP2014192347A (ja) * | 2013-03-27 | 2014-10-06 | Murata Mfg Co Ltd | 樹脂封止型電子機器およびそれを備えた電子装置 |
GB2514547A (en) | 2013-05-23 | 2014-12-03 | Melexis Technologies Nv | Packaging of semiconductor devices |
KR101933424B1 (ko) * | 2017-11-29 | 2018-12-28 | 삼성전기 주식회사 | 팬-아웃 반도체 패키지 |
JP7247124B2 (ja) * | 2020-01-07 | 2023-03-28 | 三菱電機株式会社 | 半導体モジュール |
JP2022043997A (ja) * | 2020-09-04 | 2022-03-16 | エスティーマイクロエレクトロニクス エス.アール.エル. | 信頼性を改善した電子装置の要素の製造方法、及び関連要素、電子装置、及び電子機器 |
US20230215833A1 (en) * | 2022-01-03 | 2023-07-06 | Wolfspeed, Inc. | Limiting Failures Caused by Dendrite Growth on Semiconductor Chips |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63143851A (ja) | 1986-12-08 | 1988-06-16 | Nec Corp | 半導体装置 |
JP2694871B2 (ja) | 1988-11-26 | 1997-12-24 | 三菱電機株式会社 | 半導体装置 |
JPH0563112A (ja) | 1991-09-03 | 1993-03-12 | Sony Corp | 半導体装置 |
DE4401588C2 (de) * | 1994-01-20 | 2003-02-20 | Gemplus Gmbh | Verfahren zum Verkappen eines Chipkarten-Moduls und Chipkarten-Modul |
DE19509262C2 (de) * | 1995-03-15 | 2001-11-29 | Siemens Ag | Halbleiterbauelement mit Kunststoffumhüllung und Verfahren zu dessen Herstellung |
DE19940564C2 (de) * | 1999-08-26 | 2002-03-21 | Infineon Technologies Ag | Chipkartenmodul und diesen umfassende Chipkarte, sowie Verfahren zur Herstellung des Chipkartenmoduls |
US6184064B1 (en) * | 2000-01-12 | 2001-02-06 | Micron Technology, Inc. | Semiconductor die back side surface and method of fabrication |
DE10206661A1 (de) * | 2001-02-20 | 2002-09-26 | Infineon Technologies Ag | Elektronisches Bauteil mit einem Halbleiterchip |
US6869894B2 (en) * | 2002-12-20 | 2005-03-22 | General Chemical Corporation | Spin-on adhesive for temporary wafer coating and mounting to support wafer thinning and backside processing |
-
2003
- 2003-03-11 DE DE10310842A patent/DE10310842B4/de not_active Expired - Fee Related
-
2004
- 2004-03-09 WO PCT/DE2004/000461 patent/WO2004082018A2/de active Application Filing
- 2004-03-09 US US10/548,854 patent/US7508083B2/en active Active
- 2004-03-09 EP EP04718612A patent/EP1606841A2/de not_active Withdrawn
Non-Patent Citations (1)
Title |
---|
See references of WO2004082018A2 * |
Also Published As
Publication number | Publication date |
---|---|
US20060255478A1 (en) | 2006-11-16 |
DE10310842B4 (de) | 2007-04-05 |
WO2004082018A2 (de) | 2004-09-23 |
DE10310842A1 (de) | 2004-09-30 |
US7508083B2 (en) | 2009-03-24 |
WO2004082018A3 (de) | 2004-11-11 |
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Owner name: INFINEON TECHNOLOGIES AG |
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