Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
  • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
  • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
  • H01L29/76—Unipolar devices, e.g. field effect transistors
  • H01L29/772—Field effect transistors
  • H01L29/78—Field effect transistors with field effect produced by an insulated gate
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
  • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
  • H01L29/66007—Multistep manufacturing processes
  • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
  • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
  • H01L29/66409—Unipolar field-effect transistors
  • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
  • H01L29/66833—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a charge trapping gate insulator, e.g. MNOS transistors
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
  • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
  • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
  • H01L29/76—Unipolar devices, e.g. field effect transistors
  • H01L29/772—Field effect transistors
  • H01L29/78—Field effect transistors with field effect produced by an insulated gate
  • H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
  • H01L29/7923—Programmable transistors with more than two possible different levels of programmation
• • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
  • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
  • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
  • Y10S438/00—Semiconductor device manufacturing: process
  • Y10S438/954—Making oxide-nitride-oxide device

Definitions

• the present invention relates to a production method for a multi-bit memory cell with self-aligned ONO areas.
• No. 5,768,192 describes a non-volatile memory in which electrons are trapped in a storage layer at the source or drain. These trapped electrons determine the threshold voltage of the transistor, which is designed as a SONOS transistor (Semiconductor Oxide Nitride Oxide Semiconductor). The presence of a charge at each source or drain can be interpreted as a stored bit, so that two bits can be stored in such a cell. Hot charge carriers are generated in the channel for programming; these electrons are injected from the semiconductor material into the storage layer near the drain region. For this purpose, a potential difference of typically 5 V is applied to a word line running across the gate in the direction from source to drain. The source area itself is set to 0 V, the drain area to 5 V as a bit line.
• a potential difference of typically 1.2 V between source and drain and a gate voltage between the threshold voltage in the unprogrammed state and the threshold voltage in the programmed state enable the bit stored on the source side to be read.
• a clearly negative potential at the gate and z. B. 5 V on drain (word line almost de-energized) enables the extinguishing by pushing the captured charge carriers back into the source or drain region which is positive towards ground (GIDL, gate-induced drain leakage).
• GIDL gate-induced drain leakage
• US Pat. No. 5,877,523 describes a multi-level split-gate flash memory cell in which an oxide layer and a polysilicon layer provided as a storage layer are applied and structured in two portions to form floating gate electrodes. The remaining portions are covered with a dielectric layer. A conductive layer is applied thereon, which is structured to form a gate electrode. Implants of dopant to form the source and drain follow.
• US Pat. No. 5,969,383 describes a split-gate memory component in which a layer sequence of silicon dioxide, silicon nitride and silicon dioxide is present over a portion of the channel area and over a portion of the drain area, of which the one above the channel with a control Gate electrode is provided. At this point, the memory cell is programmed by trapping charge carriers in the silicon nitride layer. A selection gate electrode is arranged over a remaining portion of the channel region.
• US Pat. No. 5,796,140 describes a method for producing a memory cell, in which the source and drain are formed as doped regions separated from one another by a channel region, over these regions one for the storage a storage electrode provided near charge carriers is arranged between boundary layers and embedded therein, a gate electrode is applied separately from the semiconductor material by means of a dielectric layer, the storage layer with the exception of regions which are located at the boundaries between the channel region and the source or Located in the drain area.
• JP 2000-58680 specifies a semiconductor memory component in which an oxide-nitride-oxide layer is also applied to the flanks of the gate electrode.
• the object of the present invention is to provide a method for producing a multi-bit memory cell which ensures a larger number of charge and discharge cycles even under unfavorable conditions.
• the memory layer provided for trapping charge carriers at the source and drain is limited to the edge region of the source region or drain region adjacent to the channel region.
• the storage layer is arranged between boundary layers and embedded in material of a higher energy band gap in such a way that the charge carriers which are trapped in the storage layer above the source region and above the drain region remain localized there.
• a nitride is preferably used as the material for the storage layer; an oxide is primarily suitable as the surrounding material.
• the memory cell in this example is silicon nitride with an energy band gap of approximately 5 eV, the surrounding boundary layers silicon oxide with an energy band gap of about 9 eV.
• the storage layer can be a different material with a smaller energy band gap than that of the boundary layers, with the difference of the energy band gaps being as large as possible for good electrical confinement of the charge carriers (confinement).
• z. B. tantalum oxide, hafnium silicate or intrinsically conductive (undoped) silicon can be used as the material of the storage layer.
• Silicon nitride has a relative dielectric constant of approximately 7.9. The use of an alternative material with a higher one
• Dielectric constant (e.g. «15 ... 18) allows a reduction in the total thickness of the layer stack intended for storage and is therefore an advantage.
• the storage layer provided for trapping the charge carriers is completely removed outside a region above that boundary of the source region and the drain region which faces the channel region in each case.
• the gate oxide and the gate electrode or a conductor track provided as a word line are then produced and structured, and free edges of the storage layer are still embedded in the material of the boundary layers, preferably an oxide. Because the memory layer above the channel region is removed, the SONOS transistor cell thus produced has memory regions separated from one another via source and drain.
• the gate oxide is not only produced on the semiconductor material of the channel region in the substrate, but also in a vertical direction
• Electrons are accelerated more towards the storage layer and are captured there.
• the operating characteristics (Performance) of the memory cell, especially when programming, are significantly improved.
• FIGS. 1 to 6 A first example of a manufacturing method according to the invention is shown in FIGS. 1 to 6.
• 1 shows a cross section of a semiconductor body 1 or a layer or layer structure made of semiconductor material grown on a substrate. If the semiconductor material does not have the desired basic doping, so-called troughs (eg p-troughs) of predetermined conductivity are produced in a known manner by implanting dopant in the required concentration.
• troughs eg p-troughs
• FIG. 1 shows a lower oxide layer 2 (bottom oxide) applied thereon as the lower boundary layer, thereon the storage layer 3 intended for trapping charge carriers (here silicon nitride in this example), thereon another oxide layer 4 (top oxide) as the upper boundary layer and at the top an auxiliary layer 5, which is considerably thicker than the previous layers and preferably also a nitride.
• the storage layer 3, the upper oxide layer 4 and the auxiliary layer 5 structured in the manner shown in Figure 1, so that they are laterally limited to an area provided for the memory cell. In the illustration in FIG. 1, the mask has already been removed.
• the auxiliary layer 5 is then used as a mask in order to produce the regions of the source 6a and drain 6b by means of an implantation of dopant into the semiconductor material.
• the dielectric layer 10 shown in FIG. 5 is produced on the semiconductor material of the substrate and on the lateral inner flanks formed by the spacer elements. The easiest way to do this is by surface oxidation of the semiconductor material, especially when using silicon.
• the gate electrode 11 is then produced or completed by the material provided for this being deposited in the recess between the spacer elements. Polysilicon doped in situ is also preferably used for this.
• Another CMP step serves to planarize the surface as shown in FIG. 5.
• the cross section of the memory cell is shown for the state after the deposition of a conductor track as a connection lead 12 for the gate electrode, the z. B. is provided as a word line for a memory cell arrangement.
• This conductor track is preferably also doped polysilicon.
• the structuring of the cell is then completed by limiting the structure shown in FIG. 6 in the directions perpendicular to the plane of the drawing. This is done by means of a further photo technique with which the material is etched down to the side of the gate electrode down to the upper oxide layer 4.
• the storage layer 3 is then preferably etched away by wet chemistry. A new oxidation serves to embed the now exposed edges of the storage layer 3 in oxide.
• the storage layer 3 is therefore also limited in the two directions perpendicular to the plane of the drawing in FIG. 6 by oxide layers. All edges of the storage layer are therefore embedded in oxide, so that a confluence of the charge carriers trapped in the two portions of the storage layer is permanently prevented. With this method, small multi-bit memory cells can therefore be produced which have a considerably longer service life than previous memory cells of this type.
• FIGS. 7 to 10 An alternative method that provides a memory cell according to the invention with a slightly modified structure is shown in FIGS. 7 to 10. This method is also based on a semiconductor body 1 (FIG. 7) or a layer or layer structure of semiconductor material grown on a substrate.
• a p-well or an n-well may be produced by implanting dopant in the required concentration.
• a lower oxide layer 2 (bottom oxide) as the lower boundary layer, the storage layer 3 intended for trapping charge carriers and a further oxide layer 4 (top oxide) as the upper boundary layer are applied over the entire surface.
• An auxiliary layer 80 the z. B. can be polysilicon, is structured according to the contours drawn to a remaining portion over the channel region 6 to be produced. Using this auxiliary layer 80, an implantation of dopant is preferably carried out first in order to
• An oxide layer 13 is produced, which is formed at least over the channel region and over the storage layer 3, so that the storage layer is completely surrounded by oxide.
• This oxide layer 13 can partly by reoxidation of the nitride (especially when using silicon as semiconductor material: 2 Si 3 N 4 + 12 H 2 0 yields 6 Si0 2 ), partly by depositing oxide (CVD oxide, chemical vapor deposition) , especially when using silicon as a semiconductor material: thermal oxidation from TEOS, tetraethyl orthosilicate, Si (OC 2 H 5 ) 4 + 120 2 provides Si0).
• a thermal oxidation of silicon has the additional advantage that the silicon can be oxidized to thicker oxide layers 70 via the portions of the source and drain regions facing away from the channel region.
• FIG. 10 The structure shown in FIG. 10 is completed by applying a conductor track 12 provided as a word line and a respective gate electrode.
• This conductor path is structured in a strip shape from the source running through the channel region to the drain, so that the conductor path is laterally delimited by edge surfaces to be thought of in front of and behind the drawing plane.
• the portion of the storage layer which is thereby exposed is removed.
• the edges of the storage layer exposed in this way are preferably embedded in oxide, which expediently takes place by reoxidation.

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• 2000
  • 2000-07-28 DE DE10036911A patent/DE10036911C2/de not_active Expired - Fee Related
• 2001
  • 2001-07-25 JP JP2002516782A patent/JP4116428B2/ja not_active Expired - Fee Related
  • 2001-07-25 CN CNB018134459A patent/CN100352021C/zh not_active Expired - Fee Related
  • 2001-07-25 EP EP01964854A patent/EP1305825A2/de not_active Withdrawn
  • 2001-07-25 WO PCT/DE2001/002811 patent/WO2002011145A2/de active IP Right Grant
  • 2001-07-25 KR KR10-2003-7000706A patent/KR100474176B1/ko not_active IP Right Cessation
  • 2001-07-27 TW TW090118284A patent/TW499738B/zh not_active IP Right Cessation
• 2003
  • 2003-01-28 US US10/352,826 patent/US6673677B2/en not_active Expired - Lifetime
  • 2003-11-12 US US10/706,841 patent/US6960505B2/en not_active Expired - Fee Related

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