EP1264335A1 - Procede de formation de jonctions de tres faible profondeur par recuit laser et recuit thermique rapide - Google Patents

Procede de formation de jonctions de tres faible profondeur par recuit laser et recuit thermique rapide

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Publication number
EP1264335A1
EP1264335A1 EP01916675A EP01916675A EP1264335A1 EP 1264335 A1 EP1264335 A1 EP 1264335A1 EP 01916675 A EP01916675 A EP 01916675A EP 01916675 A EP01916675 A EP 01916675A EP 1264335 A1 EP1264335 A1 EP 1264335A1
Authority
EP
European Patent Office
Prior art keywords
wafer
laser
laser energy
range
irradiated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP01916675A
Other languages
German (de)
English (en)
Inventor
Susan B. Felch
Somit Talwar
Daniel F. Downey
Carol M. Gelatos
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ultratech Inc
Varian Semiconductor Equipment Associates Inc
Original Assignee
Ultratech Inc
Varian Semiconductor Equipment Associates Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ultratech Inc, Varian Semiconductor Equipment Associates Inc filed Critical Ultratech Inc
Publication of EP1264335A1 publication Critical patent/EP1264335A1/fr
Withdrawn legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/268—Bombardment with radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering

Definitions

  • This invention relates to methods for thermal processing of semiconductor wafers that contain a dopant material and, more particularly, to methods for achieving ultrashallow junctions in semiconductors wafers by the use of sub-melt laser annealing and low temperature rapid thermal annealing.
  • Ion implantation is a standard technique for introducing conductivity-altering dopant materials into semiconductor wafers.
  • a desired dopant material is ionized in an ion source, the ions are accelerated to form an ion beam of prescribed energy, and the ion beam is directed at the surface of the wafer.
  • the energetic ions in the ion beam penetrate into the bulk of the semiconductor material and are embedded into the crystalline lattice of the semiconductor material.
  • the semiconductor wafer is annealed to activate the dopant material and to repair crystalline damage caused by the ion implantation. Annealing involves thermal processing of the semiconductor wafer according to a prescribed time and temperature protocol.
  • junction depths less than 1,000 angstroms and may eventually require junction depths on the order of 200 angstroms or less.
  • the implanted depth of the dopant material is determined by the energy of the ions implanted into the semiconductor wafer. Shallow junctions are obtained with low implant energies.
  • the annealing process that is used for activation of the implanted dopant material causes the dopant material to diffuse from the implanted region of the semiconductor wafer. As a result of such diffusion, junction depths are increased by annealing.
  • the implant energy may be decreased, so that a desired junction depth is obtained after annealing.
  • This approach provides satisfactory results, except in the case of ultrashallow junctions.
  • a limit is reached as to the junction depth that can be obtained by decreasing implant energy, due to the diffusion of the dopant material that occurs during annealing.
  • Rapid thermal annealing or spike annealing is typically utilized when minimal thermal diffusion is desired. Rapid thermal annealing typically involves heating the wafer to a temperature of 950°C to 1100°C for a time of 1 to 30 seconds, whereas spike annealing may involve annealing times less than 0.1 second. Controlled, low concentrations of oxygen may be added to a nitrogen ambient to minimize thermal diffusion, as described in PCT Publication No. WO 99/39381.
  • annealing parameters Notwithstanding careful selection of annealing parameters, rapid thermal anneals and spike anneals cause the dopant material to diffuse by thermal diffusion, transient enhanced diffusion, oxidation enhanced diffusion and dopant enhanced diffusion (i.e., boron enhanced diffusion or phosphorous enhanced diffusion). Even when low concentrations of oxygen are added to a nitrogen ambient and ultralow energy implants are performed, thermal diffusion still occurs.
  • Another known annealing technique is laser annealing, as described for example in
  • a surface layer of the wafer is amorphized, and a dopant material is implanted into the amorphized surface layer.
  • the amorphized surface layer is then irradiated with laser energy sufficient to melt the amorphized surface layer, causing the dopant material to be distributed throughout the region of melted silicon.
  • the integration of the laser annealing process with conventional device processes is relatively complicated. Silicon or germanium preamorphization implants are needed to avoid melting of the polysilicon gates, and deposition of an antireflective metal film is also necessary.
  • U.S. Patent No. 4,151,008 issued April 24, 1979 to Kirkpatrick discloses thermal processing of selected regions of a semiconductor device with a short duration pulse of light from a pulsed laser or a flash lamp. The disclosed process produces high sheet resistance if light energy density is too low to cause melting.
  • a method for thermal processing of a semiconductor wafer that contains a dopant material.
  • the dopant material may be implanted or deposited in the wafer by ion implantation, plasma doping or any other suitable deposition technique.
  • the method comprises the steps of irradiating the wafer with laser energy sufficient to activate the dopant material without melting the wafer and rapid thermal annealing of the wafer at relatively low temperature to repair crystalline damage.
  • the step of irradiating the wafer with laser energy is sufficient to heat the wafer to a temperature in a range of about 1100°C to 1410°C, and the step of rapid thermal annealing of the wafer is sufficient to heat the wafer to a temperature in a range of about 650°C to 850°C for a time in a range of less than 1 second to 60 seconds.
  • the implanted wafer is preferably irradiated with laser energy having a wavelength in a range of about 190 to 1500 nanometers.
  • the implanted wafer is irradiated with laser energy having a wavelength of 308 nanometers.
  • Other suitable laser wavelengths include 532 nanometers and 1064 nanometers.
  • the laser energy used to irradiate the wafer may comprise one or more laser pulses.
  • the wafer may be irradiated with laser energy comprising 100 to 1,000 laser pulses, and the pulse width of the laser pulses may be in a range of 10 to 100 nanoseconds.
  • the product of the number of laser pulses times the pulse width of the laser pulses may be in a range of 1 to 1,000 microseconds. In one embodiment, multiple laser pulses, each having a pulse width of about 20 nanoseconds, are used.
  • the laser anneal step may be performed in an ambient comprising oxygen in nitrogen, wherein oxygen concentration is controlled in a range of less than 1 to 1,000 parts per million during laser irradiation of the wafer.
  • the rapid thermal annealing step may be performed in an ambient comprising oxygen in nitrogen, wherein oxygen concentration is controlled in a range of less than 1 to 1,000 parts per million during rapid thermal annealing of the wafer.
  • a method for forming a doped region in a semiconductor wafer.
  • the method comprises the steps of implanting a dopant material into the semiconductor wafer, irradiating the implanted wafer with laser energy sufficient to activate the dopant material without melting the wafer, and rapid thermal annealing of the implanted wafer at relatively low temperature to repair crystalline damage.
  • the method of the invention achieves dopant activation with no measurable diffusion.
  • the rapid thermal anneal repairs crystalline damage from the implant of the dopant material, so that devices have good mobilities and low leakage currents.
  • Fig. 1 is a simplified, partial cross-sectional view of a semiconductor wafer
  • Fig. 2 is a flow chart that illustrates an embodiment of the process of the present invention
  • Fig. 3 is a graph of boron concentration in atoms per cubic centimeter as a function of depth in angstroms for different processes, including an embodiment of the process of the present invention.
  • FIG. 1 A highly simplified, partial cross-sectional view of a semiconductor wafer 10 is shown in Fig. 1. Junctions and regions of desired conductivities may be formed in the semiconductor, wafer 10 by ion implantation. It will be understood that an actual semiconductor device includes multiple implanted regions in a complex configuration and that the semiconductor device 10 of Fig. 1 is shown for illustrative purposes only.
  • An ion beam 12 of a dopant material is directed at wafer 10, producing an implanted region 14.
  • the depth of implanted region 14 is determined by a number of factors, including the energy and mass of the ions in ion beam 12.
  • the boundaries of implanted region 14 are typically defined by an implant mask 16.
  • the wafer is then annealed to activate the dopant material and to repair crystalline damage caused by ion implantation.
  • junction depth X j is the depth of the impurity region 20 normal to the surface of wafer 10 after annealing.
  • One of the goals in fabricating ultrashallow junctions is to minimize diffusion and to thereby limit the junction depth X j.
  • junction depth X j of impurity region 20 after annealing may be reduced in comparison with prior art processes by utilizing a novel thermal processing method including sub-melt laser annealing combined with low temperature rapid thermal annealing to form ultrashallow doped regions, with minimal thermal diffusion and without melting.
  • the process can be used to form ultrashallow, low sheet resistance junctions and to form deeper impurity regions where thermal diffusion after ion implantation is undesired.
  • a semiconductor wafer typically a silicon wafer, may be implanted with a dopant material in step 50.
  • Preferred dopant materials include, but are not limited to, boron, indium, arsenic, and phosphorous.
  • boron is implanted at ultralow energy, i.e., an energy less than 1 keV.
  • the dopant material may be implanted into the silicon wafer using a conventional ion implantation system, a plasma doping system or any other system capable of depositing or implanting the dopant material to a desired depth in the semiconductor wafer.
  • the wafer containing the dopant material is irradiated with laser energy in a laser anneal step.
  • the laser energy is sufficient to activate the dopant material without melting of the wafer.
  • the wafer is placed in a laser anneal chamber having a controlled ambient and is irradiated with laser energy having predetermined parameters.
  • the parameters of the laser anneal are selected to achieve a high wafer temperature, preferably in a range of about 1100°C to 1410°C, extremely rapidly without melting of the silicon or other wafer material. Because the silicon is not melted, the laser anneal step is referred to as "sub- melt" laser annealing.
  • the laser anneal step achieves dopant activation. Examples of suitable laser anneal parameters are described below.
  • Laser anneal step 52 preferably utilizes pulsed laser energy in a wavelength range of about 190 to 1500 nanometers.
  • One preferred laser is an excimer laser having an output wavelength of 308 nanometers.
  • Other suitable laser wavelengths include 532 nanometers and 1064 nanometers.
  • the laser energy should heat the silicon or other substrate material of the wafer to a depth of about 1 micrometer.
  • Certain structures, such as polysilicon layers, are thermally isolated from the bulk silicon by a dielectric. When the laser energy is absorbed throughout a deep layer of bulk silicon, the thin polysilicon layer absorbs very little of that energy. It has been found that use of longer wavelengths in the above range prevents unwanted melting of the polysilicon gate.
  • the laser energy density used to irradiate the wafer is selected to heat a surface layer of the wafer rapidly, preferably in less than about 10 microseconds, to a temperature in the range of about 1100°C to 1410°C that does not melt the silicon.
  • silicon melts at 1410°C.
  • the laser energy density is preferably in a range of about 0.50 to 0.58 joules per square centimeter (J/cm ) at a wavelength of 308 nanometers and a pulse width of 20 nanoseconds in order to achieve activation of the dopant material without melting of the silicon.
  • One or more laser pulses are preferably utilized to irradiate the wafer.
  • the number of pulses may be in a range from 1 to 10,000, and the pulse width may be in a range of about 1 to 10,000 nanoseconds.
  • the product of the number of laser pulses times the pulse width is preferably in a range from 1 to 1,000 microseconds. More preferably, the number of pulses is in a range of 100 to 1,000, and the pulse width is in a range of 10 to 100 nanoseconds.
  • 100 pulses, each having a pulse width of 20 nanoseconds are utilized to laser anneal a given area of the semiconductor wafer.
  • laser anneal step 52 may be performed by a modification of a system used for conventional laser annealing wherein an amorphized layer of the wafer is melted.
  • the parameters of the laser annealing system are modified to perform sub-melt laser annealing as described above.
  • One suitable system is model LA- 100 available from Verdant Technologies, which may be modified to perform sub-melt laser annealing as described above.
  • the laser beam utilized to irradiate the wafer may cover the entire wafer area or a sub-area that is less than the entire area of the wafer. In onb example, the laser beam has cross-sectional area of 10 millimeters by 10 millimeters at the wafer surface.
  • the wafer may be stepped or scanned with respect to the laser beam in order to cover the entire area of the wafer.
  • a first sub-area of the wafer may be irradiated with 100 pulses, each having a pulse width of 20 nanoseconds, and then the wafer may be moved, or stepped, relative to the laser beam to a second sub-area, and the second sub-area may be irradiated with 100 laser pulses, each having a pulse width of 20 nanoseconds. This stepping process is repeated until the entire wafer area has been irradiated.
  • a single sequence of laser pulses may be utilized to perform the laser anneal step.
  • the wafer may be stepped in small increments after one or more laser pulses, or it may be scanned continuously, so that the entire wafer surface receives the desired level of laser energy.
  • the wafer is held stationary, and the laser beam is deflected or otherwise moved relative to the stationary wafer in order to irradiate the entire wafer surface.
  • the wafer is heated in a low temperature rapid thermal anneal step.
  • the wafer is placed in a rapid thermal processing chamber having a controlled ambient and is heated according to predetermined parameters.
  • the low temperature rapid thermal anneal is preferably in a temperature range of about 650°C to 850°C for a time in a range of less than 1 second to 60 seconds.
  • the low temperature rapid thermal anneal repairs crystalline damage from the implant, so that the semiconductor devices have good mobilities and low leakage currents, but does not cause significant diffusion of the dopant material.
  • the wafer is heated to 700°C for 20 seconds in the low temperature rapid thermal anneal step. Rapid thermal annealing systems for semiconductor wafers are commercially available. One suitable system is model AST-3000 available from STEAG-AST.
  • the low temperature rapid thermal anneal step 54 is shown in Fig. 2 as following the laser anneal 52.
  • the low temperature rapid thermal anneal step 54 may be performed before laser anneal step 52.
  • the laser anneal step 52 may be performed in an enclosed chamber with a controlled ambient, preferably comprising oxygen in nitrogen at a pressure of one atmosphere.
  • the oxygen concentration in the laser anneal chamber is controlled during the laser anneal step 52 in a range of less than 1 to 1,000 parts per million.
  • the low temperature rapid thermal anneal step 54 may be performed in a thermal processing chamber with a controlled ambient, preferably comprising oxygen in nitrogen at a pressure of one atmosphere.
  • the oxygen concentration in the thermal processing chamber is controlled during the low temperature rapid thermal anneal step 54 in a range of less than 1 to 1 ,000 parts per million.
  • boron dopant profiles of Fig. 3 The benefits of the thermal processing method of the invention are illustrated in the boron dopant profiles of Fig. 3.
  • the dopant profiles shown in Fig. 3 were obtained by secondary ion mass spectrometry (SIMS).
  • SIMS secondary ion mass spectrometry
  • boron concentration in atoms per cubic centimeter is plotted as a function of depth from the wafer surface in angstroms for several different conditions.
  • silicon wafers were implanted with boron (B + ) ions at an energy of 1 keV and a dose of 9E14/cm 2 (the notation 9E14/cm 2 represents an implant dose of 9 x 10 14 atoms per square centimeter).
  • curve 70 represents a silicon wafer which was implanted with boron as described above, but was not annealed.
  • Curve 72 represents a silicon wafer which was implanted with boron as described above and was spike annealed for a time of 0.2 second at a temperature of 1050°.
  • Curve 74 represents a silicon wafer which was implanted with boron as described above and was rapid thermal annealed at 700°C for 20 seconds. The measured sheet resistance of this wafer was 3500 ohms per square.
  • Curve 76 represents a silicon wafer which was implanted with boron as described above and was laser annealed below the melting threshold with 100 laser pulses at a wavelength of 308 nanometers, and then was rapid thermal annealed at 700°C for 20 seconds.
  • Curve 76 clearly shows that no measurable diffusion has occurred and yet a sheet resistance of 360 ohms per square has been produced.
  • the junction depth at a concentration of 3E18/cm in the wafer represented by curve 76 was 372 angstroms.
  • the wafer represented by curve 74 exhibited a much higher sheet resistance, indicating that the dopant material had not been activated.
  • the spike annealed wafer represented by curve 72 exhibited significant diffusion of the dopant material, resulting in a junction depth of 561 angstroms. It will be understood that curves 70, 74 and 76 are nearly overlapping in Fig. 3.
  • the thermal processing technique described herein improves upon conventional high temperature rapid thermal annealing, either for a short time or a spike anneal, by only exposing the wafer to very high temperatures for a few microseconds, thereby minimizing thermal diffusion of dopant materials.
  • halo formation this means that boron can be used as the dopant material instead of indium, which is presently used due to its lower diffusion but is not preferable since its source material is corrosive and leads to low ion source lifetimes.
  • Another application of the disclosed process is the formation of source/drain extensions that are more abrupt than those formed by rapid thermal annealing. Source/drain extensions formed by this process have the abruptness of the as-implanted profile.
  • the invention also improves upon conventional laser annealing by eliminating melting of the silicon. This makes integration of the process into device process flows much easier and avoids dopant redistribution throughout the melted region. In addition, a preamorphizing implant is not required.

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Electromagnetism (AREA)
  • Optics & Photonics (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Recrystallisation Techniques (AREA)

Abstract

Cette invention a trait au traitement thermique d'une tranche de semi-conducteur contenant un dopant. On soumet cette tranche à un rayonnement laser suffisant pour activer le dopant sans la fondre. On procède ensuite à un recuit thermique rapide à une température relativement basse, afin de réparer tout dommage subi par les cristaux. L'activation du dopant se fait sans diffusion mesurable. Le recuit thermique rapide à une température relativement basse permet de réparer tout dommage subi par les cristaux, de sorte que les dispositifs selon cette invention font montre d'une bonne mobilité des porteurs de charge et que les courants de fuite sont faibles.
EP01916675A 2000-03-17 2001-03-15 Procede de formation de jonctions de tres faible profondeur par recuit laser et recuit thermique rapide Withdrawn EP1264335A1 (fr)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US19023300P 2000-03-17 2000-03-17
US190233P 2000-03-17
US63841000A 2000-08-11 2000-08-11
US638410 2000-08-11
PCT/US2001/008241 WO2001071787A1 (fr) 2000-03-17 2001-03-15 Procede de formation de jonctions de tres faible profondeur par recuit laser et recuit thermique rapide

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EP1264335A1 true EP1264335A1 (fr) 2002-12-11

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EP (1) EP1264335A1 (fr)
JP (1) JP4942128B2 (fr)
KR (1) KR100839259B1 (fr)
CN (1) CN1222016C (fr)
TW (1) TWI271791B (fr)
WO (1) WO2001071787A1 (fr)

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CN1419708A (zh) 2003-05-21
CN1222016C (zh) 2005-10-05
WO2001071787A1 (fr) 2001-09-27
KR20030066318A (ko) 2003-08-09
KR100839259B1 (ko) 2008-06-17
TWI271791B (en) 2007-01-21
JP4942128B2 (ja) 2012-05-30

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