TWI271791B - Use of sub-melt laser annealing and low temperature rapid thermal annealing to form ultrashallow junctions in semiconductor wafers - Google Patents

Use of sub-melt laser annealing and low temperature rapid thermal annealing to form ultrashallow junctions in semiconductor wafers Download PDF

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Publication number
TWI271791B
TWI271791B TW090106353A TW90106353A TWI271791B TW I271791 B TWI271791 B TW I271791B TW 090106353 A TW090106353 A TW 090106353A TW 90106353 A TW90106353 A TW 90106353A TW I271791 B TWI271791 B TW I271791B
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Taiwan
Prior art keywords
wafer
laser
energy
rapid thermal
irradiated
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TW090106353A
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Chinese (zh)
Inventor
Susan B Felch
Somit Talwar
Daniel F Downey
Carol M Gelatos
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Varian Semiconductor Equipment
Ultratech Stepper Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/268—Bombardment with radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Optics & Photonics (AREA)
  • Electromagnetism (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Recrystallisation Techniques (AREA)

Abstract

Methods are provided for thermal processing of a semiconductor wafer that contains a dopant material. The wafer is irradiated with laser energy sufficient to activate the dopant material without melting the wafer. In addition, rapid thermal annealing of the wafer is performed at relatively low temperature to repair crystalline damage. The dopant activation is achieved with no measurable diffusion. The low temperature rapid thermal anneal repairs crystalline damage, so that devices have good mobilities and low leakage currents.

Description

1271791 、 A7 —- __B7___ 五、發明說明（I ) 相關申請案參照 本申請案係主張臨時申請案案號60/190,233之利益’ 其申請日爲西元2000年3月17日，且該申請案在此倂入 作爲參考。 發明之領域 本發明係有關一種用於含有摻雜材質之半導體晶圓之 熱處理方法，尤其是指一種可藉由以熔心雷射退火及低溫 快速熱退火而達成在半導體晶圓中形成超淺接面之方法。 發明背景 離子植入係一種可將改變導電型態之摻雜材質植入半 導體晶圓之標準技術。於傳統之離子植入系統中，一個待 欲植入之摻雜材質先在離子源中被離子化，後再被加速形 成一具有預定能量之離子束，最後再被導引至晶圓之表面 。該具有能量之離子束穿透半導體材質之本體且被埋床在 該半導體材質之結晶格子中。接下來，該半導體晶圓需進 行一道退火步驟以活化被植入之摻雜材料和修復因離子植 入造成之結晶損傷。該退火步驟乃牽涉依據預定之退火時 間和溫度協定之半導體晶圓的熱處理。 目前在半導體業界要求將元件做得愈小，速度愈快乃 是眾所周知之趨勢。尤其是，在該半導體元件橫側面大小 和植入深度二者都一直縮減。最先進之半導體元件要求接 面深度小於1000埃（Aangstroms)且可能最終會要求接面 3 本紙張尺度適用中國國家標準（CNS)A4規格do X 297公釐） (請先閱讀背面之注意事項再填寫本頁) 裝---- 訂---------' 經濟部智慧財產局員工消費合作社印制 衣 1271791 A7 ___B7____ 五、發明說明（> ) 深度在200埃級數或更小。 該摻雜材質植入之深度係由植入該半導體晶圓之離子 能量來決定。淺接面係用低植入能量而達成。但是’用來 活化該被植入之摻雜材質的退火製程將造成該摻雑材質從 半導體晶圓中之植入區擴散。由於此種擴散之結果，接面 深度因退火而增加。爲了降低因退火造成接面深度增加之 效應，吾人可減少離子能量，使得在退火後獲得所需要之 接面深度。這種改進除了在超滲接面之特例外’基本上可 提供一滿意之結果。但是藉由降低離子能量以減少接面深 度之技術仍具有一極限，此乃因在退火之同時該摻雜材質 無可避免還是會擴散。 在仍保持可活化該摻雜材質狀態下，已嘗試各種努力 來發展可限制該摻雜材質擴散之退火製程。當要求最小量 熱擴散時，一種快速熱退火或尖峰式退火常被典型地使甩 到。快速熱退火基本上包含將該晶圓加熱至950°C至1100 工且時間爲1至30秒，而尖峰退火可能牽涉到小於0.1秒 之退火時間。在PCT公告號W099/39381專利案中揭露一 種方法將可控制低濃度之氧氣可加入氮氣環境中以達到最 小熱擴散之效果。不管如何地選擇退火參數，快速熱退火 或尖峰熱退火仍會造成該摻雜材質之熱擴散、加強型暫能 擴散、氧化加強型擴散及摻雜加強型擴散（即例如硼雜質 或磷雜質本身就會加強性擴散）。甚至，當低濃度的氧氣 被加入氮氣環境中且使用非常低能量的植入被進行時，該 熱擴散仍發生。 4 (請先閱讀背面之注意事項再填寫本頁)1271791, A7 —- __B7___ V. INSTRUCTIONS (I) RELATED APPLICATIONS This application claims the benefit of the provisional application number 60/190,233, whose application date is March 17, 2000, and the application is This intrusion is used as a reference. FIELD OF THE INVENTION The present invention relates to a heat treatment method for a semiconductor wafer containing a doped material, and more particularly to an ultra-shallow formation in a semiconductor wafer by melt laser annealing and low temperature rapid thermal annealing. The method of junction. BACKGROUND OF THE INVENTION Ion implantation is a standard technique for implanting doped materials that change conductivity patterns into semiconductor wafers. In a conventional ion implantation system, a doping material to be implanted is first ionized in an ion source, then accelerated to form an ion beam having a predetermined energy, and finally guided to the surface of the wafer. . The energy ion beam penetrates the body of the semiconductor material and is buried in the crystal lattice of the semiconductor material. Next, the semiconductor wafer is subjected to an annealing step to activate the implanted dopant material and repair crystal damage caused by ion implantation. The annealing step involves heat treatment of the semiconductor wafer in accordance with a predetermined annealing time and temperature agreement. The smaller the components are required to be made in the semiconductor industry, the faster the speed is a well-known trend. In particular, both the lateral side size and the implantation depth of the semiconductor element are reduced. The most advanced semiconductor components require a junction depth of less than 1000 angstroms (Aangstroms) and may eventually require junction 3. This paper scale applies to the Chinese National Standard (CNS) A4 specification do X 297 mm) (please read the notes on the back first) Fill in this page) Pack---- Order---------' Ministry of Economic Affairs Intellectual Property Bureau Staff Consumer Cooperative Printed Clothes 1271791 A7 ___B7____ V. Invention Description (>) Depth in 200 angstroms or more small. The depth of implantation of the doped material is determined by the ion energy implanted in the semiconductor wafer. Shallow junctions are achieved with low implant energy. However, the annealing process used to activate the implanted doped material will cause the erbium doped material to diffuse from the implanted regions in the semiconductor wafer. As a result of this diffusion, the junction depth increases due to annealing. In order to reduce the effect of increased joint depth due to annealing, we can reduce the ion energy so that the desired junction depth is obtained after annealing. This improvement, in addition to the exceptional exceptions in the hyperosmotic junction, provides essentially a satisfactory result. However, the technique of reducing the ion depth to reduce the junction depth still has a limit because the doping material is inevitable or diffuses while annealing. While still maintaining the state of the doped material, various attempts have been made to develop an annealing process that limits the diffusion of the doped material. A rapid thermal or sharp anneal is often typically entangled when a minimum amount of thermal diffusion is required. Rapid thermal annealing essentially involves heating the wafer to 950 ° C to 1100 MPa for 1 to 30 seconds, while spike annealing may involve an annealing time of less than 0.1 seconds. A method disclosed in PCT Publication No. WO99/39381 discloses that a low concentration of oxygen can be controlled to be added to a nitrogen atmosphere for minimal heat diffusion. Regardless of how the annealing parameters are selected, rapid thermal annealing or peak thermal annealing will still cause thermal diffusion, enhanced transient diffusion, oxidative enhanced diffusion, and doped enhanced diffusion of the doped material (ie, for example, boron impurities or phosphorus impurities themselves). Will strengthen the spread). Even when a low concentration of oxygen is added to the nitrogen atmosphere and is carried out using a very low energy implant, this thermal diffusion still occurs. 4 (Please read the notes on the back and fill out this page)

n I ·ϋ n 1· ϋ )OJ· ft— IBP 11 n ϋ ϋ I 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公楚) 一~^ ：~· 麵 1271791 A7 B7 五、發明說明（々） (請先閱讀背面之注意事項再填寫本頁) 如同在美國專利號5,908,307 (於1999年6月1日發給 Talwar等人）和美國專利號5,956,603 (於1999年9月21 曰發給Talwar等人）中所揭露，另外一種已知的退火技術 是雷射退火。一晶圓之表面被形成一非晶圓且一摻雜材質 被植入該非晶表面層。之後，該非晶表面層以足夠的雷射 能量加以照射致使其熔化，此時可將該摻雜材質被分佈在 該整個熔化之矽區域。將雷射退火製程與傳統元件製程整 合在一起是非常複雜的。矽或鍺之非晶化前植入是需要的 ，以避免使多晶矽閘極熔化，且沈積一抗反射金屬層亦是 需要的。 在曰本的應用物理期刊，第31卷，pt2 , 6A號，1992 年中第659-662頁作者H.Tsukamoto等人論文名稱“以激態 分子（excimer)雷射退火形成超淺接面”中揭露一種藉由 BF/離子植入及單脈衝雷射退火以達成淺接面之技術。上 述揭露的製程如果雷射能量密度太低以致無法熔化將導致 高片電阻（Sheet resistance)。 經濟部智慧財產局員工消費合作社印製 在美國專利號4，151，008 (於1979年發給Kirk pathck 中揭露一種可在半導體元件上選擇性地以脈衝雷射或閃光 燈泡作短期間加以熱處理。假如光能量密度太低而無法產 生熔化，則該揭露的製程亦產生高片電阻。 截至目前習知之半導體晶圓熱退火皆會產一至多項缺 點，這些缺點包含（但不限於）無法接受之摻雜材質擴散 程度、高片電阻及過度的製程複雜度。因此，有必要提出 一種改良之半導體晶圓退火方法以達到吾人要求之所需之 5 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 1271791 經齊部智慧財產局員工消費合作社印製 A7 B7 五、發明說明（4) 摻雜材質之分佈及片電阻，且同時g亥方法亦修復結晶受損 將擴散最小化及亦不造成製造過程上之過度的複雜度。， 發明槪要 依據本發明之第一方面，係提供一種用於將含有摻雜 材質之半導體晶圓熱處理之方法。該摻雜材質可藉離子植 入法、電漿沈積或任何其他適當沈積技術將其植入或沈積 在該半導體晶圓內。本方法包含以足夠雷射能量活化該摻 雜材質但不使該晶圓熔化及藉由在相對低溫下將該晶圓快 速熱退火以修復結晶受損等步驟。 最好是該以雷射能量照射該晶圓之步驟係足以加熱該 晶圓至溫度在大約1100°C到14HTC間的範圍內，且該晶圓 之快速熱退火步驟係將該晶圓加熱至大約650°C至850°C間 的範圍內並爲期少於1到60秒。 較佳係，該被植入之晶圓係以波長在大約190至1500 納米（nanometer)間之雷射能量照射。在本發明之一實施 例中，該被植入之晶圓係被具有波長308納米之雷射能量 照射。其他適當雷射光波長包括532及1064納米。用於照 射晶圓之雷射能量可包含一個或多個雷射脈衝。該晶圓可 被含有100至1000個雷射脈衝之雷射能量加以照射且該雷 射脈衝之脈衝寬度可在10至100納秒之間。將雷射脈衝數 與脈衝寬度之乘積後可在1至1000微秒（microsecond)之 間。在本發明之一實施例中，係採用具有脈衝寬度大約爲 20納秒之多重雷射脈衝。 6 本紙張尺度適用中國國家標準（CNS)A4規格（2]0 X 297公釐） ϋ mm·*— ϋ n n n I ϋ n ϋ · ϋ« l d ϋ n ϋ n 一 0, n mm— I ϋ n ϋ I I (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 1271791 A7 ____B7__ 五、發明說明（< ) 本發明雷射退火步驟可在含有氧氣之氮氣環境中完成 ，其中氧氣濃度係於晶圓之雷射照射期間控制在少於百萬 分之一至百萬分之一仟間。快速熱退火步驟係在含有氧氣 之氮氣環境中完成，其中氧氣濃度係晶圓之快速熱退火期 間控制在少於百萬分之一至百萬分之一仟間。 依據本發明之第二方面，係提供一種用在半導體晶圓 內形成一被雜質摻雜之區域的方法。該方法包含下述步驟 ，先植入一摻雜材質進入一半導體晶圓、再以足夠雷射能 量照射該晶圓以活化該摻雜材質且不使晶圓熔化、及再藉 將該被植入之晶圓加以在相對低溫下快速熱退火而修復結 晶受損。 本發明所提供之方法可達到活化摻雜材質且不致產生 大量擴散之目的。快速熱退火可修復由於摻雜材質植入時 造成之結晶受損，所以本發明之元件具有良好遷移率（ mobility)及低漏電流。藉由消除矽熔化將可避免該摻雜材 質在整個熔化區域內分佈。 圖式簡單說明 爲了能更進一步了解本發明，在此將包含下面附圖說 明以供參考，其中： 圖1爲一簡化和部份剖面之一半導體晶圓； 圖2爲依據本發明之製程實施例之流程圖； 圖3爲用於各種製程之硼濃度（厚子數/立方厘米）: 在不同深度（單位埃）之分佈圖，其中亦包含本發明製程 7 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ------II--I · I I---1 I ^ ·11111 111^¾ (請先閱讀背面之注意事項再填寫本頁) 1271791 A7 ___B7 __ 五、發明說明（b ) 之一實施例。 (請先閱讀背面之注意事項再填寫本頁) 詳細說明 圖1爲一高度簡化之半導體晶圓10之部份剖面圖。藉 由離子植入可在該半導體晶圓10內形成所需要導電型態之 區域和接面。我們知道實際半導體元件係包含在一個複雜 組構內具有多個植入區域並且也知道圖1之半導體元件10 僅係爲了易於說明。一摻雜材質之離子束12被導向該晶圓 10以產生一植入區域14。該植入區域14之深度係由數個 因素來決定，其中包含離子束12中離子之能量和質量。基 本上該植入區域14之界面乃由植入光罩16所定義出。該 晶圓然後做退火以活化該摻雜材料及修復由於離子植入時 造成之結晶受損。 經濟部智慧財I局員工消費合作社印製 習知技術退火製程將造成該摻雜材質擴散形成一雜質 區域20且該雜質區域20比植入區域14來得大且深。該雜 質區域20係以一接面深度Xj來特性化，且該接面深度爲 該晶圓10退火後雜質區域20垂直該晶圓10表面之深度。 在製程超淺接面之目的之一是將擴散最小化並藉此限制該 接面深度X」。 已發現到在退火後的雜質區域20之接面深度Xj比起 習知製程可藉一新穎熱處理方法加以減少，而該新穎熱處 理方法係包括次熔化雷射退火倂用低溫快速熱退火以形成 超淺摻雜區且達到最小熱擴散和不會使晶圓之表面矽熔化 。上述製程可被用來形成超淺及低片電阻之接面且同時形 8 本紙張尺玉適用一中國—1Ϊ家標準(石^六4規格—(21〇 χ 297公釐） 一~ - · '一― 1271791 A7 B7 五、發明說明（ι| ) 秒。曲線74代表一如上述方法硼離子植入後之矽晶圓且經 由溫度7〇°C爲期20秒之快速熱退火。該晶圓經由測其片電 阻爲3500歐姆/平方。曲線76代表一如上述方法硼離子 植入後之矽晶圓且經由一低於矽熔點下之含有1〇〇個雷射 脈衝波長爲308納米之雷射退火及再經一溫度700°C時間 20秒之快速熱退火。 曲線76淸楚顯現了並未發生大量擴散且產生一 360歐 姆/平方之片匣阻。在曲線76中在該晶圓在硼濃度爲3E 18/立方厘米時之深度爲372埃。經由對比發現曲線74所 代表之矽晶圓存在一非常高之片匣阻，其顯示出該摻雜材 質並沒有被活化。曲線72代表一被尖峰退火之矽晶圓，它 具有摻雜材質之大量擴散以致造成接面深度爲561埃。由 圖3很容易看出曲線70，74及76幾乎重疊。 在此所述之熱處理技術藉由僅將該晶圓曝露在非常高 溫且時間爲微秒內，因而比起傳統高溫快速熱退火不論爲 期短時間或是尖峰退火均獲得改良，並藉此將摻雜材質熱 擴散予以最小化。爲了形成暈圏的運用，意即該硼元素可 代替銦元素做爲摻雜材質，雖然銦元素是目前因其具有低 擴散而被使用但其不是較佳選擇，此乃因銦材質具有腐蝕 性會導致離子源生命期的降低。另一上述揭露技術的運用 係形成一具有較快速熱退火更陡峭接面之源極/汲極延展 面。由上述揭露技術形成之源極/汲極延展面之接面陡峭 度和離子植入後分佈之陡峭度相同。 本發明藉由可消除矽熔化而將傳統雷射退火加以改良 13 (請先閱讀背面之注意事項再填寫本頁) 裝---- 訂-------- 瘦齊即智慧財轰局員工消費合作社印制衣 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）n I ·ϋ n 1· ϋ )OJ· ft— IBP 11 n ϋ ϋ I Ministry of Economic Affairs Intellectual Property Bureau Staff Consumer Cooperative Printed This paper scale applies China National Standard (CNS) A4 specification (210 X 297 public Chu) ^ :~· Face 1271791 A7 B7 V. Description of Invention (々) (Please read the note on the back and then fill out this page) as in US Patent No. 5,908,307 (issued to Talwar et al. on June 1, 1999) and the United States Another known annealing technique is laser annealing, as disclosed in Patent No. 5,956,603 (issued to Talwar et al. on September 21, 1999). The surface of a wafer is formed into a non-wafer and a doped material is implanted into the amorphous surface layer. Thereafter, the amorphous surface layer is irradiated with sufficient laser energy to cause it to melt, and the doping material may be distributed throughout the molten crucible region. Integrating a laser annealing process with a traditional component process is very complicated. Pre-amorphization implantation of tantalum or niobium is required to avoid melting the polysilicon gate and depositing an anti-reflective metal layer is also desirable. In the Journal of Applied Physics, Sakamoto, Vol. 31, pt. 2, No. 6A, 1992, pp. 659-662, author H. Tsukamoto et al., entitled "Excimer Laser Annealing to Form Ultra-Shallow Junctions" A technique for achieving shallow junctions by BF/ion implantation and single pulse laser annealing is disclosed. The process disclosed above if the laser energy density is too low to melt will result in a sheet resistance. The Ministry of Economic Affairs' Intellectual Property Office employee consumption cooperative was printed in US Patent No. 4,151,008 (issued to Kirk Pathck in 1979 to expose a heat treatment that can be selectively applied to a semiconductor component with a pulsed laser or flash bulb for a short period of time. If the optical energy density is too low to cause melting, the disclosed process also produces high sheet resistance. As far as the conventional semiconductor wafer thermal annealing is concerned, one or more shortcomings are produced, including but not limited to unacceptable Doping material diffusion degree, high sheet resistance and excessive process complexity. Therefore, it is necessary to propose an improved semiconductor wafer annealing method to meet the requirements of our 5 paper standards applicable to China National Standard (CNS) A4 specifications. (210 X 297 mm) 1271791 Printed by Qiqi Intellectual Property Bureau employee consumption cooperative A7 B7 V. Invention description (4) Doping material distribution and sheet resistance, and at the same time ghai method also repairs crystal damage and minimizes diffusion And does not cause excessive complexity in the manufacturing process. The invention is based on the first aspect of the invention, providing a A method for heat treating a semiconductor wafer containing a doped material. The doped material can be implanted or deposited in the semiconductor wafer by ion implantation, plasma deposition, or any other suitable deposition technique. The method includes the steps of activating the doped material with sufficient laser energy but not melting the wafer and rapidly annealing the wafer at a relatively low temperature to repair crystal damage. Preferably, the laser is irradiated. The step of the wafer is sufficient to heat the wafer to a temperature in the range of between about 1100 ° C and 14 HTC, and the rapid thermal annealing step of the wafer heats the wafer to between about 650 ° C and 850 ° C. The range is less than 1 to 60 seconds. Preferably, the implanted wafer is irradiated with a laser energy having a wavelength between about 190 and 1500 nanometers. In an embodiment of the invention The implanted wafer is illuminated by a laser having a wavelength of 308 nm. Other suitable laser wavelengths include 532 and 1064 nm. The laser energy used to illuminate the wafer may include one or more laser pulses. The wafer can be contained 100 to 1 The laser energy of 10,000 laser pulses is illuminated and the pulse width of the laser pulse can be between 10 and 100 nanoseconds. The product of the number of laser pulses and the pulse width can be between 1 and 1000 microseconds. In one embodiment of the invention, multiple laser pulses having a pulse width of approximately 20 nanoseconds are employed. 6 This paper scale applies to the Chinese National Standard (CNS) A4 specification (2] 0 X 297 mm) ϋ mm·*— ϋ nnn I ϋ n ϋ · ϋ« ld ϋ n ϋ n 0, n mm — I ϋ n ϋ II (Please read the note on the back and fill out this page) Ministry of Economic Affairs Intellectual Property Office staff consumption Co-op printing 1271791 A7 ____B7__ V. INSTRUCTION DESCRIPTION (<) The laser annealing step of the present invention can be carried out in a nitrogen atmosphere containing oxygen, wherein the oxygen concentration is controlled to less than 1 part per million during laser exposure of the wafer. One to one millionth of a day. The rapid thermal annealing step is carried out in a nitrogen atmosphere containing oxygen, wherein the oxygen concentration is controlled during the rapid thermal annealing of the wafer to less than one part per million to one millionth of a day. According to a second aspect of the present invention, there is provided a method of forming a region doped with impurities in a semiconductor wafer. The method comprises the steps of first implanting a doped material into a semiconductor wafer, illuminating the wafer with sufficient laser energy to activate the doped material without melting the wafer, and borrowing the implanted The incoming wafer is subjected to rapid thermal annealing at relatively low temperatures to repair crystal damage. The method provided by the invention can achieve the purpose of activating the doping material without causing a large amount of diffusion. Rapid thermal annealing repairs crystal damage due to implantation of the doped material, so the elements of the present invention have good mobility and low leakage current. The doping of the dopant material throughout the melting zone can be avoided by eliminating the melting of the crucible. BRIEF DESCRIPTION OF THE DRAWINGS In order to provide a further understanding of the present invention, the following description of the drawings will be incorporated herein by reference, in which: FIG. 1 is a simplified and partially sectioned semiconductor wafer; FIG. 2 is a process implementation in accordance with the present invention. Figure 3 is a flow chart of boron concentration (thickness/cubic centimeters) used in various processes: distribution at different depths (in angstroms), which also includes the process of the present invention. 7 The paper scale applies to the Chinese national standard (CNS) )A4 size (210 X 297 mm) ------II--I · I I---1 I ^ ·11111 111^3⁄4 (Please read the notes on the back and fill out this page) 1271791 A7 ___B7 __ V. Description of the invention (b) One embodiment. (Please read the note on the back and fill out this page.) Detailed Description Figure 1 is a partial cross-sectional view of a highly simplified semiconductor wafer 10. The regions and junctions of the desired conductivity type can be formed within the semiconductor wafer 10 by ion implantation. It is known that the actual semiconductor component comprises a plurality of implanted regions within a complex fabric and that the semiconductor component 10 of Figure 1 is also known for ease of illustration. A doped material ion beam 12 is directed to the wafer 10 to create an implanted region 14. The depth of the implanted region 14 is determined by a number of factors including the energy and mass of the ions in the ion beam 12. The interface of the implanted region 14 is substantially defined by the implanted reticle 16. The wafer is then annealed to activate the dopant material and repair damage to the crystal due to ion implantation. Printed by the Ministry of Economic Affairs, the Ministry of Economic Affairs, and the Consumers' Cooperatives, the conventional annealing process will cause the doped material to diffuse to form an impurity region 20 which is larger and deeper than the implanted region 14. The impurity region 20 is characterized by a junction depth Xj, and the junction depth is the depth of the impurity region 20 perpendicular to the surface of the wafer 10 after the wafer 10 is annealed. One of the purposes of the ultra-shallow junction of the process is to minimize diffusion and thereby limit the junction depth X". It has been found that the junction depth Xj of the impurity region 20 after annealing can be reduced by a novel heat treatment method which involves sub-melting laser annealing and low temperature rapid thermal annealing to form a super. The shallow doped region achieves minimal thermal diffusion and does not melt the surface of the wafer. The above process can be used to form the junction of ultra-shallow and low-sheet resistance and at the same time shape 8 paper size jade is applicable to a Chinese--1 standard (stone ^ 6 4 specifications - (21 〇χ 297 mm) one ~ - · '一一 1271791 A7 B7 V. DESCRIPTION OF THE INVENTION (ι| ) sec. Curve 74 represents a rapid thermal annealing of a germanium wafer after boron ion implantation as described above and a temperature of 7 〇 ° C for 20 seconds. The circle is measured to have a sheet resistance of 3500 ohms/square. Curve 76 represents a germanium wafer after boron ion implantation as described above and has a wavelength of 308 nm via a laser beam having a melting point below the melting point of 矽. The laser is annealed and further subjected to a rapid thermal annealing at a temperature of 700 ° C for 20 seconds. Curve 76 shows that no large amount of diffusion has occurred and a 360 ohm/square chip resistance is generated. In the curve 76 in the wafer The depth at a boron concentration of 3E 18/cm 3 was 372 angstroms. It was found by comparison that a very high sheet resistance was observed for the germanium wafer represented by curve 74, which showed that the doped material was not activated. Represents a silicon wafer annealed by a spike, which has a large amount of doped material The resulting junction depth is 561 angstroms. It is easy to see from Figure 3 that the curves 70, 74 and 76 overlap almost. The heat treatment technique described herein exposes the wafer to very high temperatures and in microseconds. Therefore, compared with the conventional high-temperature rapid thermal annealing, the short-time or spike annealing is improved, and the thermal diffusion of the doping material is minimized. In order to form the use of syncope, the boron element can replace the indium element. As a doping material, although indium is currently used because of its low diffusion, it is not a good choice, because the indium material is corrosive, which leads to a decrease in the lifetime of the ion source. Another application of the above disclosed technology A source/drain extension having a steeper junction of a faster thermal anneal is formed. The junction steepness of the source/drain extension formed by the above disclosed technique is the same as the steepness of the distribution after ion implantation. The invention improves the conventional laser annealing by eliminating the melting of the crucible 13 (please read the note on the back and then fill in the page). Pack---- Order-------- Bureau staff consumption This paper printed cooperatives clothes scale applicable Chinese National Standard (CNS) A4 size (210 X 297 mm)

Claims (1)

六、申請專利範圍 ' 1. 一種用以處理含有一摻雜材質之半導體晶圓的方法 ，係包括下列步驟： 〆 在一雷射退火腔中以雷射能量照射該晶圚，其中該雷 射能量係以足夠活化該摻雜材質且不使該晶圓熔化，該雷 射能量包含一或多個雷射脈衝’其將晶圓之表面層加熱至 1100°C至14.1〇°C的溫度範圍內，其中雷射脈衝數量乘以雷 射脈衝的脈衝寬度之乘積係在於1微秒至1000微秒的範圍 內；及 在一快速熱處理腔中將該晶圓在相對低溫下予以快速 熱退火該晶圓以修復結晶受損，其中該晶圓之快速熱退火 步驟係在以雷射能量照射該晶圓之步驟之前或是之後實施 〇 2. 如申請專利範圍第1項所述之方法’其中該晶圚之 快速熱退火之步驟係足夠使該晶圓加熱到溫度大約在650°C 到850°C，間且時間在1秒到60秒間。 3. 如申請專利範圍第1項所述之方法’其中該晶圓係 以一具有波長308納米之激化分子雷射之雷射能量加以照 射。 4. 如申請專利範圍第1項所述之方法’其中該晶圓係 以具有波長532納米之雷射能量加以照射。 5. 如申請專利範圍第1項所述之方法，其中該晶圓係 以具有波長1064納米之雷射能量加以照射。 6. 如申請專利範圍第1項所述之方法，其中該晶圓係 以具有波長190納米到1500納米間之雷射能量加以照射。 ----------------------:1 哀—·……1T...............-線 I (請先閲讀背面之注意事項再填寫本頁) 國家標準（CNS)A4規格（2】0 X 297公笈） 1271791 Ay B8 CS D8 月4日修正 六、申請專利範圍 7. 如申請專利範圍第1項所述之方法，其中該晶圓係 以包含複數個雷射脈衝之雷射能量加以照射:。 8. 如申請專利範圍第1項所述之方法，其中該晶圓係 以包含1到10000個雷射脈衝之雷射能量加以照射。 9. 如申請專利範圍第1項所述之方法_，其中該晶圓係 以包含具有脈衝寬度在1納秒到10000納秒間之雷射脈衝 之雷射能量加以照射。 10. 如申請專利範圍第1項所述之方法，其中該晶圓係 以包含100到1000個雷射脈衝且該雷射脈衝之脈衝寬度是 在10納秒到100納秒之間之雷射能量加以照射。 11·如申請專利範圍第1項所述之方法，其中該晶圓係 以包含一或多個具有脈衝寬度20納秒之雷射脈衝之雷射能 量加以照射。 12·如申請專利範圍第1項所述之方法.，其中該晶圓係 以具有能量密度在0.50到0.58 J/cm2之間且波長爲308納 米之雷射能量加以照射。 13.·如申請專利範圍第1項所述之方法，其中該晶圓之 快速熱退火步驟之工作期間爲20秒。 14·如申請專利範圍第13項所述之方法，其中該晶圓 之快速熱退火步驟包含加熱該晶圓到溫度爲大約700°C。 15·如申請專利範圍第1項所述之方法，係更進一步包 含在以雷射能量照射該晶圓步驟中控制該氧氣濃度在百萬 分之1到百萬分之1000之步驟。 16·如申請專利範圍第1項所述之方法.，係更進一步包 ]6 ------------------------..........ΐτ..............線， (請先閲讀背面之注意事項再塡寫本頁) 本紙張尺度適用中國固家標準（CNS)A4規格（210 X 297公釐)VI. Application for Patent Scope 1. A method for processing a semiconductor wafer containing a doped material includes the steps of: illuminating the wafer with laser energy in a laser annealing chamber, wherein the laser The energy is sufficient to activate the doping material without melting the wafer, the laser energy comprising one or more laser pulses 'heating the surface layer of the wafer to a temperature range of 1100 ° C to 14.1 ° C The product of the number of laser pulses multiplied by the pulse width of the laser pulse is in the range of 1 microsecond to 1000 microseconds; and the wafer is rapidly thermally annealed at a relatively low temperature in a rapid thermal processing chamber. The wafer is damaged by repairing crystals, wherein the rapid thermal annealing step of the wafer is performed before or after the step of irradiating the wafer with laser energy. 2. The method of claim 1 wherein The rapid thermal annealing step of the wafer is sufficient to heat the wafer to a temperature of between about 650 ° C and 850 ° C for a period of between 1 second and 60 seconds. 3. The method of claim 1, wherein the wafer is irradiated with a laser energy having an excitation molecular laser having a wavelength of 308 nanometers. 4. The method of claim 1, wherein the wafer is irradiated with a laser energy having a wavelength of 532 nm. 5. The method of claim 1, wherein the wafer is irradiated with a laser energy having a wavelength of 1064 nm. 6. The method of claim 1, wherein the wafer is irradiated with a laser energy having a wavelength between 190 nm and 1500 nm. ----------------------: 1 哀—·......1T...............-line I (please Read the following notes on the back and fill out this page. National Standard (CNS) A4 Specification (2) 0 X 297 mm) 1271791 Ay B8 CS D8 Revision 4 on June 4, Patent Application Range 7. If the patent application scope is item 1 The method wherein the wafer is illuminated with a laser energy comprising a plurality of laser pulses: 8. The method of claim 1, wherein the wafer is irradiated with a laser energy comprising from 1 to 10,000 laser pulses. 9. The method of claim 1, wherein the wafer is irradiated with a laser energy comprising a laser pulse having a pulse width between 1 nanosecond and 10,000 nanoseconds. 10. The method of claim 1, wherein the wafer is a laser comprising 100 to 1000 laser pulses and the pulse width of the laser pulse is between 10 nanoseconds and 100 nanoseconds. The energy is irradiated. 11. The method of claim 1, wherein the wafer is illuminated with one or more laser energies having a laser pulse having a pulse width of 20 nanoseconds. 12. The method of claim 1, wherein the wafer is irradiated with a laser energy having an energy density between 0.50 and 0.58 J/cm 2 and a wavelength of 308 nm. 13. The method of claim 1, wherein the rapid thermal annealing step of the wafer is performed for 20 seconds. The method of claim 13, wherein the rapid thermal annealing step of the wafer comprises heating the wafer to a temperature of about 700 °C. 15. The method of claim 1, further comprising the step of controlling the oxygen concentration from 1 part per million to 1000 parts per million in the step of irradiating the wafer with laser energy. 16·If you apply for the method described in item 1 of the patent scope, it is a further package]6 ------------------------..... .....ΐτ..............Line, (Please read the note on the back and write this page first) This paper size applies to China National Standard (CNS) A4 specification ( 210 X 297 mm) 六、申請專利範圍 含在快速熱退火該晶圓之步驟中控制該氧氣濃度在百萬分 之1到百萬分之1000之步驟。 17. 如申請專利範圍第1項之方法，係包括下列步驟： 植入一摻雜材質於該半導體晶圓內。 18. 如申請專利範圍第17項所述之方法，其中該植入 一摻雜材質於該半導體晶圓內之步驟包含植入硼。 19. 如申請專利範圍第17項所述之方法，其中該植入 一摻雜材質於該半導體晶圓內之步驟係包含所植入之材質 係選自由硼、銦、砷及磷元素組成的一群組中。 (請先閱讀背面之注意事項/V寫本頁) 裝 '1T 線 17 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）Sixth, the scope of application for patents The step of controlling the oxygen concentration in the step of rapidly thermally annealing the wafer is in the range of 1 part per million to 1000 parts per million. 17. The method of claim 1, wherein the method comprises the steps of: implanting a doped material into the semiconductor wafer. 18. The method of claim 17, wherein the step of implanting a doped material into the semiconductor wafer comprises implanting boron. 19. The method of claim 17, wherein the step of implanting a doped material into the semiconductor wafer comprises implanting a material selected from the group consisting of boron, indium, arsenic, and phosphorus. In a group. (Please read the note on the back/V to write this page) Install '1T line 17 This paper size applies to China National Standard (CNS) A4 specification (210 X 297 mm)
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