EP1157413A2 - Procede de production de composants semi-conducteurs hautement dopes - Google Patents

Procede de production de composants semi-conducteurs hautement dopes

Info

Publication number
EP1157413A2
EP1157413A2 EP00912386A EP00912386A EP1157413A2 EP 1157413 A2 EP1157413 A2 EP 1157413A2 EP 00912386 A EP00912386 A EP 00912386A EP 00912386 A EP00912386 A EP 00912386A EP 1157413 A2 EP1157413 A2 EP 1157413A2
Authority
EP
European Patent Office
Prior art keywords
glass layer
wafer
dopant
approximately
neutral
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
EP00912386A
Other languages
German (de)
English (en)
Inventor
Richard Spitz
Alfred Goerlach
Barbara Will
Helga Uebbing
Roland Riekert
Christian Adamski
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Robert Bosch GmbH
Original Assignee
Robert Bosch GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Robert Bosch GmbH filed Critical Robert Bosch GmbH
Publication of EP1157413A2 publication Critical patent/EP1157413A2/fr
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H01L29/6609—Diodes
    • H01L29/66136—PN junction diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H01L21/2251—Diffusion into or out of group IV semiconductors
    • H01L21/2254—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides
    • H01L21/2255—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides the applied layer comprising oxides only, e.g. P2O5, PSG, H3BO3, doped oxides

Definitions

  • the invention is based on a method for producing semiconductor components according to the preamble of the independent claim. It is known in the manufacture of
  • the method according to the invention with the features of the independent claim has the advantage that doped regions can be produced with very good homogeneity.
  • a further advantage is that it is possible to have such homogeneous regions of different doping types in only one, both on the front and on the back of the semiconductor wafer Introduce diffusion step. It is also possible to provide different levels of dopant concentrations on the front and back. The heating of the wafer and thus the driving of the doping atoms into the interior of the wafer to produce doped areas at high temperatures in the
  • a range of approximately 1200 to 1280 degrees Celsius advantageously ensures a deep and concentrated penetration of the doping atoms into the wafer.
  • a chemical vapor deposition process in particular a chemical vapor deposition process at atmospheric pressure (APCVD, “Atmospheric Pressure Chemical Vapor Deposition”), to coat the wafer surfaces with doping atoms.
  • APCVD atmospheric pressure Chemical Vapor Deposition
  • the glass layer provided with dopant with a neutral glass layer before the diffusion process. This will make one mutual influencing of the doping of the front and back or of different wafers set up at the same time in the diffusion open is reliably prevented.
  • FIG. 1 shows a wafer with an applied glass layer
  • FIG. 2 shows a wafer after a diffusion process
  • FIG. 3 shows a wafer after removal of the glass layer.
  • FIG. 1 shows a side view of a wire-sawed raw wafer 1 with high surface roughness, on the front of which a p-doped glass layer 2 and on the back of which an n-doped glass layer 4 is applied.
  • the doped glass layers 2 and 4 are covered with a neutral glass layer 3 and 5, respectively.
  • Glass layers 2 and 4 serve to cover the wafer with dopants.
  • Vapor deposition process under atmospheric pressure there for example, the front of the wafer is first exposed to a silane gas in that the gas injectors to be passed on the conveyor belt flow onto the surface of the wafer with the gas.
  • B2H6 is mixed with the silane gas.
  • the silane disintegrates on the wafer surface at 380 degrees Celsius and reacts with oxygen to form silicon dioxide. Due to the B2H6 admixture, this glass is mixed with a p-type dopant.
  • the glass layer 2 is grown up to a layer thickness of approximately 2 micrometers. The admixture of the
  • B2H6 gas has been chosen so that the glass layer has a boron content of approximately 6 percent by weight.
  • the glass layer is then exposed to the same silane gas, but without the addition of B2H6.
  • the neutral glass layer 3 grows on the glass layer 2.
  • the process is ended when the neutral glass layer 3 has a thickness of approximately 0.5 micrometers.
  • the wafer is turned over and correspondingly coated with an n-doped glass layer 4 (thickness 2 micrometers, phosphorus content of approximately 6 percent by weight) on the back.
  • the n-doping is achieved by adding the silane gas instead of B2H6 PH3.
  • a neutral glass layer 5 with a thickness of 0.5 micrometers is then applied analogously to the front.
  • TEOS "tetra-ethyl-orthosilicate”
  • Si (OC 2 H 5 ) 4 gas is used instead of silane gas used, which is on the
  • the doping is carried out by admixing gas with trimethyl phosphate or trimethyl borate.
  • FIG. 2 shows the wafer after a diffusion process, with a heavily p-doped region 10 and a heavily n-doped region 11.
  • a plurality of wafers to be processed simultaneously are arranged upright in an arrangement made of silicon carbide or polysilicon. This heating is maintained for approximately 20 to 30 hours, preferably 21 hours, and is carried out in particular in an oxidizing atmosphere. With a diffusion time of 21 hours to drive the dopants deposited on the surface in the form of glass layers into the interior of the wafer
  • Phosphorus or Bordosen of about 1-2 x 10 to 17 centimeters high -2 in areas 10 and 11 reached. This is an order of magnitude higher dose than in otherwise typical semiconductor applications.
  • the applied glass layers 2, 3, 4 and 5 are removed again, for example by means of 50 percent hydrofluoric acid, and the result is the wafer 1 shown in FIG Area 11 on the back.
  • This wafer can now be used, for example, to produce high-blocking pn diodes (two-layer diodes) by applying metal contacts on both sides in further steps.
  • metal contacts for example, metal layers are sputtered on both sides of the wafer simultaneously, first a 70 nanometer thick chrome layer, followed by a 160 nanometer thick nickel vanadium layer and a 100 nanometer thick silver layer. Then the wafer is along
  • Dicing lines divided into individual diode chips the dicing lines possibly having been introduced into the wafer by sawing before the metal contacts have been applied.
  • the method according to the invention is not only suitable for two-layer diodes, but can also be used in a correspondingly modified form for the production of multilayer diodes, in particular thyristor diodes (four-layer diodes) and three-layer diodes (transistor diodes).
  • power semiconductors for example power diodes
  • Thyristors and bipolar transistors can also be produced using the method.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Formation Of Insulating Films (AREA)
  • Chemical Vapour Deposition (AREA)
  • Recrystallisation Techniques (AREA)
  • Thyristors (AREA)

Abstract

L'invention concerne un procédé de production de composants semi-conducteurs, selon lequel au moins une zone dopée est introduite dans une tranche. Une couche de verre solide (2; 4; 2, 3; 4, 5) dotée d'une matière de dopage est appliquée sur au moins sur une des deux faces d'une tranche semi-conducteur (1). Ensuite, la tranche est chauffée à des températures élevées de telle façon que la matière de dopage placée sur la couche de verre pénètre profondément dans la tranche pour produire la ou les zone(s) dopée(s) (10; 11). Enfin, la couche de verre est enlevée. Ce procédé sert à produire des zones hautement dopées homogènes. Ces zones peuvent être introduites dans la tranche des deux côtés et être de différents types de dopage.
EP00912386A 1999-02-26 2000-02-25 Procede de production de composants semi-conducteurs hautement dopes Ceased EP1157413A2 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE19908400 1999-02-26
DE19908400A DE19908400A1 (de) 1999-02-26 1999-02-26 Verfahren zur Herstellung hochdotierter Halbleiterbauelemente
PCT/DE2000/000546 WO2000052738A2 (fr) 1999-02-26 2000-02-25 Procede de production de composants semi-conducteurs hautement dopes

Publications (1)

Publication Number Publication Date
EP1157413A2 true EP1157413A2 (fr) 2001-11-28

Family

ID=7898991

Family Applications (1)

Application Number Title Priority Date Filing Date
EP00912386A Ceased EP1157413A2 (fr) 1999-02-26 2000-02-25 Procede de production de composants semi-conducteurs hautement dopes

Country Status (5)

Country Link
US (1) US6806173B1 (fr)
EP (1) EP1157413A2 (fr)
JP (1) JP2002538619A (fr)
DE (1) DE19908400A1 (fr)
WO (1) WO2000052738A2 (fr)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
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DE10058031B4 (de) * 2000-11-23 2007-11-22 Advanced Micro Devices, Inc., Sunnyvale Verfahren zur Bildung leicht dotierter Halogebiete und Erweiterungsgebiete in einem Halbleiterbauelement
US7208396B2 (en) * 2002-01-16 2007-04-24 Tegal Corporation Permanent adherence of the back end of a wafer to an electrical component or sub-assembly
US20080083611A1 (en) * 2006-10-06 2008-04-10 Tegal Corporation High-adhesive backside metallization
US7560355B2 (en) * 2006-10-24 2009-07-14 Vishay General Semiconductor Llc Semiconductor wafer suitable for forming a semiconductor junction diode device and method of forming same
US7999268B2 (en) * 2007-07-27 2011-08-16 Auburn University Low temperature impurity doping of silicon carbide
US8808513B2 (en) * 2008-03-25 2014-08-19 Oem Group, Inc Stress adjustment in reactive sputtering
US20090246385A1 (en) * 2008-03-25 2009-10-01 Tegal Corporation Control of crystal orientation and stress in sputter deposited thin films
US8058159B2 (en) * 2008-08-27 2011-11-15 General Electric Company Method of making low work function component
DE102008055515A1 (de) 2008-12-12 2010-07-15 Schott Solar Ag Verfahren zum Ausbilden eines Dotierstoffprofils
US8482375B2 (en) * 2009-05-24 2013-07-09 Oem Group, Inc. Sputter deposition of cermet resistor films with low temperature coefficient of resistance
DE102011000973A1 (de) * 2011-02-28 2012-08-30 Schott Solar Ag Verfahren zur flächigen Gasphasenbehandlng von Halbleiterbauelementen
DE102012204346A1 (de) * 2012-03-19 2013-09-19 Gebr. Schmid Gmbh Verfahren zur Herstellung eines beidseitig unterschiedlich dotierten Halbleiterwafers

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See also references of WO0052738A3 *

Also Published As

Publication number Publication date
WO2000052738A2 (fr) 2000-09-08
DE19908400A1 (de) 2000-09-07
US6806173B1 (en) 2004-10-19
JP2002538619A (ja) 2002-11-12
WO2000052738A3 (fr) 2000-12-21

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