EP1116270A1 - Ensemble circuit integre comportant des transistors verticaux, et son procede de production - Google Patents

Ensemble circuit integre comportant des transistors verticaux, et son procede de production

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Publication number
EP1116270A1
EP1116270A1 EP99955764A EP99955764A EP1116270A1 EP 1116270 A1 EP1116270 A1 EP 1116270A1 EP 99955764 A EP99955764 A EP 99955764A EP 99955764 A EP99955764 A EP 99955764A EP 1116270 A1 EP1116270 A1 EP 1116270A1
Authority
EP
European Patent Office
Prior art keywords
layer
trenches
layer sequence
produced
transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
EP99955764A
Other languages
German (de)
English (en)
Inventor
Wolfgang RÖSNER
Franz Hofmann
Emmerich Bertagnolli
Bernd Göbel
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Publication of EP1116270A1 publication Critical patent/EP1116270A1/fr
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B99/00—Subject matter not provided for in other groups of this subclass
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/05—Making the transistor
    • H10B12/053—Making the transistor the transistor being at least partially in a trench in the substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/34—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the transistor being at least partially in a trench in the substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B20/00—Read-only memory [ROM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B20/00—Read-only memory [ROM] devices
    • H10B20/27—ROM only
    • H10B20/40—ROM only having the source region and drain region on different levels, e.g. vertical channel

Definitions

  • the invention relates to an integrated circuit arrangement with at least one transistor and to a method for the production thereof.
  • An electronic circuit that is integrated in a substrate has a high packing density, because on the one hand its switching speed is high due to the short distances between its components and on the other hand its dimensions are small.
  • em upper source / drain region m an upper part of Siliziummsel and the lower source / drain region adjacent generated except ⁇ half and on the side of the Siliziummsel.
  • the channel region is arranged in the silicon cell below the upper source / drain region. The channel length is therefore determined by the etching depth when the silicon granules are produced.
  • German DR 195 19 160 C1 proposes a DRAM cell arrangement in which each memory cell comprises a projection-like semiconductor structure, the first source / drain region, the channel region arranged underneath and the second source / dram region arranged below comprises and which is surrounded by a gate electrode in a ring.
  • Semiconductor structures of memory cells are arranged in rows and columns. Self-aligned around word lines, i.e. Without using masks to be adjusted, distances between semiconductor structures arranged along the columns are smaller than distances between semiconductor structures arranged along the rows.
  • the word lines are formed by depositing and scratching back conductive material in the form of gate electrodes which are adjacent to one another along the columns.
  • an integrated circuit arrangement with at least one vertical MOS transistor for a substrate is provided adjacent to a surface on a top ⁇ of the substrate layer is doped by a first conductivity type.
  • a structured layer sequence with a lower layer, a middle layer doped by the first conductivity type and an upper layer is arranged on the substrate.
  • the layer sequence has at least a first lateral and a second lateral surface, which are each formed by the lower layer, the middle layer and the upper layer.
  • the lower layer can be used as a first source / drain region of the transistor, the middle layer as a channel region of the transistor and the upper layer as a second source / drain region of the transistor.
  • the problem is also solved by a method for producing an integrated circuit arrangement with at least one vertical MOS transistor, in which, in order to form a layer sequence on a substrate which is doped in a layer adjacent to a surface of the substrate of a first conductivity type, first a lower doped layer, which can be used as the first source / drain region of the transistor, above that a middle layer doped of the first conductivity type, which can be used as the channel region of the transistor, and above that a doped upper layer, which can be used as the second source / Drain area of the transistor can be used to be generated.
  • a connection structure doped with the first conductivity type is produced on a first surface of the layer sequence in such a way that it borders least to the middle layer and the lower layer at ⁇ and extends into the substrate.
  • the layer sequence is structured in such a way that a second surface of the layer sequence opposite the first surface is generated. At least on the second surface of the layer sequence, a gate dielectric and an adjacent gate electrode are produced.
  • connection structure enables charge to flow away from the channel area, so that, in contrast to the transistor according to Risch et al (see above), floating body effects are avoided.
  • the channel area does not become electrically charged even at high frequencies.
  • connection structure preferably consists of monocrystalline semiconductor material, such as e.g. Silicon and / or germanium.
  • the connection structure is e.g. generated by epitaxy in a trench that the
  • Layer sequence cuts or cuts It is advantageous to provide a low dopant concentration, for example up to 3 * 10 17 cm -3 , of the connection structure in order to keep capacities between the substrate and the gate electrode small.
  • connection structure polycrystalline semiconductor material such as polysilicon can be used for the connection structure.
  • the trench is filled with the semiconductor material.
  • the semiconductor material can be applied in a thickness that is not sufficient to fill the trench.
  • the semiconductor material can then be etched back are so that the connection structure is produced in the form of a spacer.
  • the connection structure comprises polycrystalline material or material with many defects, it is advantageous to provide a high dopant concentration of the connection structure, for example 5 * 10 8 cm -3 to 10 ⁇ 0 cm -3 , in order to expand space charge zones in the connection structure to decrease in.
  • connection structure To increase breakdown voltages between the connection structure and the source / drain regions and at the same time
  • connection structures To prevent reaching through space charge zones, it is within the scope of the invention to increase their dopant concentration during the production of the connection structures, so that inner parts of the connection structures are doped higher than outer parts.
  • a particularly high packing density of the circuit arrangement can be achieved if a width of the connection structure and / or a distance between the first surface and the second surface of the layer sequence, which is opposite the first surface, is smaller than the minimum one used in the manufacture of the circuit arrangement Structure size F that can be produced by photolithography.
  • connection structure is generated on the first surface of the layer sequence and the gate dielectric is generated on the second surface of the layer sequence, and thus the two surfaces are subjected to different process steps, it is advantageous if the layer sequence is generated in two different process steps.
  • a mask is applied to the surface which leaves at least one area of F-2 of the upper layer free. The mask is made by a
  • Spacer widens by depositing and etching back material. This will expose the exposed area to the top Layer reduced to sublithographic dimensions.
  • the exposed surface of the upper layer is exposed to a first etching process, with selective etching to the spacer and the mask.
  • the connection structure is then created.
  • the mask is removed selectively to the spacer.
  • the second surface of the layer sequence is generated by a second etching process, etching being selective to the spacer.
  • connection structure consists of the same semiconductor material as the upper layer, the middle layer or the lower layer, then an auxiliary structure is produced above the connection structure in order to protect the connection structure when the second surface of the layer sequence is generated. If an upper surface of the connection structure lies under an upper surface of the mask, the auxiliary structure can be produced by depositing material and planarizing it until the mask is exposed.
  • the layer sequence and the further layer sequence are preferably produced by structuring a single upper layer, middle layer and lower layer.
  • the layer sequences are generated, for example, by selective epitaxy within a suitable mask.
  • the designation "upper layer” is used for the continuous upper layer produced at the beginning of the production process, from which parts of the layer sequences are produced.
  • the analogous applies to the "middle layer” and the “lower layer” upper layer of the layer sequence "only a certain part of this layer sequence. If the layer sequences are generated from the upper layer, “the upper layer of the layer sequence” means the same as “the part of the upper layer belonging to the layer sequence”.
  • the upper layer of the layer sequence and an upper layer of the further layer sequence serve as the second source / drain region of the transistor
  • the middle layer of the layer sequence and the middle layer of the further layer sequence serve as the channel region of the transistor and the lower layer of the layer sequence and a lower one Layer of the further layer sequence as the first source / drain region of the transistor
  • the transistor has a particularly large channel width.
  • the gate electrode and the further gate electrode form a common gate electrode.
  • the upper layer, the middle layer and the lower layer can be structured in such a way that they surround the connection structure, so that the layer sequence and the further layer sequence merge into one another.
  • the layer sequence and the further layer sequence can alternatively be separated by the connection structure.
  • the mask leaves a square area, for example, so that a closed spacer is formed when the mask is widened and a correspondingly structured layer sequence can thus be generated.
  • the mask is strip-shaped, for example, so that two spacers separated from one another and thus two layer sequences separated from one another are produced.
  • Em doped by a second conductivity type opposite the first conductivity type opposite ⁇ area may be disposed over the interconnect structure to connect the top layer of the layer sequence and the upper layer of the further layer sequence electrically.
  • an upper part of the connection structure can be implanted, so that said upper part m is converted into the doped region.
  • the upper layer of the further layer sequence serves as a second source / dram region of a further transistor
  • the middle layer of the further layer sequence serves as an channel region of the further transistor
  • the lower layer of the further layer sequence serves as a first source / dram region of the further transistor Transistor
  • the packing density of the circuit arrangement is particularly high, since the connection structure acts on the one hand as a common connection structure of the two layer sequences and on the other hand separates the transistors from one another.
  • the doped region can also be provided here so that the two transistors are connected in series.
  • the circuit arrangement can be used, for example, as a memory cell arrangement.
  • the layer sequence and the further layer sequence form a pair, the second surface of the layer sequence lying opposite the first surface of the layer sequence and the first surface of the further layer sequence lying opposite the first surface of the layer sequence.
  • Several pairs that are analogous to the pair are arranged in an xy grid. At least one part of the pairs are separated from one another by first separating trenches which run essentially parallel to one another, so that one of the pairs and one of the first separating trenches are arranged alternately next to one another and the second areas of the layer sequences of the pairs adjoin the first separating trenches.
  • Word lines that run across the first separation trench are connected to the gate electrodes.
  • Lower bit lines are preferably parts of the lower ones Layer and run across the word lines.
  • the trenches in which the connecting structures belonging to the pairs are produced are produced in the form of strips.
  • the first dividing trenches run parallel to the trenches.
  • the lower layer is structured at least by the trenches, so that the lower bit lines adjoin the connection structures and run parallel to them.
  • first separating trenches are produced in such a way that they reach into the lower layer without cutting them through, one of the lower bit lines and one of the trenches are alternately arranged next to one another.
  • a circuit arrangement can be used, for example, as a ROM cell arrangement. Pairs which are arranged between two of the first separating trenches which are adjacent to one another merge into one another, so that the associated connection structures form a common connection structure which has cross sections parallel to the surface, which are strip-shaped and essentially parallel to the first Divide trench. The analog applies to the doped regions that form upper bit lines.
  • the gate electrodes are parts of the word lines which have strip-shaped cross sections parallel to the surface. Each pair is part of two m series connected transistors, which are each connected between one of the upper bit lines and one of the lower bit lines.
  • Memory cell includes a transistor.
  • the memory cell can be made with an area of 2F-2.
  • Information is stored in the form of dopant concentrations in the channel regions and thus in the form of threshold voltages of the transistors.
  • the associated word line is driven and measured as to whether or not current flows between the associated upper bit line and the associated lower bit line.
  • the dopant concentrations of the channel regions of the transistors can be set by masked oblique implantation. If the first separation trenches are produced in such a way that they cut through the lower layer, one of the lower bit lines is arranged between one of the trenches and one of the first separation trenches.
  • Such a circuit arrangement can be used, for example, as a DRAM cell arrangement.
  • connection structures of pairs which are arranged between two mutually adjacent first separation trenches form a common connection structure.
  • the connecting structure has a cross section parallel to the surface, which is strip-shaped and runs parallel to the first separating trench.
  • the pairs which are arranged between two of the first separation trenches which are adjacent to one another do not merge into one another, but are separated from one another by second separation trenches.
  • Separation trenches run across the first separation trench and extend into the lower layer.
  • the second separation trench does not cut through the lower layer so that the lower bit lines are not interrupted.
  • the connection structures are also not interrupted by the second dividing trench.
  • one of the pairs is part of one of the transistors.
  • the transistor is connected to two lower bit lines which adjoin the associated connection structure.
  • the two lower bit lines are e.g. m connected together in a periphery of the DRAM cell arrangement and act as a single bit line.
  • the upper layers and the doped regions act as first capacitor electrodes of capacitors.
  • a capacitor dielectric is placed over the upper layers and the doped regions, and a second capacitor electrode is used as a common capacitor. satorplatte all capacitors can be formed, arranged ⁇ .
  • the word lines of the DRAM cell arrangement are preferably configured differently, since they would otherwise run over the capacitors which are arranged over the upper layers.
  • the word lines are formed, for example, by the gate electrodes which laterally surround the pairs in an annular manner and adjoin one another within the first separating trench.
  • a memory cell of the DRAM cell arrangement comprises one of the transistors and one of the capacitors, which are connected to one another in a row.
  • the memory cell can be manufactured with an area of 4F2.
  • the information of a memory cell is stored in the form of a charge on the associated capacitor.
  • one of the pairs is part of two transistors.
  • the doped regions are not provided so that the transistors are separated from one another.
  • the lower bit lines act as individual bit lines.
  • a memory cell of such a DRAM cell arrangement can have an area of only 2F 2 .
  • a FRAM (ferroelectric RAM) cell arrangement is generated if the capacitor dielectric contains an ferroelectric material.
  • the mask for generating the layer sequences and the connection structures can comprise a first auxiliary layer and a second auxiliary layer arranged above it, the first auxiliary layer being selectively etchable to the spacer and the second auxiliary layer being selectively etchable to the semiconductor material.
  • the first auxiliary layer and the second auxiliary layer are structured in the form of strips, so that the upper layer is partially exposed.
  • the second auxiliary layer and the spacers act as a mask.
  • the second auxiliary layer and the spacers are removed until the first auxiliary layer is exposed.
  • the first auxiliary layer is then selectively removed from the spacers and the auxiliary structures, so that the spacers and the auxiliary structures can act as a mask when producing the first separating trench.
  • the word lines of the DRAM cell arrangement can be generated in a self-aligned manner, that is to say without using masks to be adjusted, if distances between pairs adjacent to one another transversely to the first separation trench are smaller than distances between pairs adjacent to one another parallel to the first separation trench.
  • material m of such a thickness can be deposited to produce the word lines that the first separating trenches but not the second separating trenches are filled. Scratching then creates the second separating trench spacer, while the bottom of the first
  • the trench remains covered by the material. Without masks, the gate electrodes are thus produced, which surround the pairs in a ring and adjoin one another within the first trench.
  • Auxiliary layer adjacent to the spacers are generated by depositing material and etching back.
  • ⁇ preferably consist de further spacer made of the same material as the spacer.
  • the first separating trenches are created, the spacers, the further spacers and the auxiliary structures acting as a mask.
  • the first separation trenches produced in this way are narrower than the first separation trenches of the ROM cell arrangement described above.
  • the second dividing trenches can be produced with a lithographically structured mask, so that their widths are significantly larger than the widths of the first dividing trenches and are, for example, F.
  • FIG. 1 shows a cross section through a first substrate after a lower layer, a middle layer, an upper layer, a protective layer, a first auxiliary layer, a second auxiliary layer, spacers and trenches have been produced.
  • FIG. 2 shows the cross section from FIG. 1 after connection structures, doped regions and auxiliary structures have been produced and the second auxiliary layer has been removed.
  • FIG. 3 shows the cross section from FIG. 2 after the first auxiliary layer, the protective layer, the spacers and the auxiliary structures have been removed and separating trenches and layer sequences of transistors have been produced.
  • FIG. 4a shows the cross section from FIG. 3 after a gate dielectric and word lines have been generated.
  • FIG. 4b shows a top view of the first substrate, in which the upper layer, the doped regions, the trenches and the word lines are shown.
  • FIG. 5 shows a cross section through a second substrate after a lower layer, a middle layer, an upper layer, spacers, connection structures, doped regions, auxiliary structures and further spacers have been produced.
  • Figure 6a shows the cross section of Figure 5 after the first
  • Isolation trench, second isolation trench and layer sequences of transistors were generated.
  • Figure ⁇ b shows a cross section perpendicular to the cross section from Figure 6a through the second substrate, after the process steps from Figure 6a.
  • FIG. 6c shows a top view of the second substrate, which shows the upper layer, the doped regions, the first separation trench and the second separation trench.
  • FIG. 7a shows the cross section from FIG. 6a after insulating structures, a gate dielectric, word lines, a capacitor dielectric and a capacitor electrode have been produced.
  • FIG. 7b shows the cross section from FIG. 6b after the process steps from FIG. 7a.
  • a 250 nm technology is used, that is to say the minimum photolithographically producible structure size F is 250 nm.
  • a first substrate 1 is provided as the starting material, which is p-doped in a layer adjacent to a surface of the first substrate 1 with a dopant concentration of approximately 10 * * - 7 cm -3 . Epitaxy doped in situ results in an approx.
  • n-doped lower layer U 500 nm thick n-doped lower layer U is generated.
  • the dopant concentration of the lower layer U is approximately 10 20 cm " 3rd
  • An approximately 200 nm thick p-doped middle layer M is generated by m situ doped epitaxy on the lower layer U.
  • the dopant concentration of the middle layer M is approx. 3 x 10 * 17 cm -3 .
  • an approximately 200 nm thick n-doped upper layer 0 is generated on the middle layer M by in situ doped epitaxy, the dopant concentration of which is approximately 10 * 21 cm - 3 (see FIG. 1).
  • S1O2 is deposited using a TEOS method with a thickness of approximately 50 nm.
  • a first auxiliary layer H1 is produced by depositing polysilicon with a thickness of approximately 200 nm.
  • a second auxiliary layer H2 is produced over the first auxiliary layer H1 by depositing S1O2 m with a thickness of approximately 100 nm (see FIG. 1).
  • the protective layer S, the first auxiliary layer H1 and the second auxiliary layer H2 are structured into a strip-like mask by means of a photolithographic process.
  • the strips of the mask are approximately 250 nm wide and are spaced approximately 250 nm apart.
  • CHF3 + O2 and C2F5 + O2, for example, are suitable as etchants for structuring.
  • S1O2 is deposited to a thickness of approximately 80 nm and etched back with CHF 3 + O2. As a result, the mask is widened by the spacer Sp (see FIG. 1).
  • silicon is etched selectively to S1O2 with, for example, HBr + NF3 + He + O2 to a depth of approximately 1.1 ⁇ m, so that trenches G parallel to the strips of the mask are produced (see FIG. 1) .
  • connection structures V are generated in the trench G by selective epitaxy with a doping substance concentration of 3 ⁇ 10 17 cm -3 , which electrically connect the middle layer M to the first substrate 1 (see FIG. 2).
  • a The upper surface of the connection structure V is approximately the same height as an upper surface of the upper layer 0.
  • the connection structures V have a width of approximately 90 nm. The width of the connection structures V is therefore sublithographic. Connection structures V which are adjacent to one another are at a distance of approximately 410 nm from one another.
  • V n-doped regions are generated in the upper parts of the connection structures, the dopant concentration of which is approximately 5 ⁇ 10 20 cm -3 (see FIG. 2).
  • S1O2 is deposited with a thickness of approx. 300 nm and chemically-mechanically polished.
  • the second auxiliary layer H2 is removed and part of the spacer Sp is removed.
  • Auxiliary structures H made of S1O2 are formed over the doped regions Ge (see FIG. 2).
  • the first auxiliary layer Hl is removed by selectively etching polysilicon to S1O2 with, for example, C2F5 + O2, so that the spacers Sp and the auxiliary structures H act as a mask.
  • S1O2 is then etched to a depth of approximately 50 nm with CHF3 + O2, so that the protective layer S is removed and the upper layer 0 is partially exposed.
  • separation trench T silicon is etched with HBr + NF3 + He + O2, for example, the auxiliary structures H and the spacers Sp acting as a mask.
  • the separating trenches T are approximately 600 nm deep and extend into the lower layer U without cutting them through (see FIG. 3).
  • Layer sequences SF, SF * arise from the upper layer 0, the middle layer M and the lower layer U, which adjoin the connection structures V with first areas and adjoin the separating trench T with second areas.
  • the distance between the first surface and the second surface of a layer sequence SF, SF * is approximately 80 nm and is therefore sublithographical.
  • the separating trenches T are self-aligned to the trenches G.
  • the spacers Sp and the auxiliary structures H are then selectively removed to silicon by etching SiO 2.
  • selected layer sequences SF * are implanted in such a way that the dopant concentration of the associated parts C of the middle layer M increases to approximately 10-1 c -3 (see FIG. 3).
  • n-doped polysilicon is deposited in situ to a thickness of approximately 200 nm and structured in a strip shape using a photolithographic method (see FIGS. 4a and 4b).
  • the word lines W run transversely to the trenches G. Parts of the word lines W located in the separating trenches T can be used as gate electrodes of vertical transistors. Cross sections through the word lines W parallel to the surface and above the upper layer 0 are strip-shaped.
  • the structured lower layer U acts as lower bit lines and as source / drain regions of the transistors.
  • the lower bit lines and the connection structures V are arranged alternately next to one another.
  • the middle layer M acts as channel regions of the transistors.
  • the upper layer 0 and the doped regions Ge act as further source / drain regions of the transistors and as upper bit lines, which are strip-shaped and run parallel to the lower bit lines.
  • Each layer sequence SF, SF * is part of one of the transistors.
  • the transistors are connected in series with one another in the word line direction.
  • the transistors are each connected between one of the upper bit lines and one of the lower bit lines.
  • the circuit arrangement generated is suitable as a ROM cell arrangement.
  • Egg- ne memory cell comprises one of the transistors.
  • the space requirement per memory cell is only 2F 2 .
  • the associated word line W is driven and checked whether a current flows or not between the upper bit line and the lower bit line between which the transistor is connected. If the part of the middle layer M, which belongs to the associated layer sequence SF *, was implanted obliquely, none flows due to the higher threshold voltage of this transistor
  • a second substrate 2 made of silicon is provided as the starting material and, analogously to the first exemplary embodiment, is p-doped in a layer adjacent to a surface.
  • a lower layer U ', a middle layer M', an upper layer 0 ', spacer Spl', connecting structures V, doped regions Ge 'and auxiliary structures H' are produced (see FIG. 5).
  • SiO 2 is deposited to a thickness of approximately 80 nm and etched back with CH 3 + O2 (see FIG. 5). This exposes an exposed area of the upper layer 0 '.
  • second separating trenches T2 are produced which extend to the lower layer U 'enough without cutting them.
  • the second dividing trenches T2 cross the first dividing trenches Tl and are approximately 600 nm deep outside the first dividing trenches Tl.
  • HBr + NF3 + He + O2 is suitable as an etchant (see FIGS. 6b and 6c).
  • Layer sequences SF ' which are adjacent to one another and are separated from one another by one of the connecting structures V are at a distance of approximately 90 nm, while mutually adjacent layer sequences SF' which are separated from one another by one of the second trenches T2 'are at a distance of approx Have 250 nm from each other.
  • second insulating structures 12 m in the second separation trench T2 SiO 2 is deposited to a thickness of approximately 300 nm and planarized by chemical mechanical polishing until the upper layer 0 'is exposed. S1O2 is then jerked back so that the upper surfaces of the first insulating structures II and the second insulating structures 12 are approximately 500 nm below the surface of the sub- strats 2 lie.
  • the first insulating structures II thus have a thickness of approximately 600 nm and the second insulating structures 12 have a thickness of approximately 100 nm.
  • This process step ensures that a lattice-shaped flat base of S1O2 is formed within the first separating trench T1 and the second separating trench T2. The formation of undesirable conductive spacers between adjacent word lines W 'is avoided by the flat floor.
  • a thermal dielectric approx. 5 nm thick gate dielectric Gd ' is produced (see FIGS. 7a and 7b).
  • n-doped polysilicon is deposited in situ to a thickness of approximately 80 nm and etched back to a depth of approximately 150 nm.
  • the word lines W ' are self-aligned in the form of mutually adjacent gate electrodes which surround pairs of layer sequences SF' in a ring.
  • Parts of the word lines W 'located in the second trench T2 are spacer-shaped (see FIG. 7b).
  • connection structures V Two mutually adjacent layer sequences SF ', which are separated from one another by one of the connection structures V, form a pair which is part of a transistor.
  • the parts of the lower layer U 'belonging to the pair can be used as the first source / dram region of the transistor.
  • the parts of the middle layer M 'belonging to the pair can be used as channel regions of the transistor.
  • the parts of the upper layer 0 'and the doped regions Ge' belonging to the pair are suitable as the second source / dram region of the transistor.
  • the connection structures V connect the channel regions of the transistors to the substrate 2, as a result of which floating body effects are prevented.
  • a third insulating structure 13 is then produced by depositing S1O2 m with a thickness of approximately 300 nm and planarizing it by chemical-mechanical polishing until the upper layer 0 'is exposed (see FIGS. 7a and 7b). Subsequently, barium strontium titanate is applied in a thickness of approx. 20 nm, whereby a capacitor dielectric Kd is formed. The second source / drain regions of the transistors simultaneously act as first capacitor electrodes of capacitors.
  • n-doped polysilicon is deposited in situ to a thickness of approximately 200 nm (see FIGS. 7a and 7b).
  • the circuit arrangement produced is a DRAM cell arrangement in which a memory cell comprises one of the transistors and one of the capacitors which are connected in series.
  • Transistors arranged between two mutually adjacent first separation trenches T1 have first source / drain regions which are interconnected and form bit lines.
  • the bit lines are divided into two, so that said transistors are connected to two separate bit lines, which, however, are interconnected in a periphery of the DRAM cell arrangement.
  • the memory cell has an area of 4F 2 .
  • the capacitor dielectric can also consist of another material or comprise several layers, for example in the form of an ONO layer sequence.
  • the doped regions can be omitted in the DRAM cell arrangement.
  • Each transistor comprises a layer sequence.
  • the bit lines are operated as individual bit lines and are not connected in pairs in the periphery. In this case, a memory cell has an area of only 2F 2 .

Abstract

Le transistor du circuit présenté est un transistor vertical MOS qui comprend une série de couches (SF, SF*) disposée sur un substrat (1) dopé d'un premier type de conductivité, et présentant une couche inférieure (U) servant à former une première zone de source/drain, une couche intermédiaire (M) dopée, du premier type de conductivité, destinée à former une zone de canal, et une couche supérieure (O), destinée à former une seconde zone de source/drain. Pour la connexion électrique de la zone de canal avec le substrat (1), une structure de connexion (V) dopée du premier type de conductivité est disposée sur au moins une première surface de la série de couches (SF, SF*). Une électrode de grille du transistor est disposée sur au moins une seconde surface de la série de couches (SF, SF*). La structure de connexion (V) peut être disposée entre la série de couches (SF, SF*) et une autre série de couches (SF, SF*) qui peut appartenir au même transistor ou à un autre transistor. Les dimensions de la structure de connexion (V) et de la série de couches (SF, SF*) peuvent être inférieures à celles obtenues avec un procédé lithographique. La production se fait de façon autoajustée. Cet ensemble circuit peut être utilisé en tant qu'ensemble cellule de mémoire à grande densité d'enregistrement.
EP99955764A 1998-09-25 1999-09-22 Ensemble circuit integre comportant des transistors verticaux, et son procede de production Pending EP1116270A1 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE19844083 1998-09-25
DE19844083 1998-09-25
PCT/DE1999/003031 WO2000019529A1 (fr) 1998-09-25 1999-09-22 Ensemble circuit integre comportant des transistors verticaux, et son procede de production

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EP1116270A1 true EP1116270A1 (fr) 2001-07-18

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US (1) US6750095B1 (fr)
EP (1) EP1116270A1 (fr)
JP (2) JP2002526928A (fr)
KR (1) KR100423765B1 (fr)
CN (1) CN1152425C (fr)
TW (1) TW437060B (fr)
WO (1) WO2000019529A1 (fr)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10030391C2 (de) * 2000-06-21 2003-10-02 Infineon Technologies Ag Verfahren zur Herstellung einer Anschlussfläche für vertikale sublithographische Halbleiterstrukturen
US6686604B2 (en) * 2001-09-21 2004-02-03 Agere Systems Inc. Multiple operating voltage vertical replacement-gate (VRG) transistor
KR20030060327A (ko) * 2002-01-08 2003-07-16 삼성전자주식회사 고집적 자성체 메모리 소자 및 그 구동 방법
DE10204871A1 (de) * 2002-02-06 2003-08-21 Infineon Technologies Ag Kondensatorlose 1-Transistor-DRAM-Zelle und Herstellungsverfahren
US6838723B2 (en) * 2002-08-29 2005-01-04 Micron Technology, Inc. Merged MOS-bipolar capacitor memory cell
US7224024B2 (en) 2002-08-29 2007-05-29 Micron Technology, Inc. Single transistor vertical memory gain cell
US6804142B2 (en) * 2002-11-12 2004-10-12 Micron Technology, Inc. 6F2 3-transistor DRAM gain cell
US6956256B2 (en) * 2003-03-04 2005-10-18 Micron Technology Inc. Vertical gain cell
KR100610496B1 (ko) * 2004-02-13 2006-08-09 삼성전자주식회사 채널용 핀 구조를 가지는 전계효과 트랜지스터 소자 및 그제조방법
US7145186B2 (en) * 2004-08-24 2006-12-05 Micron Technology, Inc. Memory cell with trenched gated thyristor
JP2007189008A (ja) * 2006-01-12 2007-07-26 Elpida Memory Inc 半導体記憶装置およびその製造方法
US7439135B2 (en) * 2006-04-04 2008-10-21 International Business Machines Corporation Self-aligned body contact for a semiconductor-on-insulator trench device and method of fabricating same
US8138538B2 (en) * 2008-10-10 2012-03-20 Qimonda Ag Interconnect structure for semiconductor devices
US20100090263A1 (en) 2008-10-10 2010-04-15 Qimonda Ag Memory devices including semiconductor pillars
JP4487221B1 (ja) * 2009-04-17 2010-06-23 日本ユニサンティスエレクトロニクス株式会社 半導体装置
US9184281B2 (en) * 2013-10-30 2015-11-10 Infineon Technologies Ag Method for manufacturing a vertical semiconductor device and vertical semiconductor device
US9397094B2 (en) 2014-09-25 2016-07-19 International Business Machines Corporation Semiconductor structure with an L-shaped bottom plate

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0793365B2 (ja) 1984-09-11 1995-10-09 株式会社東芝 半導体記憶装置およびその製造方法
US4914739A (en) * 1984-10-31 1990-04-03 Texas Instruments, Incorporated Structure for contacting devices in three dimensional circuitry
US4939104A (en) * 1984-10-31 1990-07-03 Texas Instruments, Incorporated Method for forming a buried lateral contact
US4791463A (en) * 1984-10-31 1988-12-13 Texas Instruments Incorporated Structure for contacting devices in three dimensional circuitry
JPH01125858A (ja) * 1987-11-10 1989-05-18 Fujitsu Ltd 半導体装置およびその製造方法
JP2606857B2 (ja) * 1987-12-10 1997-05-07 株式会社日立製作所 半導体記憶装置の製造方法
JPH01227468A (ja) * 1988-03-08 1989-09-11 Oki Electric Ind Co Ltd 半導体記憶装置
US5316962A (en) * 1989-08-15 1994-05-31 Matsushita Electric Industrial Co., Ltd. Method of producing a semiconductor device having trench capacitors and vertical switching transistors
US5181089A (en) * 1989-08-15 1993-01-19 Matsushita Electric Industrial Co., Ltd. Semiconductor memory device and a method for producing the same
US5010386A (en) * 1989-12-26 1991-04-23 Texas Instruments Incorporated Insulator separated vertical CMOS
JPH0425171A (ja) * 1990-05-21 1992-01-28 Matsushita Electric Ind Co Ltd 半導体メモリ装置
DE4341667C1 (de) * 1993-12-07 1994-12-01 Siemens Ag Integrierte Schaltungsanordnung mit mindestens einem CMOS-NAND-Gatter und Verfahren zu deren Herstellung
JP3745392B2 (ja) 1994-05-26 2006-02-15 株式会社ルネサステクノロジ 半導体装置
DE19519160C1 (de) * 1995-05-24 1996-09-12 Siemens Ag DRAM-Zellenanordnung und Verfahren zu deren Herstellung
DE19617646C2 (de) * 1996-05-02 1998-07-09 Siemens Ag Speicherzellenanordnung und ein Verfahren zu deren Herstellung
EP0899790A3 (fr) * 1997-08-27 2006-02-08 Infineon Technologies AG Réseau de cellules DRAM et procédé de fabrication

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO0019529A1 *

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KR100423765B1 (ko) 2004-03-22
KR20010075236A (ko) 2001-08-09
US6750095B1 (en) 2004-06-15
TW437060B (en) 2001-05-28
WO2000019529A1 (fr) 2000-04-06
JP4149498B2 (ja) 2008-09-10
JP2002526928A (ja) 2002-08-20
CN1152425C (zh) 2004-06-02
CN1312955A (zh) 2001-09-12
JP2007329489A (ja) 2007-12-20

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