WO2001001489A1 - Dispositif d'elements dram et son procede de fabrication - Google Patents

Dispositif d'elements dram et son procede de fabrication Download PDF

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Publication number
WO2001001489A1
WO2001001489A1 PCT/DE2000/001156 DE0001156W WO0101489A1 WO 2001001489 A1 WO2001001489 A1 WO 2001001489A1 DE 0001156 W DE0001156 W DE 0001156W WO 0101489 A1 WO0101489 A1 WO 0101489A1
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WO
WIPO (PCT)
Prior art keywords
trenches
word line
trench
substrate
source
Prior art date
Application number
PCT/DE2000/001156
Other languages
German (de)
English (en)
Inventor
Till Schlösser
Franz Hofmann
Original Assignee
Infineon Technologies Ag
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies Ag filed Critical Infineon Technologies Ag
Publication of WO2001001489A1 publication Critical patent/WO2001001489A1/fr

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/34—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the transistor being at least partially in a trench in the substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/05—Making the transistor
    • H10B12/053—Making the transistor the transistor being at least partially in a trench in the substrate

Definitions

  • the invention relates to a DRAM cell arrangement, i. H. a memory cell array with dynamic random access.
  • Em transistor memory cell which comprises a transistor and a capacitor, is almost exclusively used as the memory cell of a DRAM cell arrangement.
  • the information of the memory cell is stored in the form of a charge on the capacitor.
  • the capacitor is connected to the transistor, so that when the transistor is driven via a local line, the charge of the capacitor can be read out via a bit line.
  • the general aim is to produce a DRAM cell arrangement that has a high packing density.
  • Such a DRAM cell arrangement is described, for example, in M. Aoki et al., "Fully Self-Aligned 6F 2 Cell Technology for Low Cost 1 Gb DRAM", Symposium on VLSI Technology Digest of Technical Papers (1996), 22.
  • Thermal oxidation produces stripe-shaped insulating structures in a substrate that define active areas of transistors.
  • a surface of the substrate is covered with a gate dielectric.
  • Word lines are then produced which run transversely to the insulating structures and are covered with silicon nitride.
  • Source / drain regions of the transistors are produced between the word lines and the insulating structures.
  • a first insulating layer is deposited in which contact holes are produced which sometimes extend to one of the source / drain regions.
  • msitu doped polysilicon is deposited to such a thickness that the contact holes are not filled.
  • a second insulating layer is deposited that fills the contact holes. Every third along an isolating S corture adjacent contact hole is opened again and filled with further situ doped polysilicon, are generated so that Kon ⁇ contacts.
  • the second insulating layer, parts of the polysilicon, which are arranged over the word lines, and the first insulating layer are removed.
  • Ov ⁇ rig Economicsendes polysilicon in the contact hole punches, m which no contacts were generated form first capacitor electrodes of the capacitors of the memory cells.
  • a capacitor dielectric and second capacitor electrodes arranged above it are generated and by a third insulating one
  • the third insulating layer creates depressions that expose the contacts. Then bit lines are generated which adjoin the contacts. Every third word line, which is arranged between two source / dra regions, which are "each connected to a capacitor, is connected to a potential such that no current can flow between these source / dram regions. These word lines act as isolations ,
  • German patent DE 44 08 764 C2 describes a DRAM cell arrangement in which first trenches, which run essentially parallel to one another, and second trenches running transversely thereto are provided in a substrate.
  • a word line which is separated from the substrate by a gate dielectric, is sometimes arranged in the lower parts of the second trench.
  • the first trenches outside the word lines are filled with insulating material.
  • source / dram regions of transistors are arranged in the substrate, which adjoin a surface of the substrate.
  • the source / dram regions have the shape of an upturned U and adjoin the flanks of the second trench up to the lower regions of the second trench.
  • Every third of the source / dram regions that are adjacent to one another along a first trench is connected to a bit line that runs parallel to the first trench.
  • the remaining source / dram areas are covered with a capacitor dielectric over which a thin conductive one Layer, the upper areas of the word line trenches ⁇ and serves as a capacitor plate, arranged.
  • the capacitor dielectric is likewise arranged in the upper regions of the word line trench and separates the source / dram regions which are not connected to the bit lines and act as capacitor electrodes from the capacitor plate.
  • Those word lines that are between two of the source / dram regions, which act as capacitor electrodes are connected to a fixed potential, so that no current flows between these source / dram regions. These word lines therefore serve to isolate adjacent memory cells.
  • the invention is based on the problem of specifying a DRAM cell arrangement which, compared to the prior art, has improved electrical properties with a high packing density at the same time.
  • a method for producing such a DRAM cell arrangement is also to be specified.
  • first trenches which run essentially parallel to one another
  • second trenches which run transverse to the first trenches and essentially parallel to one another
  • the second trenches are subdivided into m word line trenches which are provided with a gate dielectric and m each of which a word line is arranged, and isolation trenches which are filled with insulating material.
  • Insulating protective structures are arranged above the word lines in the word line trenches which, together with the word lines, fill the word line trenches.
  • One of the word line trenches is adjacent to another of the word line trenches and to one of the isolation trenches.
  • One of the isolation trenches is adjacent to two of the word line trenches.
  • the first trenches are filled with insulating material outside the word line trenches.
  • First source / dram regions of transistors are arranged in the substrate, d ie to a surface of the substrate adjacent a sentlichen in we ⁇ homogeneous vertical thickness, ie, a thickness perpendicular ⁇ right to the surface of the substrate, comprise less deep m the substrate extend as the word lines are connected to lines with bit, and in each case tung dig two of the wordline ⁇ and adjacent to two of the first trench.
  • sub dram regions are ⁇ strat second source / of the transistors being ⁇ arranged adjacent to the surface of the substrate have a substantially homogeneous vertical thickness less deep m the substrate extend as the word lines are connected to capacitors, and each of one of the word line trenches, adjoin one of the isolation trenches and two of the first trenches.
  • bit lines run across the word lines.
  • first trenches which run essentially parallel to one another and second trenches which run transversely to the first trenches and essentially parallel to one another are produced in a substrate become.
  • Some of the second trenches, which are referred to as word line trenches, are provided with a gate dielectric and the remaining of the second trenches, which are referred to as isolation trenches, are filled with insulating material, one of the word line trenches being connected to another of the word line trenches and to one of the Isolation trench is adjacent, and one of the isolation trench is adjacent to two of the word line trenches.
  • a word line and an insulating protective structure arranged above it are generated in the word line trenches, which together fill the corresponding word line trench.
  • the first trenches are filled with insulating material outside the word line trenches.
  • the first source / dram regions of transistors are produced in the substrate in such a way that they adjoin a surface of the substrate, have an essentially homogeneous vertical thickness, and extend less deep into the substrate tung dig as d ie word line trenches and in each case two of the wordline ⁇ and adjacent to two of the first trench. There he joined generated ⁇ the bit lines and ebieten to the first source / dram G.
  • the substrate dram regions of the transistors are second source / generated so that they at the SURFACE ⁇ surface of the substrate adjacent which have a substantially homogeneous vertical thickness less deeply extend into the substrate than the word line trenches and in each case to one of the word line trenches to one of the isolation trenches and adjoin two of the first trenches.
  • Capacitors are generated and connected to the second source / dram regions.
  • a memory cell of the DRAM cell arrangement comprises one of the transistors and an associated capacitor.
  • the isolation trenches separate adjacent memory cells from one another along a first trench.
  • the first trenches separate adjacent memory cells from one another along a word line trench.
  • the vertical thickness of one of the source / dram regions can vary slightly locally. Such fluctuations are e.g. to be attributed to the not exactly defined implantation depth during the generation of the source / dram region or to statistical deviations during the diffusion of the dopant of the source / dram region.
  • Channel areas of the transistors are U-shaped. Despite the high packing density of the DRAM cell arrangement, i.e. small space requirement per memory cell, the channel length of the transistors can be increased via the depth of the word line trench, and short channel effects can thereby be avoided.
  • the DRAM cell arrangement can be produced with a high packing density because, on the one hand, the source / dram regions of the
  • Transistors can be produced in a self-aligned manner with respect to the word line trench and the first trench, and contacts between the source / dram regions and the bit lines or the capacitors can be produced with a high adjustment tolerance.
  • an intermediate oxide can be deposited on the surface of the substrate by opening the contact hole to the source / dram regions.
  • the adjustment tolerance of the contact holes is large because the
  • Protective structures cover the word lines, and the intermediate oxide can be selectively etched to the protective structures. Short circuits between the word lines and the contacts that are generated in the contact holes are thereby avoided.
  • the second source / dram areas can also act as capacitor electrodes of the capacitors.
  • bit lines in such a way that they adjoin the first source / dram region, so that corresponding contacts can be dispensed with.
  • a trench is etched in the intermediate oxide for each bit line and filled with conductive material.
  • a particularly high packing density is achieved if the widths of the first trenches, the distances of the first trenches from one another, the widths of the second trenches and the distances of the second trenches from one another have the same value and are preferably equal to the minimum structural size F which can be produced using the technology used.
  • the capacitors can then be produced with a larger capacitance. For example, its horizontal cross section can be enlarged in this case.
  • a depression can also be produced in the substrate, which cuts through the second source / dram region and in which the capacitor can be arranged.
  • bit line can then be arranged in a further trench which cuts through the first source / dram region.
  • the isolation trenches and the word line trenches can be filled as follows: First, the second trenches are filled with insulating material. A strip-shaped mask is then produced, the strip of which covers every third of the second trenches, namely the isolation trenches. Using the mask, exposed insulating material is removed from the uncovered second trench, namely the word line trench. The gate dielectrics and the word lines are then produced in the second trench, from which the insulating material has been removed.
  • the auxiliary layer is then applied and structured in the form of a strip. Between the stripes of the structured Auxiliary layer, which acts as a mask, the second digger is created.
  • the auxiliary layer additionally serves to strip-shaped mask as a mask during the removal of iso ⁇ lierenden material from the word line trench is removed.
  • the auxiliary layer prevents the insulating material from remaining outside the word line trenches in the first trench. Since the first trenches are created first, they can be deeper than the second trenches, so that leakage currents between source / dram regions adjacent to one another along the word line can be prevented. In this case, the insulating material on the bottom of parts of the first trenches where the first trenches and the word line trenches cross is not removed.
  • the second trenches are first created.
  • the substrate consists of semiconductor material, e.g. Silicon.
  • the word lines can be made of doped polysilicon or of another conductive material, such as. B. metal or metal silicide.
  • the intermediate oxide consists of Si02, it is advantageous for selective etchability if the protective structures consist of silicon nitride.
  • FIG. 1 shows a plan view of a substrate after the first trenches have been produced.
  • FIG. 2 shows a cross section through the substrate after an auxiliary layer, second trench and a mask have been produced.
  • FIG. 3a shows the cross section from FIG. 2, after gate dielectric, word lines, protective structures, source / dram regions of transistors, an intermediate oxide,
  • FIG. 3b shows the top view of FIG. 1 after the process steps from FIG. 3a, with the contacts that
  • Word lines, the first trench and the second trench are shown.
  • the starting material is a substrate 1, which contains p-doped silicon.
  • a first mask made of photoresist (not shown)
  • approximately 400 nm deep first trenches G1 are produced in the substrate 1.
  • the first trenches Gl are approximately 150 nm wide and are spaced approximately 150 nm apart.
  • the first trenches G1 are filled with insulating material by depositing S1O2 in a thickness of approximately 90 nm and planarizing by chemical mechanical polishing until the substrate 1 is exposed (see FIG. 1).
  • silicon nitride is deposited to a thickness of approximately 50 nm (see FIG. 2).
  • the second trenches G2 are approximately 150 nm wide and are spaced approximately 150 nm apart.
  • the second trenches G2 are filled with insulating material by depositing S1O2 in a thickness of approximately 90 nm and chemical-mechanically polishing until the auxiliary layer H is exposed.
  • the strips of which run parallel to the second trench G2 are approximately 300 nm wide and covers every third of the second trench G2, S1O2 is selectively etched to silicon nitride.
  • the insulating material is retained in the second trench G2, which are covered by the third photoresist mask P.
  • These second trenches G2 are referred to below as isolation trenches.
  • the insulating material is removed from the remaining second trenches G2, which are referred to below as word line trenches, until the bottom of the word line trenches are exposed (see FIG. 2).
  • the third photoresist mask P is removed.
  • word lines W m the word line trench, polysilicon is deposited in a thickness of approximately 30 nm and above it WSi m in a thickness of approximately 60 nm and planarized by chemical-mechanical polishing until the auxiliary layer H is exposed. Then WSi and polysilicon are etched back until an upper surface of the word lines W is approximately 50 nm below a surface F of the substrate 1 (see FIG. 3a).
  • the auxiliary layer H is z. B. hot H3PO4 removed. Subsequently, silicon nitride is deposited in a thickness of approx. 70 nm and planed by chemical-mechanical polishing until the surface F of the substrate 1 is exposed. As a result, the word lines W become insulating
  • Protective structures S are generated which, together with the word lines W, fill the word line trenches (see FIG. 3a).
  • first source / dram regions S / D1 and second source / dram regions S / D2 of transistors are produced between the first trench G1 and the second trench G2.
  • the source / dram areas S / Dl, S / D2 are approximately 80 nm deep and have an essentially homogeneous vertical, ie. H. thickness running perpendicular to the surface F of the substrate 1.
  • the source / dram regions S / Dl, S / D2 extend less deep into the substrate 1 than the word line trenches and thus as the word lines W, so that when the transistors are driven, a channel is produced which runs in a U-shape.
  • a current consequently flows both on the flanks and on the bottom of the word line trenches.
  • Two transistors are surrounded by two mutually adjacent first trenches Gl and two mutually adjacent isolation trenches.
  • the first source / dram regions S / DL are each arranged between two word line trenches and each act as a common source / dram region of two of the transistors.
  • S1O2 is deposited with a thickness of approx. 1000 nm (see FIG. 3a).
  • contact holes are produced which each expose one of the source / dram regions S / Dl, S / D2 of the transistors (see FIGS. 3a and 3b).
  • the intermediate oxide Z is selectively etched to the protective structures S.
  • Contacts KB to bit lines B are produced in the contact holes which expose the first source / dram regions S / DL (see FIGS. 3a and 3b).
  • Contacts KS to capacitors Ko are produced in the contact holes which expose the second source / dram regions S / D2 (see FIGS. 3a and 3b).
  • capacitors Ko shown schematically in FIG. 3a
  • bit lines B which run transverse to the word lines W

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)

Abstract

Un substrat (1) comprend des premières tranchées et, perpendiculairement à celles-ci, des deuxièmes tranchées (G2) qui se divisent en tranchées de conducteurs-mots et en tranchées d'isolation. Les tranchées de conducteurs-mots sont remplies chacune d'un conducteur-mots (W) et d'une structure de protection (S) agencée sur celui-ci. Les domaines source/drain (S/D1, S/D2) des transistors sont adjacents à une surface (F) du substrat (1) et pénètrent moins profondément dans le substrat (1) que les conducteurs-mots (W). Deux transistors adjacents se partagent un domaine commun source/drain (S/D1) qui est connecté à un conducteur de bits (B). Les autres domaines source/drain (S/D2) des transistors sont connectés à des condensateurs (Ko).
PCT/DE2000/001156 1999-06-23 2000-04-13 Dispositif d'elements dram et son procede de fabrication WO2001001489A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE19928781.3 1999-06-23
DE19928781A DE19928781C1 (de) 1999-06-23 1999-06-23 DRAM-Zellenanordnung und Verfahren zu deren Herstellung

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US7034408B1 (en) 2004-12-07 2006-04-25 Infineon Technologies, Ag Memory device and method of manufacturing a memory device
US7098105B2 (en) 2004-05-26 2006-08-29 Micron Technology, Inc. Methods for forming semiconductor structures
US7139184B2 (en) 2004-12-07 2006-11-21 Infineon Technologies Ag Memory cell array
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US7476920B2 (en) 2004-12-15 2009-01-13 Infineon Technologies Ag 6F2 access transistor arrangement and semiconductor memory device
US7696567B2 (en) 2005-08-31 2010-04-13 Micron Technology, Inc Semiconductor memory device
US7732343B2 (en) 2006-04-07 2010-06-08 Micron Technology, Inc. Simplified pitch doubling process flow
US7736980B2 (en) 2006-03-02 2010-06-15 Micron Technology, Inc. Vertical gated access transistor
US7759704B2 (en) 2008-10-16 2010-07-20 Qimonda Ag Memory cell array comprising wiggled bit lines
US7768051B2 (en) 2005-07-25 2010-08-03 Micron Technology, Inc. DRAM including a vertical surround gate transistor
US7842558B2 (en) 2006-03-02 2010-11-30 Micron Technology, Inc. Masking process for simultaneously patterning separate regions
US7851356B2 (en) 2007-09-28 2010-12-14 Qimonda Ag Integrated circuit and methods of manufacturing the same
US7888721B2 (en) 2005-07-06 2011-02-15 Micron Technology, Inc. Surround gate access transistors with grown ultra-thin bodies
US7902598B2 (en) 2005-06-24 2011-03-08 Micron Technology, Inc. Two-sided surround access transistor for a 4.5F2 DRAM cell
US7956387B2 (en) 2006-09-08 2011-06-07 Qimonda Ag Transistor and memory cell array
US8101497B2 (en) 2008-09-11 2012-01-24 Micron Technology, Inc. Self-aligned trench formation
US8294188B2 (en) 2008-10-16 2012-10-23 Qimonda Ag 4 F2 memory cell array
US10515801B2 (en) 2007-06-04 2019-12-24 Micron Technology, Inc. Pitch multiplication using self-assembling materials
US10815367B2 (en) 2013-12-18 2020-10-27 Ineos Styrolution Group Gmbh Moulding compositions based on vinylaromatic copolymers for 3D printing

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US7139184B2 (en) 2004-12-07 2006-11-21 Infineon Technologies Ag Memory cell array
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US7476920B2 (en) 2004-12-15 2009-01-13 Infineon Technologies Ag 6F2 access transistor arrangement and semiconductor memory device
US8933508B2 (en) 2005-06-24 2015-01-13 Micron Technology, Inc. Memory with isolation structure
US7902598B2 (en) 2005-06-24 2011-03-08 Micron Technology, Inc. Two-sided surround access transistor for a 4.5F2 DRAM cell
US8836023B2 (en) 2005-06-24 2014-09-16 Micron Technology, Inc. Memory device with recessed construction between memory constructions
US8115243B2 (en) 2005-07-06 2012-02-14 Micron Technology, Inc. Surround gate access transistors with grown ultra-thin bodies
US7888721B2 (en) 2005-07-06 2011-02-15 Micron Technology, Inc. Surround gate access transistors with grown ultra-thin bodies
US7768051B2 (en) 2005-07-25 2010-08-03 Micron Technology, Inc. DRAM including a vertical surround gate transistor
US8481385B2 (en) 2005-08-31 2013-07-09 Micron Technology, Inc. Methods of fabricating a memory device
US8222105B2 (en) 2005-08-31 2012-07-17 Micron Technology, Inc. Methods of fabricating a memory device
US8546215B2 (en) 2005-08-31 2013-10-01 Micron Technology, Inc. Methods of fabricating a memory device
US7696567B2 (en) 2005-08-31 2010-04-13 Micron Technology, Inc Semiconductor memory device
US8039348B2 (en) 2006-03-02 2011-10-18 Micron Technology, Inc. Vertical gated access transistor
US8772840B2 (en) 2006-03-02 2014-07-08 Micron Technology, Inc. Memory device comprising an array portion and a logic portion
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US7736980B2 (en) 2006-03-02 2010-06-15 Micron Technology, Inc. Vertical gated access transistor
US9184161B2 (en) 2006-03-02 2015-11-10 Micron Technology, Inc. Vertical gated access transistor
US8592898B2 (en) 2006-03-02 2013-11-26 Micron Technology, Inc. Vertical gated access transistor
US7842558B2 (en) 2006-03-02 2010-11-30 Micron Technology, Inc. Masking process for simultaneously patterning separate regions
US8030217B2 (en) 2006-04-07 2011-10-04 Micron Technology, Inc. Simplified pitch doubling process flow
US7732343B2 (en) 2006-04-07 2010-06-08 Micron Technology, Inc. Simplified pitch doubling process flow
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