Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
  • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
  • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
  • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
  • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
  • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
  • H01L27/1259—Multistep manufacturing methods
  • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
  • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
  • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
  • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs

Definitions

• the invention relates to a method for producing MOS transistors, to a device comprising MOS transistors obtained by such a method and to a device for addressing and controlling an active matrix produced with such devices.
• the invention relates in particular to a device for addressing and controlling a flat screen with liquid crystal and active matrix.
• the invention relates in particular to the field of large area electronics. It is involved in the production of electronic circuits with complementary CMOS transistors in polycrystalline silicon; these transistors may include a lightly doped area at the edge of the gate.
• the invention applies to low temperature processes (Tmax ⁇ 450 ° C) compatible with non-refractory and non-crystalline substrates.
• the liquid crystal and active matrix flat screens are, according to known techniques, produced on a glass plate.
• the addressing of liquid crystal and active matrix flat screens is currently achieved by integrating thin film transistors on the glass plate; transistors designated by the abbreviation TFT which corresponds to the Anglo-Saxon expression Thin Film Transistor.
• TFT thin film transistors
• These TFT transistors are made from aSi-H hydrogenated amorphous silicon.
• This type of TFT transistor has low electronic mobility, of the order of 0.5 cm 2 V "1 s " 1 .
• the technology implemented for their realization does not allow to obtain a complementary logic. These constraints limit the use of such technology to the production of the transistors necessary for addressing the pixels of the screen.
• Screen management includes selecting rows, formatting and presenting video data on the different columns.
• the creation of a device for managing the screen requires the use of another technology; for example a technique for bringing silicon integrated circuits to the periphery of the glass slab.
• a technique for bringing silicon integrated circuits to the periphery of the glass slab To overcome the drawbacks of technologies using amorphous silicon, an evolution of technologies is made towards polycrystalline silicon in thin layer.
• the benefits of using silicon polycrystalline thin film lies in the possibilities offered by this material to produce good quality electronic circuits on non-refractory and non-crystalline substrates.
• the main known applications are in the field of addressing liquid crystal and active matrix flat screens.
• Polycrystalline silicon allows the production at low temperature of N-type TFT and P-type TFT exhibiting greater mobilities respectively of the order of 100 and 50 cm 2 V “1 s " 1 .
• Polycrystalline silicon therefore makes it possible to produce performance CMOS circuits compatible with the addressing of flat screens.
• the integration of all or part of the peripheral addressing electronics results in a relative reduction in the cost of the screen linked to the disappearance of the integrated circuits.
• the manufacturing yield is directly related to the number of masks used for the realization of the electronic circuits.
• CMOS circuits on insulating substrates for example of the SOI type, abbreviation of the English terms Silicon On Insulator
• SOI type abbreviation of the English terms Silicon On Insulator
• the object of the invention is to reduce the number of masks necessary for the production of circuits in CMOS technology compared to known methods.
• the subject of the invention is a method for producing transistors of a first and a second type in CMOS technology in an active layer, characterized in that it consists:
• each transistor controls the transistor allowing control of the channel of this transistor.
• the method according to the invention has the advantage of reducing the number of masks and the number of implantation steps.
• the gates of the NMOS and PMOS transistors are etched simultaneously.
• the N + and P + contact zones are obtained by ion implantation. They are self-aligned with respect to the edges of the grid; the grid playing the role of mask.
• This situation leads to intense electric fields in the channel at the edge of the gate.
• the intense electric fields induce either an instability of the characteristics when the grid polarization is positive, or large leakage currents when the grid polarization is negative.
• the instability of the characteristics is linked to the generation of hot electrons in the channel and to the creation of interface defects when these hot carriers interact with the hydrogen atoms making the defects of the Si0 2 / Si interface passive.
• Leakage currents originate from the intense electric field of the reverse-polarized drain-channel junction. The level of the leakage currents then depends exponentially on the drain-source and gate-source voltages.
• LDD area abbreviation of the Anglo-Saxon terms Lightly Doped Drain.
• the LDD zone is of the N- type for a N-type transistor.
• the extension of the LDD zone is of the order of 10% of the length of the channel, or approximately 0.1 ⁇ m for monocrystalline silicon technologies and approximately 0.5 ⁇ m for polycrystalline silicon technologies.
• the LDD area is obtained by producing a dielectric space at the edge of the grid or "spacer" according to English terminology. Dielectric space is obtained by conformal deposition and anisotropic etching of a dielectric film. This technology is not directly applicable on large surface substrates.
• the production of the LDD zone requires a particular mask and a particular implantation step. This brings the number of masks required to seven and the number of implantation steps to three.
• the invention reduces the number of masks required to five and the number of implantation steps to two.
• the invention allows self-alignment of the LDD area and allows control of the dopant dose independently of the extension of the LDD area.
• the LDD area is obtained by a low dose self-aligned implantation on the grid.
• the LDD region is then protected by the resin during the implantation dose dopant; N + type for an N type transistor, for example phosphorus.
• N + type for an N type transistor for example phosphorus.
• the subject of the invention is also a device for addressing and controlling a flat screen with liquid crystal and active matrix produced with CMOS transistors obtained by a method according to the invention.
• the addressing and control device includes an addressing device and a control device.
• the addressing device is a CMOS complementary transistor device.
• the control device is a device which does not require additional transistors. It is preferably made with N type transistors. When these transistors are equipped with an LDD zone, according to a particular embodiment of the invention, they have the advantage of having a very reduced leakage current. . This characteristic is particularly important for screens with active matrix of large dimensions. Each pixel of the screen is controlled by the gate of a transistor. Between two refreshes of a row in the matrix, the state of a pixel is maintained thanks to the memory function performed by the association of the capacity of the pixel and of the transistor in the off state; provided, however, that the drain-source leakage current does not have time to have a noticeable effect on the capacity charge. Thus, the drain-source leakage current of the control transistors has an immediate effect on the quality of the image. In particular, the lower the drain-source leakage current, the more it allows a large number of gray levels to be obtained.
• FIG. 5a respectively 5b, a schematic top view of a gate of a transistor of a first type, respectively of a gate of a transistor of a second type.
• FIG. 1 illustrates the different stages of carrying out the method according to the invention.
• the method applies to a substrate on which a thin active layer has been deposited.
• the process takes place in several stages.
• the method consists in defining 1 of the active islands. Definition 1 of the active islands is carried out either by engraving zones of the active layer, or by rendering zones of the active layer inactive.
• the active islands are intended to produce the sources, the channels and the drains of the transistors of the first type, respectively of the second type.
• the process consists of depositing two two layers.
• a first insulating layer covers at least the active islands.
• a second conductive layer covers the first layer.
• the second conductive layer is intended to produce the control grid for the transistors.
• the process consists in etching 3 sequentially all of the gates of the transistors of the first type and all of the gates of the transistors of the second type.
• the etching of all of the gates of the transistors of a given type is carried out by means of a particular mask.
• the mask reproduces the grids of the transistors of the given type and masks the implantation areas of the transistors of the other type. With the same mask it is thus possible to carry out doping operations for a given type of transistors.
• FIGS. 2a, 2b and 2c illustrate the steps of defining 1 of active islands and of depositing 2 of the first and second layers for a transistor of a first type or of a second type.
• the first type corresponds to type N and the second type to type P.
• This choice corresponds to a first mode of implementation of the method.
• the transistors N and the transistors P are produced, by the first mode of implementation of the method according to the invention, on the same substrate.
• the substrate 4 preferably consists of glass on which is deposited a preparation layer 5 intended to obtain a surface condition favorable to subsequent treatments. According to the state of the art, this preparation layer can be silica Si0 2 .
• An active layer 6 is deposited on the preparation layer 5.
• the active layer 6 is composed for example of polycrystalline silicon.
• a protective resin layer 7 is deposited on the active layer 6.
• a first mask reproduces the active islands to be kept in the active layer 6; active islands which allow the sources, channels and drains of the transistors to be produced subsequently.
• the active islands are produced by known techniques, for example by etching. According to the illustration in FIG. 2b, the active islands 6 are produced by removing material.
• a variant of this technique consists in making inactive, instead of deleting them, the areas not masked by the first mask, for example by passivation.
• the active islands 6 being produced, the resin layer 7 is removed by known techniques; for example aqueous baths.
• the insulating layer 8 and the conductive layer 9 are successively deposited.
• the insulating layer 8 is for example a silicon oxide, SiO 2 in particular.
• the insulating layer 8 has a thickness of between 50 and 150 nm. According to the illustration, FIG. 2c, the insulating layer 8 covers the entire substrate. In variants of implementation of the method, the insulating layer 8 covers at least the active islands 6.
• the conductive layer 9 is for example made with N + doped polycrystalline silicon or with a metal, for example tungsten (W), molybdenum (Mo) or aluminum (Al). Between the different metals, the choice is preferably made of aluminum which is the least resistive.
• the conductive layer 9 has a thickness between 150 and 300 nm. It is intended to make the gate of the transistors.
• FIGS. 3a, 3b, 3c, 3d-, 3e, 4a, 4b, 4c, 4d and 4e illustrate the step of sequential etching of the set of gates of the N transistors and of the set of gates of the P transistors.
• the N transistors and the P transistors are produced on the same substrate.
• the first mode of implementation of the method is illustrated by FIGS. 3a to 3e and 4a to 4e which represent different zones of the same substrate.
• Figures 3a to 3e illustrate an implantation area of an N-type transistor
• Figures 4a to 4e illustrate an implantation area of a P-type transistor.
• FIG. 3a represents a substrate 4 covered with a preparation layer 5 on which has been engraved an active island 6.
• the active island 6 is buried under an insulating layer 8, itself covered with a layer conductive 9.
• FIGS. 3a and 3b respectively 4a and 4b
• a layer of protective resin 7 has been deposited to protect certain areas.
• a second mask, not shown, defining the gates of the transistors N makes it possible to engrave only the gates 9 of the transistors N, FIG. 3b.
• the protective resin layer 7 remains intact on the transistors P; Figure 4b illustrates this.
• the etching of the gates of the transistors N consists of an etching produced in an isotropic manner illustrated in FIG. 3b. It is followed by an anisotropic etching illustrated by Figures 3c and 4c.
• the isotropic etching technique used can be either a wet technique or a dry technique.
• the wet technique is generally retained (it consists of dipping the circuit to be etched in a solution).
• the conductive layer 9 is made from polycrystalline silicon or tungsten W, the dry process technique is generally used; it consists in introducing the circuit to be etched in an enclosure filled with a plasma. Isotropic etching gives a depth of overprint L ov - The depth of overprint L ov is controlled between 0.2 and 2 ⁇ m in the case of a dry technique and between 0.5 and 2 ⁇ m in the case of a technique wet. Isotropic etching of the conductive layer 9 is carried out until reaching the insulating layer 8.
• the second mask is maintained during the anisotropic etching.
• Anisotropic etching is exclusively carried out by a dry technique. This operation consists in etching the insulating layer 8 in a self-aligned manner with respect to the resin 7 until reaching an active island 6.
• the succession of the two etchings, isotropic and anisotropic makes it possible to obtain a step at the edge of the grid constituted by the insulating layer 8.
• the width of the step is equal to the depth of the etching L ov .
• L r be the length of the protective resin layer 7 etched during the grid etching operation illustrated in FIG. 3b.
• the length L of the grid, etched in the conductive layer 9, is given by the relation: (1)
• L L r - (2.L 0V )
• the method consists in doping the sources and drains of the N transistors.
• the dopant used is of the N type, for example phosphorus.
• the doping operation is carried out on the surface without mask or protective resin.
• the implantation areas of the P transistors are automatically protected during the doping operation of the N transistors: the metal layer 9 completely covers the implantation areas of the P-type transistors and protects them from the dopant.
• the method includes a particular operation.
• This operation consists of implanting a weakly doped area, called LDD, at the edge of the gate of type N transistors. It is illustrated by Figures 3d and 4d.
• the implantation of a high dose at low energy leads to penetration of the dopant to a depth of about 40 nm. This depth being less than the thickness of the insulating layer 8, the part of the channel 10 located under the insulating layer is protected by the latter during this implantation.
• the implantation of a low dose with high energy has an implantation peak located approximately 150 nm from the surface. It causes penetration of the dopant, beyond the insulating layer 8, into the zone 11 of the channel 10 not protected by the gate 9.
• the active islands 6 of the transistors P are completely protected by the superposition of the insulating layer 8 and the conductive layer 9, as illustrated in FIG. 4d.
• the source 12 and the drain 13 of a transistor are on either side of the gate 9 in the extension of the channel 10. During each of the two preceding implantations, the dopant penetrates into the areas of the active islet not masked by the gate 9 allowing the doping of the source 12 and the drain 13.
• the method advantageously allows implantation of a high dose of phosphorus without having residual resin on the substrate 4. It is in fact known that implantation with high dose of phosphorus (atomic mass 29) is likely to cause the glass plate to heat up to a temperature above 120-150 ° C. The heating compromises the operation of removing the protective resin layer, leaving organic residues on the surface.
• the method then consists in carrying out the operation of etching the gates of the P-type transistors and the doping operation with a P-type dopant. Following the illustration, FIGS. 3e and 4e, the method consists in depositing a layer of protective resin 7 on all of the transistors, both of type N and of type P. A third mask (not shown), reproducing the gates of transistors P and masking all of the transistors of type N, is used for etching the grids 9 of the transistors P.
• the etching operation is of the anisotropic type. It allows the etching of the conductive layer 9 and the insulating layer 8 to self-align with the protective resin 7.
• the doping operation makes it possible to dop the sources 12 and the drains 13 of the P-type transistors.
• the dopant is of the P-type, this can for example be boron.
• the transistors N are protected by the protective resin layer 7.
• the heating problem encountered with phosphorus is almost nonexistent in the case of boron; on the one hand, due to the difference in atomic mass between boron (atomic mass 10) and phosphorus (atomic mass 29) and on the other hand, due to energy which is less important during the implantation of the boron.
• FIG. 5a represents a top view of the transistor N of FIG. 3d, respectively of the transistor P of FIG. 4e.
• Figures 5a and 5b give a truncated view of the transistor N and the transistor P.
• Figures 5a and 5b show schematically the relative arrangement of the gate and the channel of the transistor.
• the transistor N has an insulating step 8.
• the channel 10 is in line with the source 12, not shown, and the drain 13, not shown.
• the grid 9 has a width lg.
• the channel has a width l ⁇ .
• the etching of the grid 9 is carried out so that lg> l ⁇ j, according to the techniques of a person skilled in the art.
• the doping operation of the sources and drains of the N transistors has been described with reference to FIG. 3d. Another embodiment of the doping operation can be implemented. It consists :
• the transistors of the first type are of type P and the transistors of the second type are of type N.
• the method does not include the particular operation which consists in implanting an LDD area.
• the structures obtained are of the type of so-called offset structures.
• the transistors of the second type are produced on a substrate different from the substrate on which the transistors of the first type are produced.
• a device for addressing and controlling a flat screen with liquid crystal and active matrix according to the invention is produced with CMOS transistors obtained by a method according to the invention.
• the addressing and control device includes an addressing device and a control device.
• the addressing device is a CMOS complementary transistor device.
• the N-type and P-type transistors are obtained according to the third mode of implementation of the method.
• the other embodiments of the addressing device are produced by the other embodiments of the method for producing transistors according to the invention.
• the control device is a device which requires transistors having a low leakage current.
• Transistors of type N are produced according to the first mode of implementation of the method. Since the control device does not require additional transistors, the first embodiment of the method can be limited to the sole production of the N transistors. In another embodiment of the control device, the transistors are of type P. The P type transistors are produced according to the second mode of implementation of the method. Since the control device does not require additional transistors, the second mode of implementation of the method can be limited to the sole production of the transistors P.
• the invention has been described using the example of a glass substrate.
• the invention is applicable to other types of substrate, such as plastic substrates or quartz.
• the process according to the invention takes place at a given temperature within a certain range.
• a glass substrate corresponds to a determined temperature range.
• a plastic substrate corresponds to another temperature range, lower than the determined temperature range.
• Yet another temperature range corresponds to a quartz substrate, higher than the determined temperature range.

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• Engineering & Computer Science (AREA)
• Power Engineering (AREA)
• Physics & Mathematics (AREA)
• Condensed Matter Physics & Semiconductors (AREA)
• General Physics & Mathematics (AREA)
• Computer Hardware Design (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Manufacturing & Machinery (AREA)
• Thin Film Transistor (AREA)
• Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
• Liquid Crystal (AREA)
• Devices For Indicating Variable Information By Combining Individual Elements (AREA)

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• 1998
  • 1998-12-18 FR FR9816028A patent/FR2787634B1/fr not_active Expired - Fee Related
• 1999
  • 1999-12-15 KR KR1020007009131A patent/KR100722728B1/ko not_active IP Right Cessation
  • 1999-12-15 WO PCT/FR1999/003151 patent/WO2000038229A1/fr active IP Right Grant
  • 1999-12-15 EP EP99958336A patent/EP1057215A1/de not_active Withdrawn
  • 1999-12-15 JP JP2000590208A patent/JP2002533925A/ja active Pending
  • 1999-12-15 US US09/601,350 patent/US6627489B1/en not_active Expired - Lifetime

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