EP1036418A2 - Bordure optimale de composants semi-conducteurs - Google Patents

Bordure optimale de composants semi-conducteurs

Info

Publication number
EP1036418A2
EP1036418A2 EP98963372A EP98963372A EP1036418A2 EP 1036418 A2 EP1036418 A2 EP 1036418A2 EP 98963372 A EP98963372 A EP 98963372A EP 98963372 A EP98963372 A EP 98963372A EP 1036418 A2 EP1036418 A2 EP 1036418A2
Authority
EP
European Patent Office
Prior art keywords
insulator
metallization
curvature
area
profile
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP98963372A
Other languages
German (de)
English (en)
Inventor
Roland Sittig
Detlef Nagel
Ralf-Ulrich Dudde
Bernd Wagner
Klaus Reimer
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fraunhofer Gesellschaft zur Forderung der Angewandten Forschung eV
Original Assignee
Fraunhofer Gesellschaft zur Forderung der Angewandten Forschung eV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fraunhofer Gesellschaft zur Forderung der Angewandten Forschung eV filed Critical Fraunhofer Gesellschaft zur Forderung der Angewandten Forschung eV
Publication of EP1036418A2 publication Critical patent/EP1036418A2/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H01L29/404—Multiple field plate structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/872—Schottky diodes

Definitions

  • edge terminations are used in the prior art, so-called "junction terminations", which, for example as specially shaped field plates, optimize the course of equipotential lines and accordingly avoid high field strengths lead in the edge area of such components, cf. DE-A 195 35 322 (Siemens) in column 3, line 58 to column 4, line 35 or "Multistep Field Plates " from IEEE Transactions on electron. devices, vol. 39, no. 6, June 1992, pages 1514 ff, "The Contour of an Optimal Field
  • planar edge closures described there are optimized in terms of their geometry, on the one hand as a stepped field plate and on the other hand as an optimized, continuously curved field plate with a modified elliptical geometry, but so far it has not been successful in the prior art to optimize it to be able to economically produce the geometric structure of a field plate in the edge region of a lockable semiconductor component, in particular a component that can be subjected to a high voltage above 500V.
  • the invention sees its task in producing the above-mentioned, in particular highly locking or lockable components on an economical basis, that is to say at low cost, and yet utilizing their maximum locking capability.
  • an edge region of the inner anode metallization has an insulator profile that has a flat beginning and continuously curved outward and upward shape, which region is the "region of curvature" of the insulator profile, and one thereon directly adjacent, practically flat "base area” which, together with the curvature area, defines the cross section of the insulator profile.
  • the insulator profile is designed in such a way that extreme values of an electrical field that arises during operation can be avoided between the curved inner metallization, which extends the anode outwards, and the outer metallization, which is usually the cathode, next to the base area of the insulator profile.
  • the insulator profile is produced by a method in which an initially applied thick insulator layer is additionally covered on the entire substrate with a resist layer, which is illuminated in a structured manner by a mask, which changes in the gray tone value in accordance with the desired curvature in the curvature area of the respective insulator profile.
  • the gray tone value in the mask is transferred to the resist layer by exposure, which can then be patterned, in particular by development, in order then to transfer the structure of the developed resist layer into the strong insulator layer using an etching process such as RIE (reactive ion etching), it is advantageous if the etching rate of the insulator layer and the etching rate of the remaining resist residues which remain after the development of the exposed resist layer are approximately the same, in order to avoid a non-conformal transfer of the resist profile into the insulator.
  • the resulting insulator profiles can either run as a wall around the anode or a plurality of insulator profiles that are staggered outwards and have different curvatures can be provided. If several staggered isolator profiles are provided
  • Metallizations are applied to the respective curved surfaces mentioned, which conductively merges into the anode metallization for the insulator profile which is directly adjacent on the outside to the inside anode.
  • the structuring of the exposure coded in the gray tone value takes place in such a way that a desired light intensity profile in the halftone process, i.e. via a pixel grid in which the mask is coded and the pixel sizes below the resolution limit of a reducing projection exposure are converted into an almost continuous exposure curve of the resist layer, which thus makes it possible to produce continuous surfaces that curve outwards and upwards;
  • the isolator profiles designed according to the invention thus have at least one continuous surface (without steps) over a considerable area, which is designed in such a way that theoretical calculations for an optimized course of the field lines under reverse voltage stress or forward blocking stress appear favorable.
  • the thickness of the insulator layer can be varied in a predetermined manner in a controlled manner in a process over a wide range up to 10 ⁇ m; it is not absolutely necessary to give the surface curvature an ideal course if it is only ensured that the substantial field strength increases can be avoided and the reverse voltage stress at the edge of the anode towards the cathode has no significant extreme values.
  • the theoretically maximum possible reverse voltage can be achieved with a minimal space requirement for the edge termination, that is to say the "blocking capability" of the space taken up can be fully utilized.
  • the minimum space requirement is the
  • Components of importance which are manufactured in multiples from one wafer, and the highest possible utilization of the blocking ability becomes all the more important the higher the blocking voltages. These aspects are particularly important for high-blocking IGBTs.
  • the insulator profiles produced according to the invention can also be used advantageously in Schottky diodes which are not based on a pn junction but instead utilize the blocking capability of a metal-semiconductor junction.
  • the small effective radii of curvature would lead to enormous field increases.
  • diffused guard rings are used according to the prior art, which, however, lead to an undesired injection of minority charge carriers in the event of high forward load.
  • the component has those which do not run out continuously or continuously at the transition to the anode, but with a small jump in the order of magnitude of above 5 nm and below End 50 nm.
  • This step is very low compared to the thickness of the metallization and is practically insignificant, but results from the manufacturing process using gray-tone lithography.
  • the metallization can be approximately 1 ⁇ m thick, while the “jump” of the isolator at the end of the curvature region of the isolator produced by gray-tone lithography is 20 nm.
  • the gray tone lithography works in such a way that the substrate is covered with an insulator layer, which is first covered with a light-sensitive layer, which is exposed in such a way that the curvature of the surface of the insulator profile is varied by gray tone, that is to say by adapting the light intensity distribution to the shape of the insulator profile, is exposed in the photoresist layer, which is then structured by development (claim 11).
  • the photoresist layer structured in this way now still consists of resist residues which form blocks on the insulator layer which correspond to the insulator profiles.
  • the resist residue still above the substrate surface is etched conformally into the insulator layer, the insulator layer being removed essentially over the entire area and being removed more strongly where the resist residues are not (claim 6).
  • the correct transfer is favored if the etching rates of the resist residues and the insulator layer are the same; if they are different, the shape of the resist residue must be adapted accordingly, which can be done by adjusting the intensity distribution during the exposure.
  • the height of the insulator profile in the base area can be chosen rather higher or rather lower (claim 4, claim 5). If the insulator profile in the base area has a height of above approximately 5 ⁇ m, the inclination at the end of the curvature area in the transition to the base area is above 10 °. The area of curvature ends here steeper than in the insulator profile, which is flat in the base area (claim 5). With a higher base area, the tooo
  • the penetration depth of the diffused zones below the metallization is preferably only small, preferably below 10 ⁇ m, which does not give rise to field peaks technologically.
  • the p + diffusion zones transfer their potential to the respective metallization that curves outwards and upwards (away from the substrate).
  • the lateral extent of the metallic curvature areas should be matched to the space charge depth and should correspond to about two to three times the space charge depth.
  • FIG. 1 shows in cross section a section of an active part of a lockable semiconductor element, here a diode with anode 1 and cathode 2, 3, and an edge region of the anode, which is designed by means of a planar edge termination, here a field plate, as shown in FIGS. 3 in enlarged form of the AV area.
  • FIG. 2a is an illustration of the structuring of a photoresist layer 20 which is initially present over the entire surface and, after structuring (by exposure) with the shape 20a shown, is transferred conformally into the insulator 10 by means of dry etching 60, here a reactive ion etching (RIE).
  • dry etching 60 here a reactive ion etching
  • Figure 2b corresponds to Figure 2a, a representation of staggered resist profiles 20b, 20c, 20d, which are arranged in series on the insulator 10 to the outside, starting with reactive ion etching 60, the resist residues (resist profiles), which already have the shape desired Have insulator profiles in the
  • FIG. 3a is a section through a finished edge finish, which was created after completion of the reactive ion etching 60 according to FIG. 2a and with a metallization 30a, the anode metallization 1 in the region of curvature
  • FIG. 3 b is a result of the finished production process for the staggered insulator profiles, which were started according to FIG. 2 b, to be transferred into the insulator layer 10.
  • the figure is only a schematic explanation, with the Cut lines "S" take out a large area of unchanged shape.
  • FIG. 4 and FIG. 4a are a representation of a flatter insulator profile 11, which has a small one towards the anode 31 at the inner end
  • This step is less than 50 nm, preferably it is in the order of magnitude between 20 nm and 30 nm in the case of a metallization 31, 31a, 31b overlying it with a
  • the flat insulator profile is supplemented with a metallic shield 32 which, starting from the anode metallization 31, is designed in the manner of a hood and an elliptical shape which extends laterally outwards and upwards following the curvature of the metallization.
  • a potting compound 41 insulates the area between the anode, metallic hood 32 and cathode 3, outside the end of the insulator profile, which here has a lateral size of approximately 50 times to 200 times the height of the
  • Profile 11 has in the base area.
  • Figure 5 schematically illustrates the structure of a
  • Gray-tone lithography produced insulator profile with curvature area KB and extensive base area SB, the latter of which has an approximately constant height "h", while the curvature area drops from the constant height in a steady course towards the anode and there, preferably through a small step 11s, to the level of the substrate 9 arrives.
  • a metallization MET1 is applied in the area of curvature, it extends the anode metallization 1.31 and allows a controlled course of the field lines between the anode and the outer cathode MET2 without strong extreme values.
  • FIG. 6 is an approximately true-to-scale illustration of the
  • the diffused zones 8, 7b, 7a below the metallizations in FIGS. 3a and 3b have only a small penetration depth of less than 10 ⁇ m, preferably 3 to 6 ⁇ m.
  • the semiconductor acc. Figure 3b is very inexpensive to manufacture because the insulator profiles have only a small height h 1Q in the base area SB.
  • the height h 10 will be less than 5 ⁇ m, preferably in the order of 2 ⁇ m.
  • the three staggered metallizations described are located at different potentials from the anode 1 via the first stage 1 ′ with a curved region 30c and the second stage 1 ′′ with a curved region 30d, which are present from the potential-transmitting zones 7b, 7a
  • the extent of the potential-transmitting zones 7a, 7b diffused from the crystal region of the substrate 9, which are not deeply diffused in, are selected such that they begin in each case below the outer end region of the base region of the insulator profile and outwardly approximately up to that Extend area in which the insulator profile lying further out with its curvature area KB begins to arise or rise.
  • FIGS. 3a and 3b The production of the geometries of FIGS. 3a and 3b will be explained using FIGS. 2a and 2b.
  • FIG. 2a shows the starting point at which a shape 20a formed after structuring (by exposure) Resist profiles or resist residues from a photoresist layer 20 which is present over the entire surface (shown in broken lines) is transferred in conformity to the insulator layer 10 underneath.
  • a dry etching process here a reactive ion etching by ion radiation 60, is shown as the etching process.
  • a diffused region 8 (p + diffusion region) under the anode to be produced and a diffused channel stopper 7 with an n + diffusion region (outside the resist profile to be formed) are previously introduced into the substrate 9.
  • An insulator 10 is applied uniformly to the substrate 9 prepared in this way and has essentially the height that a later resist profile in the base region SB of FIG. 3a is to have.
  • An additional resist layer 20 is applied to the insulator profile, which is first illuminated in a structured manner by a mask, which mask changes in the gray tone value in accordance with the respective curvature in the curvature region KB of the insulator profile.
  • the gray tone value in the mask (not shown) is transferred by the exposure into the resist layer 20, which is then patterned (in particular by development), and then in the etching process shown in FIG.
  • the resist residues remaining after the exposure and development into the insulator layer 10 to be transferred figuratively speaking the surface of the previous resist layer 20 is lowered onto the surface of the substrate, that is to say the remaining resist relief 20a is lowered into the insulator layer (figuratively speaking) as an insulator profile.
  • the insulator 10 is removed where there are no resist blocks, is less removed where the height of the resist residue 20a is low, and where the resist residue 20a is to form the base region SB, little or nothing is removed from the insulator height.
  • Metallizations are then applied, possibly also the wall-like casting compound 40, in order to complete the edge closure.
  • FIG. 3b The structure of FIG. 3b is produced in the same way according to the production method shown schematically in FIG. 2b, which takes place analogously to the manufacture of FIG.
  • a staggered arrangement of insulator profiles 10b, 10c, 10d has been imaged from resist residues 20b, 20c, 20d, corresponding to the resist residue 20a from FIG. 2a.
  • the starting point in FIG. 2b is also the flat one
  • Resist layer 20 is patterned illuminated and resist residues leaves that are conformally mapped in the thinner here chosen insulator 10 by a dry etching process 60, the height h j _g microns in the size range of less than 5, in particular 2 microns for the staggered arrangement is located.
  • the potential-transmitting zones or - in the case of a circular design - rings 7a, 7b are diffused into an n ⁇ substrate 9, these zones being placed in such a way that they lie below that area of the insulator 10 come to rest, in which the flat resist layer 20 is virtually completely removed by the development.
  • Areas of curvature of the resist residues 20b, 20c, 20d can be identified with a. ⁇ > A. > oi2 are expressed, i.e. an increasing inclination at the upper end of the curvature range for everyone lying further out Resist residue, which translates into a correspondingly increasing inclination of the upper end of the staggered curvature areas KB of FIG. 3b.
  • FIG. 5 shows an enlarged detail from either FIG. 3a or the outer step of the field plate 1 "of FIG. 3b.
  • FIG. 5 is subdivided into a left-hand curvature area KB with a lateral extension b- ⁇ and in a base region SB with a lateral extension b 2.
  • the substrate 9 is arranged below the insulator profile (comprising the curvature region and the base region).
  • the outer metallization MET2 begins with a thickness d m , left of that
  • the base region at the upper end of the curvature region KB begins the inner metallization MET1 which runs inwards and which is applied to a correspondingly curved surface OF with a thickness d m .
  • the angle of inclination a at the upper end of the curvature area is shown. For the examples in FIG. 3a or 3b, it corresponds to the angle a. ⁇ Or ⁇ ⁇ .
  • the height h of the base area SB corresponds to the height h 1Q of FIGS. 3a, 3b.
  • Figure 4 with its enlarged detail in Figure 4a shows an insulator profile 11, which can be designed in accordance with the flat insulator profile of Figure 3b, but does not consist of several staggered arrangements, but has a hood 32 which extends above the insulator profile and acts as a shield with an outer curved area 32a is used. It is connected in a galvanically conductive manner to the anode 31 (above the p + diffusion region 8) and extends first upwards and then laterally outwards with a constant height 41 . The area between the lower surface of the hood 32 and the insulator profile and the metallization 31, 31a, 31b is filled with a casting compound 41, which has an insulating effect.
  • Figure 4 is not to scale, instead the structural elements are to be explained on it.
  • FIG. 6 An example of an imaginary, approximately true-to-scale design of the arrangement according to FIG. 4 is shown in FIG. 6.
  • Insulator profile 11 are explained. This inner end, which essentially begins at the outer end of the p + diffusion zone 8, is provided with a step 11s which is formed on the order of 20 nm to 30 nm; it can also deviate from these values, but is usually less than 50 nm high, which height is marked with "d".
  • This stage arises in the manufacturing process according to FIGS. 2a, 2b and follows from the gradation of the gray tone value of the mask during the exposure.
  • the gray tone value cannot decrease infinitely finely to zero (permeable mask), so that from a minimum gray tone value no further grading takes place and during exposure the step 11s initially occurs in the resist residue 20a or 20b and then in the insulator 10 by dry etching 60 is transmitted.
  • the course of the metallization 31 to the curvature area 31b which runs continuously without a step, also has a slight increase 31a, which, however, is hardly noticeable at a metallization thickness of mostly 1 ⁇ m compared to the preferred step height "d" in the range of 50 nm and extreme values not caused in the field line course.
  • the insulator 10 here has a flat height h- j n according to FIG. 3b, which is below 5 ⁇ m and is preferably located at 2 ⁇ m.
  • the radius r represented as r 32 in FIG. 4, has a dimension of 100 ⁇ m, for example, and the distance b 1Q according to FIG. 4 is also formed.
  • the lateral is also suitable for this
  • Extension of the curvature region KB of the insulator profile 11 is provided with a width b 9 which essentially corresponds to the width b 1Q .
  • the distance between the lower surface of the hood 32 and the curved field plate 31b in the region of curvature and the base region 10 is in the example between 10 ⁇ m and 30 ⁇ m, represented by h 4 ⁇ , as shown in FIG. 4.
  • This area like the area of curvature and the area located laterally further out, is filled with a casting compound 41. It isolates and forms a mechanical stabilization.
  • a lockable semiconductor component is an IGBT, thyristor, GTO or diode, in particular. Schottky diode.
  • an insulator profile (10a, 10b, 10c, 10d, ll) with a curvature area (KB) and base area (SB) is provided (directly) on the substrate (9) of the component.
  • which insulator profile in the curvature area (KB) has a surface (OF) which, starting flat, runs more and more curved outwards and upwards.
  • On the surface (OF) is one of the

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Thyristors (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)

Abstract

L'invention concerne un élément semi-conducteur blocable, tel qu'un transistor polaire à grille isolée (IGBT), un thyristor, un GTO ou une diode, notamment une diode de Schottky. Dans la bordure d'une couche métallique anode (1, 31), un profilé isolateur (10a, 10b, 10c, 10d, 11) est solidement fixé (au niveau de cette bordure directement) au substrat (9) du composant. Ce profilé isolateur comprend une zone de courbure (KB) et une zone socle (SB), la zone de courbure présentant une surface (OF) qui commence plate puis s'élève vers l'extérieur avec une inclinaison de plus en plus forte. Une couche métallique (MET1; 30a, 30b, 30b, 30d, 31b) appliquée sur la surface (OF) suit directement la courbure de cette surface et prolonge latéralement la couche métallique interne anode. L'extrémité supérieure de la couche métallique courbée (MET1; 30a; 30b...) est distante et isolée d'une couche métallique extérieure (MET2; 3) enveloppante par la zone socle circonférentielle (SB) du profilé isolateur (10a,...,11) de telle façon qu'un tracé de ligne de champ largement stable, évitant les valeurs extrêmes, soit généré entre les deux couches métalliques (1, 31,MET1,3,MET2) par application d'une tension à l'état bloqué ou d'une tension de blocage ou d'une tension entre les couches métalliques distantes.
EP98963372A 1997-11-24 1998-11-23 Bordure optimale de composants semi-conducteurs Withdrawn EP1036418A2 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE19752020 1997-11-24
DE19752020 1997-11-24
PCT/DE1998/003453 WO1999027582A2 (fr) 1997-11-24 1998-11-23 Bordure optimale de composants semi-conducteurs

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EP1036418A2 true EP1036418A2 (fr) 2000-09-20

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US (3) US6426540B1 (fr)
EP (1) EP1036418A2 (fr)
JP (1) JP2001524756A (fr)
DE (1) DE19881806D2 (fr)
WO (1) WO1999027582A2 (fr)

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US20020140046A1 (en) 2002-10-03
JP2001524756A (ja) 2001-12-04
WO1999027582A2 (fr) 1999-06-03
US6426540B1 (en) 2002-07-30
US6956249B2 (en) 2005-10-18
WO1999027582A3 (fr) 1999-07-15
DE19881806D2 (de) 2000-08-24
US20040129993A1 (en) 2004-07-08

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