EP0843316B1 - Nichtflüchtige Halbleiterspeicheranordnung - Google Patents

Nichtflüchtige Halbleiterspeicheranordnung Download PDF

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Publication number
EP0843316B1
EP0843316B1 EP97308480A EP97308480A EP0843316B1 EP 0843316 B1 EP0843316 B1 EP 0843316B1 EP 97308480 A EP97308480 A EP 97308480A EP 97308480 A EP97308480 A EP 97308480A EP 0843316 B1 EP0843316 B1 EP 0843316B1
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Prior art keywords
word lines
blocks
transistors
memory cell
voltage
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EP97308480A
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English (en)
French (fr)
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EP0843316A2 (de
EP0843316A3 (de
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Masaru Nawaki
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Sharp Corp
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Sharp Corp
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/16—Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/08—Address circuits; Decoders; Word-line control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/14—Word line organisation; Word line lay-out
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2216/00—Indexing scheme relating to G11C16/00 and subgroups, for features not directly covered by these groups
    • G11C2216/12—Reading and writing aspects of erasable programmable read-only memories
    • G11C2216/22—Nonvolatile memory in which reading can be carried out from one memory bank or array whilst a word or sector in another bank or array is being erased or programmed simultaneously
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2216/00—Indexing scheme relating to G11C16/00 and subgroups, for features not directly covered by these groups
    • G11C2216/12—Reading and writing aspects of erasable programmable read-only memories
    • G11C2216/24—Nonvolatile memory in which programming can be carried out in one memory bank or array whilst a word or sector in another bank or array is being erased simultaneously
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/10—Decoders

Definitions

  • the present invention relates to an electrically writable/erasable non-volatile semiconductor memory device.
  • the present invention relates to a non-volatile semiconductor memory device having a structure in which a read operation and a write/erase operation in connection with a particular memory cell can be simultaneously performed on one chip.
  • Figure 4 is a circuit configuration diagram of a conventional non-volatile semiconductor memory device (one chip flash memory in which data is erasable on a block basis).
  • a floating gate type MOS transistor is used as a non-volatile memory transistor, which has a floating gate and allows data to be written by injection of channel hot electrons and to be erased by tunnel erasing by a Fowler-Nordheim current.
  • each of memory cell array blocks BL 1 , BL 2 , ..., BL K the above-mentioned floating gate type MOS transistors are arranged in a matrix.
  • Control gates of the transistors in each identical row are commonly connected to form word lines W 1 , W 2 , ..., W M .
  • Drains of the transistors in each identical column are commonly connected to form bit lines B 1-1 , ..., B 1-N , B 2-1 , ..., B 2-M , ..., B K-1 , ... , B K-M .
  • sources of all the transistors arranged in the matrix are commonly connected so as to form common sources S 1 , ..., S K .
  • the word lines in each block are commonly connected to the corresponding ones.
  • the memory cell array blocks BL 1 , ..., BL K respectively have column decoders YD 1 , ..., YD K which selectively connect the plurality of bit lines to a data bus D-BUS in accordance with a signal value of a column selection signal portion of an input address signal at the time of writing and reading data.
  • the memory cell array blocks BL 1 , ..., BL K respectively have output circuits SV 1 , ..., SV K for selectively outputting a predetermined voltage to the common sources S 1 , ..., S K at the time of writing, erasing, and reading data (i.e., GND (ground voltage) at the time of writing and reading data; V HH (high voltage) at the time of erasing data).
  • the output circuits SV 1 , ..., SV K respectively have P-channel MOS transistors P 11 , ..., P K1 for applying a high voltage V HH and N-channel MOS transistors N 11 , ... N K1 for applying a ground voltage GND.
  • a row decoder XD outputs a predetermined word line selection signal commonly to the word lines of each of the memory cell array blocks BL 1 , ..., BL K in accordance with a signal value of a row selection signal portion of an input address signal.
  • An N-channel MOS transistor N 1 applies a predetermined high voltage V PP for writing to the data bus D-BUS, and a sense amplifier SA senses, amplifies, and outputs a current of the data bus D-BUS at the time of reading data.
  • a control signal P/R 2 is set at "H" to turn on a transistor N 21 , whereby the common source S 2 is set at the GND level.
  • the row decoder XD applies a high voltage of around 10 volts for writing to the word line W 2 based on an input address signal.
  • the column decoder YD 2 connects the data bus D-BUS to the bit line B 2-Z .
  • a high voltage is applied to the data bus D-BUS by setting a control signal PGEN at "H”, and a voltage of around 6 volts is applied to the bit line B 2-2 . This allows a current to flow from the bit line B 2-2 to the source S 2 in the memory cell M 2-22 . Hot electrons generated at this time are injected into a floating gate of the memory cell M 2-22 . Thus, writing of data is completed.
  • All the word lines W 1 , ..., W M are set at the GND level by the row decoder XD . Thereafter, control signals ER 2 and P/R 2 are set at "L" so as to set the common source S 2 at a high voltage of around 10 volts during a predetermined period, whereby a high voltage of around 10 volts is applied between sources and control gates of all the memory cells in the memory cell array block BL 2 . Electrons are ejected from the floating gates of all the memory cells. Thus, erasing of data is completed.
  • the transistor N 21 is turned on by setting the control signal P/R 2 at "H", and the common source S 2 is set at the GND level.
  • a voltage of around 5 volts for reading is applied to the word line W 2 by the row decoder XD , and a voltage of around 1 volt is applied to the bit line B 2-2 via the column decoder YD 2 .
  • a current flowing through the memory cells at this time is amplified by the sense amplifier SA . Thus, reading of data is performed.
  • the time required for the above-mentioned respective operations is as follows: the read operation is performed at a relatively high speed, i.e., about tens of nanoseconds, the write operation usually requires several microseconds to about ten microseconds, and the erase operation requires a relatively long period of time, i.e., about hundreds of milliseconds to about 1 second.
  • the write operation includes a write verifying operation for checking whether or not the threshold value of the memory cell has reached a predetermined value after writing, and further requires a re-write operation if the threshold value has not reached the predetermined value. Therefore, the write operation requires a relatively long period of time.
  • the erase operation includes a write operation before erasing for the purpose of equalizing the threshold values of all the memory cells at the time of starting erasing, in addition to the erase verifying and reerase operations similar to the write verifying and re-write operations. Therefore, the erase operation requires the longest period of time.
  • FIG. 5 shows one such example.
  • the word lines are completely isolated from each other at the center thereof to form two word line blocks ( W 1-1 , W 1-2 , ..., W 1-M ) and ( W 2-1 , W 2-2 , ..., W 2-M ), and row decoders XD 1 and XD 2 are provided for the respective blocks. More specifically, memory cell array blocks BL 1 through BL K/2 are driven by the row decoder XD 1 , and the memory cell array blocks BL K/2+1 to BL K are driven by the row decoder XD 2 .
  • the memory cell array blocks BL 1 , BL 2 , ..., BL K may be respectively provided with independent word lines ( W 1-1 , W 1-2 , ..., W 1-M ), ( W 2-1 , W 2-2 , ... W 2-M ), ..., and ( W K-1 , W K-2 , ... W K-M ), so that the memory cell array blocks BL 1 , BL 2 , ..., BL K can be respectively driven by completely independent row decoders XD 1 , XD 2 , ..., XD K , as shown in Figure 6. In this case, a layout area remarkably increases. This is also disadvantageous.
  • the present invention provides a non-volatile semiconductor memory device as set out in claim 1.
  • EP-A-0 478 251 discloses a memory array including a plurality of sub-arrays with repeaters between each pair of adjacent sub-arrays for passing on the energized state of the selected row line and the selected sub-array and de-energizing the row line for sub-arrays which are not selected.
  • JP 05 054682 relates to a nonvolatile semiconductor memory having memory cells arranged in blocks, with a read decoder for each block.
  • WO 96/34391 also relates to a nonvolatile memory with memory cells arranged in blocks, each with a respective local decoder.
  • US 5 448 517 also discloses a matrix memory cell array with memory cells arranged in blocks.
  • the gates of the plurality of switching transistors provided between the blocks are commonly connected on an inter-block basis and supplied with a predetermined transistor ON or OFF voltage.
  • the above-mentioned semiconductor memory device further includes a storage circuit whose stored content is variable, and a transistor switching voltage output circuit for selectively outputting the transistor ON or OFF voltage in accordance with the content stored in the storage circuit.
  • each of the groups of switching transistors includes N channel MOS transistors and P channel MOS transistors respectively connected to the corresponding word lines of the adjacent blocks.
  • the plurality of the word lines of each of the blocks respectively include global word lines for connecting between the blocks, and local word lines for commonly connecting the control gates of the transistors of each identical row of the matrix within each block.
  • switching transistors provided between memory cell array blocks allow the respective word lines to be electrically isolated between any blocks.
  • block regions where data is simultaneously read and written or erased can be arbitrarily set.
  • the switching transistors are merely provided between the respective blocks in addition to two word line selection circuits (row decoders), so that the increase in a chip layout area can be minimized.
  • a word line isolating position can be arbitrarily varied.
  • the invention described herein makes possible the advantage of providing a non-volatile semiconductor memory device in which data can be read from one memory cell array block while data is being written in or erased from another memory cell array block on one chip, with the increase in chip layout area being minimized.
  • Figure 1 is a block diagram of the first example according to the present invention.
  • Figure 2 is a block diagram of the second example according to the present invention.
  • Figure 3 is a block diagram of the third example according to the present invention.
  • Figure 4 is a block diagram of a conventional non-volatile semiconductor memory device.
  • Figure 5 is a block diagram of a conventional non-volatile semiconductor memory device.
  • Figure 6 is a block diagram of a conventional non-volatile semiconductor memory device.
  • Figure 1 is a circuit configuration diagram of a non-volatile semiconductor memory device (one chip flash memory in which data is erasable on a block basis) of Example 1 according to the present invention.
  • a floating gate type MOS transistor is used as a non-volatile memory transistor, which has a floating gate and allows data to be written by injection of channel hot electrons and to be erased by tunnel erasing by a Fowler-Nordheim current.
  • each of memory cell array blocks BL 1 , BL 2 , ..., BL K the above-mentioned floating gate type MOS transistors are arranged in a matrix.
  • Control gates of the transistors in each identical row are commonly connected to form word lines ( W 1-1 , W 1-2 , ..., W 1-M ), ( W 2-1 , W 2-2 , ..., W 2-M ), ..., ( W K-1 , W K-2 , ..., W K-M ).
  • Drains of the transistors in each identical column are commonly connected to form bit lines ( B 1-1 , ..., B 1-N ), ( B 2-1 , ..., B 2-N ), ...
  • the memory cell array blocks BL 1 , ..., BL K respectively have column decoders YD 1 , ..., YD K which connect bit lines, selected in accordance with a signal value of a column selection signal portion of an input address signal, alternatively to a data bus D-BUS-1 or D-BUS-2 at the time of writing and reading data.
  • the memory cell array blocks BL 1 , ..., BL K respectively have output circuits SV 1 , ..., SV K for selectively outputting a predetermined voltage to the common sources S 1 , ..., S K at the time of writing, erasing, and reading data (i.e., GND (ground voltage) at the time of writing and reading data, and V HH (high voltage) at the time of erasing data).
  • the output circuits SV 1 , ..., SV K respectively have P-channel MOS transistors P 11 , ..., P K1 for applying a high voltage V HH and N-channel MOS transistors N 11 , ... N K1 for applying a ground voltage GND.
  • row decoders XD 1 and XD 2 are provided. More specifically, the row decoders XD 1 and XD 2 output a predetermined word line selection signal in accordance with a signal value of a row selection signal portion of an input address signal.
  • Row decoder XD 1 is connected to the respective word lines W 1-1 , ..., W 1-M of the memory cell array block BL 1 .
  • Row decoder XD 2 is connected to the respective word lines W K-1 , ..., W K-M of the memory cell array block BL K .
  • N-channel MOS transistors N 1 and N 2 respectively apply a predetermined high voltage V PP for writing to the data buses D-BUS-1 and D-BUS-2 at the time of writing data.
  • Sense amplifiers SA 1 and SA 2 respectively sense, amplify, and output currents of the data buses D-BUS-1 and D-BUS-2 at the time of reading data.
  • a multiplexer MUX selectively outputs an output signal of the sense amplifier SA 1 or SA 2 in accordance with a control signal.
  • switching MOS transistor groups MOS 1 , ..., MOS K-1 are interposed between the respective memory cell array blocks BL 1 , ..., BL K (i.e., between the word lines of the respective blocks).
  • the switching MOS transistor groups MOS 1 , ..., MOS K-1 respectively include a plurality of N-channel MOS transistors ( NT 1-1 , ..., NT 1-M ), ... , ( NT K-1-1 , ... , NT K-1-M ). Gates of each of the MOS transistor groups MOS 1 , ..., MOS K-1 are commonly connected so as to receive an identical control voltage.
  • Configuration circuits CON 1 , ..., CON K-1 respectively output control voltages G 1 , ..., G K-1 to the commonly connected gates of the switching MOS transistor groups MOS 1 , ... , MOS K-1 .
  • the configuration circuits CON 1 , ... , CON K-1 respectively include registers R 1 , ..., R K-1 and CMOS circuits CM 1 , ..., CM K-1 which selectively output the ground voltage GND or a voltage V xx in accordance with the content ("H" or "L” ) stored in the registers R 1 , ..., R K-1 .
  • the switching MOS transistor groups MOS 1 , ..., MOS K-1 and the configuration circuits CON 1 , ..., CON K-L are components characteristic of the present example.
  • the register R 1 is set at "H” and the registers R 2 to R K-1 are set at "L” through a configuration signal line CSL . It is also possible for a user to set this configuration operation by entering a command after power-on. Alternatively, a manufacturer of flash memories may previously set the configuration operation prior to shipment.
  • the gate control voltage G 1 of the MOS transistor group MOS 1 provided between the word lines W 1-1 , ..., W 1-M of the memory cell array block BL 1 and the word lines W 2-1 , ... , W 2-M of the memory cell array block BL 2 , reaches the GND level, and the respective transistors NT 1-1 , ..., NT 1-M of the MOS transistor group MOS 1 are turned off.
  • the word lines W 1-1 , ..., W 1-M of the memory cell array block BL 1 are electrically isolated from the word lines W 2-1 , ..., W 2-M of the memory cell array block BL 2 .
  • the gate control voltages G 2 , ..., G K-1 of the MOS transistor groups MOS 2 to MOS K-1 between the other memory cell array blocks BL 2 to BL K reach a voltage V xx level, and each transistor of the MOS transistor groups MOS 2 to MOS K-1 is turned on.
  • the word lines are electrically connected to each other between the memory cell array blocks BL 2 to BL K .
  • the column decoders YD 1 , to YD K connect the selected bit lines to either of the data bus D-BUS-1 and D-BUS-2.
  • a control signal P/R 1 is set at "H" to turn on a transistor N 11 , and the common source S 1 is set at a GND level.
  • a voltage of around 5 volts for the read operation is applied to the word line W 1-1 by the row decoder XD 1 .
  • the data bus D-BUS-1 is connected to the bit line B 1-1 through the column decoder YD 1 , whereby a voltage of around 1 volt is applied to the bit line B 1-1 .
  • a current flowing at this time is amplified by the sense amplifier SA 1 .
  • SA 1 sense amplifier
  • a control signal P/R 2 is set at "H", and the common source S 2 is set at a GND level.
  • a high voltage of around 10 volts for the write operation is applied to the word line W K-2 by the row decoder XD 2 .
  • Each voltage V xx of the configuration circuits is set sightly higher than 10 volts (i.e., around 12 volts).
  • the registers R 2 , ..., R K-1 are set at "L", so that the control voltages G 2 to G K-1 are set at 12 volts. Because of this, each transistor of the switching MOS transistor groups between the memory cell array blocks BL 2 and BL K-1 is conducted.
  • a voltage of 10 volts applied to the word line W K-2 is directly transmitted to the word line W 2-2 . Since the word lines W K-1 , W K-3 , ..., W K-M other than the word line W K-2 are set at the GND level by the row decoder XD 2 , the word lines W 2-1 , W 2-3 , ..., W 2-M of the memory cell array block BL 2 are all set at the GND level. The control voltage G 1 of the switching MOS transistor group MOS 1 located between the memory cell array blocks BL 1 and BL 2 is at the GND level at this time.
  • each transistor of this MOS transistor group MOS 1 is in an OFF state, whereby a voltage of the word lines W 2-1 , ..., W 2-M of the memory cell array block BL 2 are not transmitted to the word lines W 1-1 , ..., W 1-M of the memory cell array block BL 1 .
  • a high voltage is applied to the data bus D-BUS-2 by setting a control signal PGEN 2 at "H".
  • a voltage of around 6 volts is applied to the bit line B 2-2 via the column decoder YD 2 , whereby data is written in the memory cell M 2-22 .
  • data is read through the data bus D-BUS-2 by using the sense amplifier SA 2 . When data is found not to have been normally written as a result of this reading, the re-write operation is performed.
  • the memory cell array block BL 1 is operated completely independently from the memory cell array block BL 2 , whereby the read and write operations can be simultaneously performed.
  • memory cell array blocks which are to be independently operated can be arbitrarily selected. For example, in the case where the memory cell array blocks BL 2 and BL 3 are desired to be independently operated, a register R 2 (not shown) is set at "H” , and the other registers, i.e., registers R 1 , R 3 (not shown), ..., R K-1 are set at "L".
  • each transistor of the switching MOS transistor group between the memory cell array blocks BL 2 and BL 3 are in an OFF state, and the word lines W 2-1 , ..., W 2-M of the memory cell array block BL 2 are electrically isolated from the word lines W 3-1 , ..., W 3-M of the memory cell array block BL 3 .
  • the regions to be independently operated are arbitrarily set, and the setting can also be altered.
  • the read and write operations, the write and erase operations, or the read and erase operations can be simultaneously performed in the regions operating independently from each other.
  • a program storage portion and a data storage portion can be provided in one chip flash memory. Furthermore, the setting thereof can be arbitrarily performed.
  • FIG. 2 is a circuit configuration diagram of Example 2 according to the present invention.
  • the difference between Examples 1 and 2 lies in the configuration of each switching MOS transistor group provided between memory cell array blocks. More specifically, in Example 1, the switching MOS transistor groups are composed of N-channel MOS transistors.
  • P-channel MOS transistors ( PT 1-1 , ..., PT 1-M ), ..., ( PT K-1-1 , ... , PT K-1-M ) are connected in parallel to N-channel MOS transistors. Because of the above alteration, one more CMOS circuit CM' 1 , ..., CM' K-1 is added to each of the configuration circuits CON 1 , ..., CON K-1 .
  • Example 1 since the switching MOS transistor groups are composed of N-channel MOS transistors, a voltage V xx supplied to the configuration circuits is required to be made higher by around 2 volts than the word line voltage (10 volts) at the time of writing (for the purpose of preventing the decrease in a threshold voltage).
  • Example 2 since the switching MOS transistor groups are composed of CMOS, a voltage V xx supplied to the configuration circuit can be set at'the identical level with that of the word line voltage at the time of writing.
  • Figure 3 is a circuit configuration diagram of Example 3 according to the present invention.
  • a method for erasing data by applying a negative voltage to word lines is adopted.
  • a voltage to be applied to word lines is set to be negative (i.e., around -10 volts) rather tnan the GND level.
  • the purpose of this is to decrease the level of a high voltage applied to the sources of memory transistors.
  • This method has the advantage that double diffusion for enhancing pressure resistance is not required in source portions, etc.
  • word lines include global word lines ( GW 1-1 , ..., GW 1-M ), ..., ( GW K-1 , ..., GW K-M ), and local word lines ( LW 1-1 , ..., LW 1-M ), ..., ( LW K-1 , ..., LW K-M ) which are suitable for erasing data with a negative voltage.
  • the number of memory cells i.e., the number of bit lines in the memory cell array blocks from which data is independently erased, is different depending upon the block.
  • the memory cell array block BL 1 has N bit lines
  • the memory cell array block BL 2 has L bit lines
  • the memory cell array block BL K has J bit lines.
  • the memory block configuration as shown in Figure 3 is called "boot block” configuration
  • the memory block configuration as shown in Figure 1 in which blocks having the identical number of memory cells are arranged is called “symmetrical block” configuration.
  • the boot block configuration as shown in Figure 3 can be applied to the usual erasing method as shown in Figure 1.
  • the equivalent block configuration as shown in Figure 1 can be applied to the method for erasing data by applying a negative voltage to word lines as shown in Figure 3.
  • a negative voltage is applied to word lines at the time of erasing, so that P-channel MOS transistors are used as switching MOS transistors. If it is possible to use a triple well process even in the case of erasing data with a negative voltage, an N-channel MOS transistor can be formed in a P-well. This allows the electric potential of the P-well to be set at a predetermined negative voltage (i.e., voltage lower than a word line negative voltage at the time of erasing) independently from a P-substrate. Therefore, the switching MOS transistor groups composed of N-channel MOS transistors as shown in Figure 1 or the switching MOS transistor groups composed of CMOS as shown in Figure 2 can be used.
  • a register R 1 is set at "L” and registers R 2 , ..., R K-1 are set at "H” for the purpose of electrically isolating the global word lines between the memory cell array blocks BL 1 and BL 2 .
  • a voltage to be applied to word lines in the case of adopting a method for erasing data with a negative voltage is as follows:
  • voltages V xx and V NEG to be supplied to the configuration circuits are required to be set, for example, at around 10 volts and around -12 volts.
  • a charge pump circuit or the like can be used as a circuit for generating such a voltage.
  • the global word line GW 1-1 is set at around 5 volts by the row decoder XD 1 , whereby a gate voltage L 1 of P-channel MOS transistors between the local word line LW 1-1 and the global word line GW 1-1 is set at a negative voltage of around -2 to -5 volts.
  • Gate voltages L 3 , ..., L K of the P-channel MOS transistors between the global word lines and the local word lines in the other blocks are set, for example, at 10 volts so as to turn off the P-channel MOS transistors.
  • the setting of each gate voltage L 1 , ..., L K is controlled based on the information specifying the blocks to be operated in parallel and the information indicating which operation (i.e., the read, write, or erase operation) is performed in the blocks.
  • word lines can be electrically isolated.
  • the regions to be independently operated can be arbitrarily set, and the setting can be altered.
  • the read and write operations, the write and erase operations, and the read and erase operations can be simultaneously performed in the regions operating independently from each other.
  • a very useful non-volatile semiconductor memory device in which memory blocks where the read, write, and erase operations are completely independently performed can be arbitrarily selected and altered while minimizing the increase in a layout area by interposing simple switching transistors in series between word lines on the basis of a block to be erased. Furthermore, according to the present invention, word lines are electrically isolated so as to decrease a load capacitance of each word line. Therefore, a read speed can be enhanced.
  • blocks BL 2 to BL K are assigned as data storage portions in which data is written or erased, the load capacitance of word lines to be driven by the row decoder XD 1 decreases. Therefore, the transition speed of the word lines is enhanced, whereby the read speed of the program storage portion can be enhanced.

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  • Microelectronics & Electronic Packaging (AREA)
  • Read Only Memory (AREA)
  • Non-Volatile Memory (AREA)

Claims (5)

  1. Nichtflüchtige Halbleiterspeichereinrichtung mit mehr als zwei Speicherzellenanordnungsblöcken (BL1, BL2, ..., BLK) auf einem einzelnen integrierten Schaltkreis.
       wobei jeder der Blöcke aufweist:
    nichtflüchtige Speichertransistoren (M), welche in der Lage sind, elektrische Informationen zu schreiben, zu löschen und zu lesen, wobei die Transistoren in einer Matrix angeordnet sind und wobei die Sourcebereiche aller Transistoren gemeinsam miteinander verbunden sind.
    eine Mehrzahl Wortleitungen (W1-1, W1-2, ..., W1-M, WK-1, WK-2, ..., WK-M) zum gemeinsamen Kontaktieren von Steuergatebereichen der Transistoren in jeder identischen oder gleichen Zeile der Matrix,
    eine Mehrzahl Bitleitungen (B1-1, B1-2, ..., B1-N, BK-1, BK-2, ..., BK-N) zum gemeinsamen Verbinden von Drainbereichen der Transistoren in einer identischen oder selben Spalte der Matrix,
    einen Bitleitungsauswahlschaltkreis (YD1, ..., YDK) zum selektiven oder wahlweisen Verbinden der Mehrzahl Bitleitungen mit einem von zwei Datenbussen (D-BUS-1, D-BUS-2) gemäß einem Signalwert eines ersten vorbestimmten Bereichs eines Eingabeadressensignals und
    einen Spannungsauswahlausgabeschaltkreis (SV1, ..., SVK) zum wahlweisen Ausgeben einer vorbestimmten Spannung an die gemeinsam verbundenen Sourcebereiche zu einem Zeitpunkt des Schreibens, Löschens oder Lesens von Informationen,
       dadurch gekennzeichnet,
    dass die Mehrzahl Wortleitungen jedes Blocks jeweils mit den korrespondierenden Wortleitungen in einem benachbarten oder angrenzenden Block über eine Gruppe von Schalttransistoren (MOS1, ..., MOSK-1) verbunden ist, die zwischen den Blöcken vorgesehen sind, um eine Kette von Blöcken zu bilden,
    wobei jede Gruppe von Schalttransistoren individuell ein- oder ausgeschaltet werden kann, um die Wortleitungen angrenzender oder benachbarter Blöcke miteinander elektrisch zu verbinden oder voneinander elektrisch zu isolieren,
    dass ein erster Zeilendecodierer (XD1) mit den Wortleitungen des Blocks (BL1) an einem Ende der Kette und ein zweiter Zeilendecodierer (XD2) mit den Wortleitungen des Blocks (BLK) am anderen Ende der Kette verbunden sind.
    dass zumindest zwei Wortleitungsauswahlschaltkreise (XD1, XD2) des Weiteren vorgesehen sind, die ein vorgegebenes Wortleitungsauswahlsignal gemäß einem Signalwert eines zweiten vorbestimmten Bereichs eines Eingabeadresssignals ausgeben,
    dass die Mehrzahl Wortleitungen eines vorbestimmten Paares zweier Blöcke unter der Mehrzahl Blöcke jeweils mit den korrespondierenden Wortleitungsauswahlschaltkreisen verbunden ist und
    dass jeder der Bitleitungsauswahlschaltkreise die ausgewählte Bitleitung gemäß eines Signalwerts des ersten vorbestimmten Bereichs des Eingabeadresssignals alternativ mit einem der beiden Datenbusse (D-BUS-1, D-BUS-2) verbindet.
  2. Nichtflüchtige Halbleiterspeichereinrichtung nach Anspruch 1,
    bei welcher die Gatebereiche der Mehrzahl Schalttransistoren (NT1-1, ..., NT1-M, NTK-1-1, ..., NTK-1-M), die zwischen den Blöcken vorgesehen sind, miteinander auf einer Zwischenblockbasis verbunden und mit einer vorbestimmten Transistor-EIN- oder -AUS-Spannung versorgt sind.
  3. Nichtflüchtige Halbleiterspeichereinrichtung nach Anspruch 2,
    welche des Weiteren einen Speicherschaltkreis (R1, ..., RK-1), dessen gespeicherter Inhalt variabel ist, und einen Transistorschaltspannungsausgabeschaltkreis (CM1, ..., CMK-1) aufweist zum wahlweisen Ausgeben der Transistor-EIN- oder -AUS-Spannung gemäß des im Speicherschaltkreis gespeicherten Inhalts.
  4. Nichtflüchtige Halbleiterspeichereinrichtung nach Anspruch 2,
    bei welcher jede der Gruppen Schalttransistoren N-Kanal-MOS-Transistoren (NT1-1, .... NT1-M, NTK-1-1, ..., NTK-1-M) und P-Kanal-Transistoren (PT1-1, ..., PT1-M, PTK-1-1, ..., PTK-1-M) aufweist, die jeweils mit den korrespondierenden Wortleitungen benachbarter oder angrenzender Blöcke verbunden sind.
  5. Nichtflüchtige Halbleiterspeichereinrichtung nach Anspruch 2,
    bei welcher die Mehrzahl Wortleitungen jedes Blocks jeweils aufweist:
    globale Wortleitungen (GW1-1, ..., GW1-M, GWK-1, ..., GWK-M) zum Verbinden zwischen den Blöcken und
    lokale Wortleitungen (LW1-1, ..., LW1-M, LWK-1, ..., LWK-M) zum gemeinsamen Verbinden der Steuergates der Transistoren jeder identischen oder gleichen Zeile der Matrix innerhalb jedes Blocks, wobei diese jeweils mit den globalen Wortleitungen verbunden sind.
EP97308480A 1996-11-14 1997-10-23 Nichtflüchtige Halbleiterspeicheranordnung Expired - Lifetime EP0843316B1 (de)

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Application Number Priority Date Filing Date Title
JP302269/96 1996-11-14
JP30226996 1996-11-14
JP30226996A JPH10144086A (ja) 1996-11-14 1996-11-14 不揮発性半導体記憶装置

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EP0843316A2 EP0843316A2 (de) 1998-05-20
EP0843316A3 EP0843316A3 (de) 1999-05-19
EP0843316B1 true EP0843316B1 (de) 2003-12-10

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EP (1) EP0843316B1 (de)
JP (1) JPH10144086A (de)
KR (1) KR100287131B1 (de)
DE (1) DE69726698T2 (de)
TW (1) TW355844B (de)

Families Citing this family (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3940513B2 (ja) 1999-01-11 2007-07-04 株式会社東芝 半導体記憶装置
KR100560634B1 (ko) * 1999-01-13 2006-03-16 삼성전자주식회사 불휘발성 반도체 메모리 장치
EP1052646B1 (de) 1999-05-11 2004-07-14 Fujitsu Limited Nichtflüchtige Halbleiterspeicheranordnung, die eine Datenleseoperation während einer Datenschreib/lösch-Operation erlaubt
US6163478A (en) * 1999-10-19 2000-12-19 Advanced Micro Devices, Inc. Common flash interface implementation for a simultaneous operation flash memory device
US6240040B1 (en) * 2000-03-15 2001-05-29 Advanced Micro Devices, Inc. Multiple bank simultaneous operation for a flash memory
JP2001283594A (ja) * 2000-03-29 2001-10-12 Sharp Corp 不揮発性半導体記憶装置
US6851026B1 (en) * 2000-07-28 2005-02-01 Micron Technology, Inc. Synchronous flash memory with concurrent write and read operation
KR100368590B1 (ko) * 2000-04-17 2003-01-24 삼성전자 주식회사 비등분할 메모리 블록을 가진 반도체 메모리 장치
JP3871184B2 (ja) 2000-06-12 2007-01-24 シャープ株式会社 半導体記憶装置
US6594194B2 (en) * 2001-07-11 2003-07-15 Sun Microsystems, Inc. Memory array with common word line
US7184307B2 (en) * 2001-08-28 2007-02-27 Samsung Electronics Co., Ltd. Flash memory device capable of preventing program disturbance according to partial programming
US6741502B1 (en) 2001-09-17 2004-05-25 Sandisk Corporation Background operation for memory cells
US7177197B2 (en) * 2001-09-17 2007-02-13 Sandisk Corporation Latched programming of memory and method
US20050185465A1 (en) * 2003-03-11 2005-08-25 Fujitsu Limited Memory device
JP2005116119A (ja) 2003-10-10 2005-04-28 Toshiba Corp 不揮発性半導体記憶装置
US7058754B2 (en) * 2003-12-22 2006-06-06 Silicon Storage Technology, Inc. Nonvolatile memory device capable of simultaneous erase and program of different blocks
US7092288B2 (en) * 2004-02-04 2006-08-15 Atmel Corporation Non-volatile memory array with simultaneous write and erase feature
KR100610006B1 (ko) * 2004-05-04 2006-08-08 삼성전자주식회사 호스트 시스템의 다중동작 지원에 적합한 메모리 구조를갖는 반도체 메모리 장치
EP1727153B1 (de) * 2005-05-25 2008-10-15 STMicroelectronics S.r.l. Entladeschaltung für einen wortweise löschbaren Flash-Speicher
JP2007128633A (ja) * 2005-10-07 2007-05-24 Matsushita Electric Ind Co Ltd 半導体記憶装置及びこれを備えた送受信システム
JP2007157331A (ja) * 2007-03-16 2007-06-21 Ricoh Co Ltd 複合化フラッシュメモリ及びそれを搭載した携帯用機器
KR20110131208A (ko) * 2009-02-09 2011-12-06 램버스 인코포레이티드 동기화된 제어를 갖는 다중 플레인의 비휘발성 메모리
WO2012160821A1 (ja) 2011-05-24 2012-11-29 パナソニック株式会社 抵抗変化型不揮発性記憶装置および抵抗変化型不揮発性記憶装置の駆動方法
CN102918600B (zh) 2011-05-31 2014-11-19 松下电器产业株式会社 电阻变化型非易失性存储装置
KR102586179B1 (ko) * 2018-10-04 2023-10-10 에스케이하이닉스 주식회사 반도체 장치
CN112634955A (zh) * 2019-09-24 2021-04-09 长鑫存储技术有限公司 Dram存储器
JP2023141465A (ja) * 2022-03-24 2023-10-05 キオクシア株式会社 半導体記憶装置

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5448517A (en) * 1987-06-29 1995-09-05 Kabushiki Kaisha Toshiba Electrically programmable nonvolatile semiconductor memory device with NAND cell structure
US5119340A (en) * 1990-09-26 1992-06-02 Sgs-Thomson Microelectronics, Inc. Semiconductor memory having latched repeaters for memory row line selection
JP3143161B2 (ja) * 1991-08-29 2001-03-07 三菱電機株式会社 不揮発性半導体メモリ
US5621690A (en) * 1995-04-28 1997-04-15 Intel Corporation Nonvolatile memory blocking architecture and redundancy
EP0741415A1 (de) * 1995-05-05 1996-11-06 STMicroelectronics S.r.l. Flash-EEPROM-Speicher mit kontaktlosen Speicherzellen

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KR100287131B1 (ko) 2001-04-16
US6081450A (en) 2000-06-27
KR19980042858A (ko) 1998-08-17
JPH10144086A (ja) 1998-05-29
DE69726698D1 (de) 2004-01-22
DE69726698T2 (de) 2004-10-07
EP0843316A2 (de) 1998-05-20
EP0843316A3 (de) 1999-05-19
TW355844B (en) 1999-04-11

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