EP0759664A2 - Multiplexer und Demultiplexer - Google Patents

Multiplexer und Demultiplexer Download PDF

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Publication number
EP0759664A2
EP0759664A2 EP96108607A EP96108607A EP0759664A2 EP 0759664 A2 EP0759664 A2 EP 0759664A2 EP 96108607 A EP96108607 A EP 96108607A EP 96108607 A EP96108607 A EP 96108607A EP 0759664 A2 EP0759664 A2 EP 0759664A2
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EP
European Patent Office
Prior art keywords
stage
data
block
demultiplexer
multiplexer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP96108607A
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English (en)
French (fr)
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EP0759664A3 (de
Inventor
Shimada c/o Mitsubishi K.K. Masaaki
Higashisaka c/o Mitsubishi K.K. Norio
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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Publication of EP0759664A2 publication Critical patent/EP0759664A2/de
Publication of EP0759664A3 publication Critical patent/EP0759664A3/de
Withdrawn legal-status Critical Current

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M9/00—Parallel/series conversion or vice versa
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0685—Clock or time synchronisation in a node; Intranode synchronisation

Definitions

  • the present invention relates to a multiplexer for converting parallel data to serial data and a demultiplexer for converting serial data to parallel data and, more particularly, to a multiplexer and a demultiplexer used for high-speed operation.
  • Figure 19 is a circuit diagram illustrating a prior art multiplexer.
  • the m:1 multiplexer block comprises a plurality of D flip-flops as many as the input parallel data.
  • Reference numeral 4 designates a D flip-flop for timing control.
  • Reference numeral 5a designates a frequency divider that divides the frequency of an input clock signal to produce an output signal having a frequency that is an exact integral submultiple of the input frequency. The integral submultiple depends on the circuit structure of the m:1 MUX block 3a.
  • Reference numeral 60 designates a parallel data input terminal.
  • Reference numeral 61 designates a serial data output terminal.
  • Reference character CLK designates a high-speed clock.
  • Reference numeral 64 designates a high-speed clock input terminal.
  • the prior art multiplexer comprises the output stages S 1 to S n , and the final output stage S n includes the D flip-flop 4 that synchronizes the serial data output from the previous stage S n-1 with the high-speed clock input CLK.
  • the m n-j-1 m:1 MUX blocks 3a in the S j stage are connected to the next stage so that the serial data output from each m:1 MUX block 3a in the S j stage becomes one of the parallel data input to the m:1 MUX block 3a in the next stage or becomes serial data input to the D flip-flop 4 in the S n stage.
  • a plurality of parallel data input to the input terminal 60 are successively converted into serial data by the m:1 MUX blocks 3a, and serial data is produced at the S n-1 stage prior to the final stage.
  • This serial data is synchronized with the clock CLK at the final stage S n and output from the output terminal 61 as a serial data output.
  • FIG 12 is a block diagram for explaining the operating principle of the prior art multiplexer.
  • the multiplexer 200 includes 2:1 MUX blocks 1, 2, and 3 corresponding to the m:1 MUX blocks 3a, 1/2 frequency dividers 5 and 5b corresponding to the frequency dividers 5a, and a D flip-flop 4.
  • Reference character SIG 1 denotes a serial data output from the 2:1 MUX block 3.
  • the multiplexer 200 is a 4:1 multiplexer converting four bit parallel data into serial data, the operating principle is identical even when the bit number of the input parallel data is changed.
  • Figure 13 is a block diagram illustrating a circuit structure of the 2:1 MUX blocks 1 to 3 shown in figure 12.
  • reference numeral 7 designates a D flip-flop
  • numeral 8 designates a D flip-flop with a phase shifter
  • numeral 9 designates a two-input selector. More specifically, the D flip-flop 7 latches the input data and outputs the data synchronously with clocks input to the 2:1 MUX block.
  • the D flip-flop 8 with the phase shifter latches the input data, delays the phase of the data by 1/2 period of the clock input to the 2:1 MUX block, and outputs the data.
  • the two-input selector 9 selects one of the outputs from the D flip-flops 7 and 8 synchronously with a clock signal.
  • the parallel data B input to the D flip-flop 8 is phase-delayed by 1/2 period from the parallel data A input to the D flip-flop 7 when it is input to the selector 9.
  • the parallel data A and the parallel data B are alternatingly selected at intervals equivalent to 1/2 period of the input clock.
  • the 2:1 MUX block converts two bit parallel data into serial data.
  • the operation of the m:1 MUX block 3a shown in figure 19 is fundamentally identical to the above-described operation although the number of the D flip-flops and the operating timing of the selector are different. More specifically, in the m:1 MUX block, the number of the D flip-flops is m, and one of the m D flip-flops has no phase shifter. That is, the (m-1) D flip-flops delay the phases of the input clocks by 1/m period, 2/m period, ..., (m-1)/m period, respectively.
  • the multiplexer 200 comprises the 2:1 MUX blocks 1 to 3, the D flip-flop 4, and the frequency dividers 5 and 5b for dividing frequency of an input clock to 1/2.
  • the 1/2 frequency dividers 5 and 5b produce a clock 1/2CLK having a frequency equivalent to a half of the frequency of the high-speed clock CLK and a clock 1/4CLK having a frequency equivalent to a quarter of the high-speed clock CLK, respectively.
  • the first stage 2:1 MUX blocks 1 and 2 convert four bit parallel data 3, 2, 1, and 0 into two bit parallel data ODD and EVEN in response to the clock 1/4CLK.
  • the second stage 2:1 MUX block 3 converts the two bit parallel data ODD and EVEN into serial data SIG 1 in response to the clock 1/2CLK.
  • the D flip-flop 4 synchronizes the serial data SIG 1 with the high-speed clock CLK that is directly applied from the outside of the multiplexer 200, and obtained serial data output is output from the multiplexer 200.
  • Figures 14(a)-14(k) show a timing chart of the prior art multiplexer. More specifically, figures 14(a)-14(d) show the timings of the parallel data 3, 2, 1, and 0 input to the multiplexer 200, respectively, figures 14(e), 14(h), and 14(j) show the timings of the clocks 1/4CLK, 1/2CLK, and CLK, respectively, figures 14(f) and 14(g) show the timings of the parallel data ODD and EVEN, respectively, figure 14(i) shows the timing of the serial data SIG 1 , and figure 14(k) shows the timing of the serial data output from the multiplexer 200.
  • ⁇ Ta is a delay time in the frequency divider 5
  • ⁇ Tb is a delay time in the frequency divider 5b
  • ⁇ Tc is a delay time in the first stage 2:1 MUX blocks 1 and 2
  • ⁇ Td is a delay time in the second stage 2:1 MUX block 3
  • ⁇ Te is a delay time in the D flip-flop 4.
  • Figures 18(a)-18(c) show the relationship between a clock input and a data input in the D flip-flop 4. More specifically, figure 18(a) shows a clock CLK input, and figures 18(b) and 18(c) show data SIG 1 inputs.
  • reference characters T su and T h denote a setup time and a hold time of the D flip-flop 4, respectively.
  • Reference numeral 19 designates a data SIG 1 changing point.
  • the data should not be changed between the setup time T su and the hold time T h of the D flip-flop 4, and the data SIG 1 should not be changed between the setup time T su and the hold time T h when the clock CLK rises.
  • the D flip-flop 4 selects the data A1.
  • the data SIG 1 is changed between the setup time T su and the hold time T h as shown in figure 18(c)
  • the timing of the data output from the D flip-flop 4 is deviated.
  • the timing of the clock CLK that is input to the D flip-flop 4 and the timing of the data SIG 1 that is obtained using the clock 1/2CLK produced by 1/2 division of the clock CLK are determined by the total of the delay times ⁇ Ta and ⁇ Td.
  • the delay times ⁇ Ta and ⁇ Td are not always as designed and are significantly varied due to variations in the process parameters or the temperature of the constituents of the multiplexer circuit, so that the timing of the clock CLK is sometimes deviated from the timing of the data SIG 1 .
  • the time interval where the data SIG 1 is not changed is shortened, and the timing margin for the setup time T su and the hold time T h of the D flip-flop 4 is reduced, resulting in a difficulty in normally operating the D flip-flop 4.
  • Figure 20 is a block diagram illustrating a circuit structure of a prior art demultiplexer.
  • the 1:m demultiplexer block 13a comprises a plurality of D flip-flops as many as the number of the parallel data.
  • Reference numeral 14 designates a D flip-flop for timing control.
  • Reference numeral 15a designates a frequency divider that divides the frequency of an input clock to produce an output signal having a frequency that is an exact integral submultiple of the input frequency. The integral submultiple depends on the circuit structure of the 1:m DEMUX block 13a.
  • Reference numeral 62 designates a serial data input terminal.
  • Reference numeral 63 designates a parallel data output terminal.
  • Reference character CLK designates a high-speed clock.
  • Reference numeral 65 designates a high-speed clock input terminal.
  • the prior art demultiplexer comprises the output stages S 1 to S n , and the first stage S1 includes the D flip-flop 14 that synchronizes the serial data that is input to the input terminal 62 with the high-speed clock CLK.
  • the m i-2 1:m DEMUX blocks 13a of the S i stage are connected to the previous stage so that the serial data output from the previous D flip-flop 14 or one of the parallel data output from the 1:m DEMUX block 13a of the previous stage is input to the 1:m DEMUX block 13a in the S i stage as serial data.
  • serial data input to the input terminal 62 is synchronized with the clock signal CLK in the S 1 stage and then it is output to the S 2 stage. Thereafter, the data is successively converted into parallel data by the 1:m DEMUX blocks. Finally, the parallel data are output from the output terminals of the final output stage, i.e., the S n stage, as parallel data outputs.
  • FIG. 15 is a block diagram for explaining the operating principle of the prior art demultiplexer.
  • the demultiplexer 400 includes 1:2 DEMUX blocks 11, 12, and 13 corresponding to the 1:m DEMUX blocks 13a, 1/2 frequency dividers 15 and 15b corresponding to the frequency dividers 15a, and a D flip-flop 14.
  • Reference character SIG 1 denotes serial data.
  • the demultiplexer 400 is a 1:4 demultiplexer converting serial data into four bit parallel data, the operating principle is identical even when the bit number of the output parallel data is changed.
  • FIG 16 is a block diagram illustrating a circuit structure of the 1:2 DEMUX blocks 11 to 13 shown in figure 15.
  • the 1:2 DEMUX block comprises a D flip-flop 7 to which serial data is input and a D flip-flop 8 with a phase shifter that delays the phase of the serial data by 1/2 period of the clock with respect to the D flip-flop 7.
  • the period of the clock CLK that is input to the 1:2 DEMUX block is twice as long as the period of the serial data.
  • the serial data is input to the D flip-flops 7 and 8 since the D flip-flop 8 has the phase shifter, the serial data input to the D flip-flop 8 is delayed by one period of the data from the data input to the D flip-flop 7. Since the data output from the D flip-flops 7 and 8 are synchronized alternately, the input serial data are alternately output from the D flip-flop 7 and the D flip-flop 8. In this way, the 1:2 DEMUX block converts the serial data into two bit parallel data.
  • the operation of the 1:m DEMUX block 13a shown in figure 20 is fundamentally identical to the above-described operation although the number of the D flip-flops and the operating timing are changed. More specifically, in the 1:m DEMUX block, the number of the D flip-flops is m, and one of the m D flip-flops has no phase shifter. That is, the (m-1) D flip-flops delay the phases of the input clocks by 1/m period, 2/m period, ..., (m-1)/m period, respectively.
  • the demultiplexer 400 comprises the D flip-flop 14, the 1:2 DEMUX blocks 11 to 13, and the frequency dividers 15 and 15b for dividing frequency of an input clock to 1/2.
  • the frequency dividers 15 and 15b produce a clock 1/2CLK having a frequency equivalent to 1/2 of the frequency of the high-speed clock CLK and a clock 1/4CLK having a frequency equivalent to 1/4 of the frequency of the high-speed clock CLK, respectively.
  • the D flip-flop 14 synchronizes the serial data input to the demultiplexer 400 with the high-speed clock CLK and outputs serial data SIG 1 .
  • serial data SIG 1 is converted into two bit parallel data ODD and EVEN by the 1:2 DEMUX block 13 in the next stage.
  • the two bit parallel data ODD and EVEN are converted into four bit parallel data 3, 2, 1, and 0 by the 1:2 DEMUX blocks 11 and 12 in the final output stage, and these parallel data are output from the demultiplexer 400.
  • Figures 17(a)-17(k) show a timing chart of the prior art demultiplexer 400. More specifically, figures 17(h)-17(k) show the timings of the parallel data 3, 2, 1, and 0 output from the demultiplexer, respectively, figures 17(b), 17(d), and 17(g) show the timings of the clocks CLK, 1/2CLK, and 1/4CLK, respectively, figures 17(e) and 17(f) show the timings of the parallel data ODD and EVEN, respectively, figure 17(c) shows the timing of the serial data SIG 1 , and figure 17(a) shows the timing of the serial data input to the demultiplexer.
  • ⁇ Ta is a delay time in the frequency divider
  • ⁇ Tb is a delay time in the frequency divider 15b
  • ⁇ Tc is a delay time in the first stage D flip-flop
  • ⁇ Td is a delay time in the second stage 1:2 DEMUX block 13
  • ⁇ Te is a delay time in the 1:2 DEMUX blocks 11 and 12 at the final output stage.
  • the timing of the 1:2 DEMUX block 13 Assuming that the setup time and the hold time of the D flip-flops 7 and 8 in the 1:2 DEMUX block 13 are T su and T h , respectively, in order to operate the 1:2 DEMUX block 13 normally, the data SIG 1 must not be changed, i.e., it must be stable, between the setup time T su and the hold time T h when the clock 1/2CLK rises. If the data SIG 1 is changed between the setup time T su and the hold time T h , it becomes unstable which data the D flip-flops 7 and 8 select between the data before the data changing point 19 and the data after that point, whereby the operation becomes unstable.
  • the timing of the clock 1/2CLK and the data SIG 1 to be input to the 1:2 DEMUX block 13 is determined by a difference between the delay time ⁇ Ta and the delay time ⁇ Tc.
  • the delay times ⁇ Ta and ⁇ Tc are not always as designed and are significantly varied due to variations in the process parameters and the temperature of the constituents of the demultiplexer circuit, whereby the timing of the clock 1/2CLK is sometimes deviated from the timing of the data SIG 1 that is synchronized with the clock CLK.
  • the time interval where the data SIG 1 is not changed is shortened, and the timing margin for the setup time T su and the hold time T h of the D flip-flops 7 and 8 is reduced, resulting in a difficulty in operating the 1:2 DEMUX block 13 normally.
  • the multiplexer further includes a variable delay circuit connected to the data input terminal of each multiplexer block in any of the second to the n-th stages, and the variable delay circuit delays the data input by a variable delay time. Therefore, even when the delay times of the constituents of the circuit are varied due to variations in the device parameters or the temperature and the timing of the data input is deviated, the timing of the data input is adjusted by the variable delay circuit, whereby the D flip-flop in the stage having the variable delay circuit is normally operated.
  • the multiplexer further includes a variable delay circuit connected to the clock input terminal of each multiplexer block in any of the first to the (n-1)th stages or to the clock input terminal of the D flip-flop in the n-th stage, and the variable delay circuit delays the clock input by a variable delay time. Therefore, even when the delay times of the constituents of the circuit are varied due to variations in the device parameters or the temperature and the timing of the clock input is deviated, the timing of the clock input is adjusted by the variable delay circuit, whereby the D flip-flop in the stage having the variable delay circuit is normally operated.
  • the multiplexer further includes a variable delay circuit connected to the data input terminal of each multiplexer block in any of the second to the n-th stages, and the variable delay circuit delays the data input by a variable delay time. Therefore, even when the delay times of the constituents of the circuit are varied due to variations in the device parameters or the temperature and the timing of the data input is deviated, the timing of the data input is adjusted by the variable delay circuit, whereby the D flip-flop in the stage having the variable delay circuit is normally operated.
  • the multiplexer further includes a variable delay circuit connected to the clock input terminal of each multiplexer block in any of the first to the (n-1)th stages or to the clock input terminal of the multiplexer block in the n-th stage, and the variable delay circuit delays the clock input by a variable delay time. Therefore, even when the delay times of the constituents of the circuit are varied due to variations in the device parameters or the temperature and the timing of the clock input is deviated, the timing of the clock input is adjusted by the variable delay circuit, whereby the D flip-flop in the stage having the variable delay circuit is normally operated.
  • the above-described multiplexers further include means for monitoring data output from the data output terminal of the D flip-flop or the multiplexer block in the final n-th stage; and means for controlling the delay time of the variable delay circuit with a control signal according to the result of the monitoring. Therefore, even when the delay times of the constituents of the circuit are varied due to variations in the device parameters or the temperature and the timing of the data input or the clock input is deviated, the deviation of the timing is monitored and the delay time of the variable delay circuit is controlled according to the result of the monitoring so that the deviation of the timing is prevented, thereby providing a normally operating multiplexer.
  • the variable delay circuit comprises a plurality of lines comprising buffers in different numbers and providing different delay times, the lines being arranged in parallel with each other; and a selector for selecting one of the lines in response to the control signal supplied from the delay time controlling means, the selector being connected to the lines and the delay time controlling means. Therefore, the delay time of the variable delay circuit is easily controlled by switching the lines using the selector, thereby providing a multiplexer that is easily adjusted to the normal operating state even when the delay times of the constituents of the circuit are varied.
  • the variable delay circuit comprises at least a variable delay buffer that is connected to the delay time controlling means and varies the delay time in response to the control signal supplied from the delay time controlling means. Therefore, the delay time of the variable delay circuit is easily controlled by varying the delay time of the variable delay buffer with the control signal, thereby providing a multiplexer that is easily adjusted to the normal operating state even when the delay times of the constituents of the circuit are varied.
  • variable delay buffer comprises a source follower buffer including a current supply transistor, and the delay time is controlled by controlling a gate voltage of the current supply transistor with the control signal supplied from the delay time controlling means.
  • the demultiplexer further includes a variable delay circuit connected to the data input terminal of each demultiplexer block in any of the second to the n-th stages, and the variable delay circuit delays the data input by a variable delay time. Therefore, even when the delay times of the constituents of the circuit are varied due to variations in the device parameters or the temperature and the timing of the data input is deviated, the timing of the data input is adjusted by the variable delay circuit, whereby the D flip-flop in the stage having the variable delay circuit is normally operated.
  • the demultiplexer further includes a variable delay circuit connected to the clock input terminal of each demultiplexer block in any of the second to the n-th stages or to the clock input terminal of the D flip-flop in the first stage, and the variable delay circuit delays the clock input by a variable delay time. Therefore, even when the delay times of the constituents of the circuit are varied due to variations in the device parameters or the temperature and the timing of the clock input is deviated, the timing of the clock input is adjusted by the variable delay circuit, whereby the D flip-flop in the stage having the variable delay circuit is normally operated.
  • the demultiplexer further includes a variable delay circuit connected to the data input terminal of each demultiplexer block in any of the second to the n-th stages, and the variable delay circuit delays the data input by a variable delay time. Therefore, even when the delay times of the constituents of the circuit are varied due to variations in the device parameters or the temperature and the timing of the data input is deviated, the timing of the data input is adjusted by the variable delay circuit, whereby the D flip-flop in the stage having the variable delay circuit is normally operated.
  • the demultiplexer further includes a variable delay circuit connected to the clock input terminal of each demultiplexer block in any of the second to the n-th stages or to the clock input terminal of the D flip-flop in the first stage, and the variable delay circuit delays the clock input by a variable delay time. Therefore, even when the delay times of the constituents of the circuit are varied due to variations in the device parameters or the temperature and the timing of the clock input is deviated, the timing of the clock input is adjusted by the variable delay circuit, whereby the D flip-flop in the stage having the variable delay circuit is normally operated.
  • the above-described demultiplexers further include means for monitoring data output from the data output terminals of the demultiplexer blocks in the final n-th stage; and means for controlling the delay time of the variable delay circuit with a control signal according to the result of the monitoring. Therefore, even when the delay times of the constituents of the circuit are varied due to variations in the device parameters or the temperature and the timing of the data input or the clock input is deviated, the deviation of the timing is monitored and the delay time of the variable delay circuit is controlled according to the result of the monitoring so that the deviation of the timing is prevented, thereby providing a normally operating demultiplexer.
  • the variable delay circuit comprises a plurality of lines comprising buffers in different numbers and providing different delay times, the lines being arranged in parallel with each other; and a selector for selecting one of the lines in response to the control signal supplied from the delay time controlling means, the selector being connected to the lines and the delay time controlling means. Therefore, the delay time of the variable delay circuit is easily controlled by switching the lines using the selector, thereby providing a demultiplexer that is easily adjusted to the normal operating state even when the delay times of the constituents of the circuit are varied.
  • the variable delay circuit comprises at least a variable delay buffer that is connected to the delay time controlling means and varies the delay time in response to the control signal supplied from the delay time controlling means. Therefore, the delay time of the variable delay circuit is easily controlled by varying the delay time of the variable delay buffer with the control signal, thereby providing a demultiplexer that is easily adjusted to the normal operating state even when the delay times of the constituents of the circuit are varied.
  • variable delay buffer comprises a source follower buffer including a current supply transistor, and the delay time is controlled by controlling a gate voltage of the current supply transistor with the control signal supplied from the delay time controlling means.
  • Figure 1 is a block diagram illustrating a circuit structure of a multiplexer in accordance with a first embodiment of the present invention.
  • Figures 2(a)-2(l) are diagrams illustrating a timing chart of the multiplexer according to the first embodiment of the invention.
  • Figure 3 is a block diagram illustrating a circuit structure of a multiplexer in accordance with a second embodiment of the present invention.
  • Figure 4 is a block diagram illustrating a circuit structure of a demultiplexer in accordance with a fourth embodiment of the present invention.
  • Figures 5(a)-5(l) are diagrams illustrating a timing chart of the demultiplexer according to the fourth embodiment of the present invention.
  • Figure 6 is a block diagram illustrating a circuit structure of a demultiplexer in accordance with a fifth embodiment of the present invention.
  • Figure 7 is a block diagram illustrating a variable delay circuit included in the multiplexer according to the first embodiment of the invention.
  • Figure 8 is a block diagram illustrating a variable delay circuit included in the multiplexer in accordance with a seventh embodiment of the invention.
  • Figure 9 is a block diagram illustrating a circuit structure of a variable delay buffer included in the variable delay circuit according to the seventh embodiment of the invention.
  • Figure 10 is a block diagram illustrating a circuit structure of a multiplexer in accordance with a third embodiment of the present invention.
  • Figure 11 is a block diagram illustrating a circuit structure of a demultiplexer in accordance with a sixth embodiment of the present invention.
  • Figure 12 is a block diagram illustrating a circuit structure of a 4:1 multiplexer according to the prior art.
  • Figure 13 is a block diagram illustrating a circuit structure of a 2:1 multiplexer block included in the prior art multiplexer.
  • Figures 14(a)-14(k) are diagrams illustrating a timing chart of the prior art multiplexer.
  • Figure 15 is a block diagram illustrating a circuit structure of a 1:4 demultiplexer according to the prior art.
  • Figure 16 is a block diagram illustrating a circuit structure of a 1:2 demultiplexer block included in the prior art demultiplexer.
  • Figures 17(a)-17(k) are diagrams illustrating a timing chart of the prior art demultiplexer.
  • Figures 18(a)-18(c) are diagrams illustrating a timing chart of a clock input and a data input in a D flip-flop of the prior art multiplexer.
  • Figure 19 is a block diagram illustrating a circuit structure of the prior art multiplexer.
  • Figure 20 is a block diagram illustrating a circuit structure of the prior art demultiplexer.
  • FIG. 1 is a block diagram illustrating a circuit structure of a multiplexer in accordance with a first embodiment of the present invention.
  • Reference numeral 100 designates a multiplexer according to this first embodiment of the invention.
  • the multiplexer 100 comprises 2:1 MUX blocks 1, 2, and 3, a variable delay circuit 10, a D flip-flop 4, 1/2 frequency dividers 5 and 5b, a monitor 20, and a control circuit 30. More specifically, the 2:1 MUX block 1 receives parallel data 3 and 1 and outputs parallel data ODD.
  • the 2:1 MUX block 2 receives parallel data 2 and 0 and outputs parallel data EVEN.
  • the 2:1 MUX block 3 receives the parallel data ODD and EVEN output from the 2:1 MUX blocks 1 and 2, respectively, and outputs serial data SIG 1 .
  • the variable delay circuit 10 receives the serial data SIG 1 output from the 2:1 MUX block 3, delays the serial data SIG 1 by a variable delay time, and outputs serial data SIG 2 .
  • control circuit 30 is connected to the variable delay circuit 10 and controls the variable delay circuit 10 with a control signal that determines the delay time.
  • the D flip-flop 4 receives the serial data SIG 2 output from the variable delay circuit 10.
  • the monitor 20 is connected to an output terminal of the D flip-flop 4.
  • the monitor 20 monitors the serial data output from the D flip-flop 4 and compares the serial data with an expected value that is input to the monitor 20 in advance.
  • a measuring instrument or a combination of a measuring instrument and a computer is employed as the monitor 20.
  • a high-speed clock CLK supplied from the outside of the multiplexer is input to the D flip-flop 4 and to the 1/2 frequency divider 5.
  • the 1/2 frequency divider 5 divides the frequency of the high-speed clock CLK and produces a clock 1/2CLK.
  • the clock 1/2CLK is input to the 2:1 MUX block 3 and to the 1/2 frequency divider 5b.
  • the 1/2 frequency divider 5b divides the frequency of the clock 1/2CLK and produces a clock 1/4CLK.
  • the clock 1/4CLK is input to the 2:1 MUX blocks 1 and 2.
  • the multiplexer according to the first embodiment further includes a monitor for monitoring an output from the D flip-flop 4 in the final output stage, a variable delay circuit connected to the data input terminal of the D flip-flop 4, and a control circuit for controlling the variable delay circuit, whereby the variable delay circuit is controlled by the control circuit according to the result of the monitoring to adjust the delay time at variable values.
  • the multiplexer 100 is a 4:1 multiplexer
  • the monitor 20, the variable delay circuit 10, and the control circuit 30 may be applied to a multiplexer including n stages of m:1 MUX blocks as shown in figure 19 with the same operating principle and the same effects.
  • Figure 7 is a block diagram illustrating a structure of the variable delay circuit 10 according to this first embodiment of the invention.
  • reference numeral 23 designates an input terminal of the variable delay circuit 10 to which the serial data SIG 1 is applied.
  • Reference numeral 22 designates a 2 r :1 selector that has 2 r data input terminals and selects one of 2 r data inputs.
  • One of the 2 r input terminals of the selector 22 is connected to the input terminal 23 of the variable delay circuit 10.
  • the selector 22 is controlled by control signals L 1 to L r which are input to control signal input terminals 24.
  • the data SIG 2 selected in the selector 22 is output from the data output terminal 25.
  • a plurality of lines 210 in which one, two, four, ..., and 2 r-1 buffers 21 are respectively connected in series (hereinafter referred to as buffer lines) are connected between the input terminal 23 and the (2 r -1) input terminals of the selector 22.
  • the delay times of the respective buffer lines 210 are varied by changing the number of the buffers 21 included in the buffer lines 210.
  • the delay times of the respective buffer lines 210 can be varied by changing the kind, fan-out number, fan-in number, wiring length, or I/O method of the buffers included in the respective buffer lines.
  • Figures 2(a)-2(l) are diagrams illustrating a timing chart of the multiplexer 100 according to this first embodiment of the invention. More specifically, figures 2(a)-2(d) show the timings of the parallel data 3, 2, 1, and 0 input to the multiplexer 100, respectively, figures 2(e) and 2(h) show the timings of the clocks 1/4CLK and 1/2CLK, respectively, figures 2(f) and 2(g) show the timings of the parallel data ODD and EVEN, respectively, figure 2(i) shows the timing of the serial data SIG 1 , figure 2(k) shows the timing of the high-speed clock CLK, figure 2(j) shows the timing of the serial data SIG 2 output from the variable delay circuit 10, and figure 2(l) shows the timing of the serial data output from the D flip-flop 4.
  • the same reference characters as those shown in figures 14(a)-14(k) denote the same or corresponding elements.
  • Reference character ⁇ T denotes a delay time in the variable delay circuit 10.
  • the input terminal 23 to which the data SIG 1 is input is connected to the selector 22 through the buffer lines 210 which are arranged in parallel and include the buffers 21 in different numbers.
  • the selector 22 selects one of the buffer lines 210 in response to a control signal that is supplied from the control circuit 30 through the control signal input terminal 24 to the selector 22. Thereby, the number of the buffers 21 through which the input data SIG 1 travels is changed, and a desired delay time is obtained.
  • a high-speed clock CLK is divided using the frequency dividers 5 and 5b to produce a clock 1/2CLK having a frequency equivalent to 1/2 of the frequency of the high-speed clock CLK and a clock 1/4CLK having a frequency equivalent to 1/4 of the frequency of the high-speed clock CLK.
  • first stage 2:1 MUX blocks 1 and 2 using the clock 1/4CLK, four bit parallel data 3, 2, 1, and 0 are converted into two bit parallel data ODD and EVEN.
  • the second stage 2:1 MUX block 3 using the clock 1/2CLK, the two bit parallel data ODD and EVEN are converted into serial data SIG 1 .
  • serial data SIG 1 is delayed by ⁇ T by the variable delay circuit 10 to produce serial data SIG 2 .
  • the serial data SIG 2 is synchronized with the highspeed clock CLK that is directly input from the outside of the multiplexer 100, whereby the serial data SIG 2 is delayed by ⁇ Te.
  • the serial data output obtained by the D flip-flop 4 is output from the multiplexer 100.
  • known parallel data 3, 2, 1, 0 for test are input to a multiplexer identical to the multiplexer 100 and being kept at a temperature proximate to an actual operating temperature, and an output from the final output stage is monitored using the monitor 20.
  • the delay time ⁇ T of the data SIG 2 in the variable delay circuit 10 is adjusted in response to a control signal supplied from the control circuit 30 so that the monitored value becomes equivalent to an expected value for the serial data output obtained from the parallel data for test.
  • the delay times of the constituents of the circuit are unfavorably varied due to variations in the process parameters and the temperature, so that the timing of the high-speed clock CLK and the serial data SIG 1 to be input to the D flip-flop 4 is deviated from the design timing, whereby the D flip-flop 4 is not normally operated.
  • the delay time of the variable delay circuit 10 is adjusted in advance. Therefore, even when the timing of the high-speed clock CLK and the serial data SIG 1 is deviated from the design timing and the data changing point of the serial data SIG 1 is placed between the setup time and the hold time of the D flip-flop 4, since the timing of the serial data SIG 1 is adjusted in the variable delay circuit 10 and the timing-adjusted serial data SIG 2 is input to the D flip-flop 4, the data changing point of the data input SIG 2 is prevented from being placed between the setup time and the hold time of the D flip-flop 4, whereby the deviation of the timing in the final output stage, i.e., the D flip-flop 4, is avoided. As a result, the multiplexer 100 is normally operated.
  • control of the output signal from the control circuit according to the result of the monitoring may be manually performed.
  • control of the output signal may be automated conjointly with the result of the monitoring in advance.
  • variable delay circuit 10 is connected to the data input terminal of the D flip-flop 4 for timing control, and the delay time of the variable delay circuit 10 is controlled by the control circuit in response to the output of the D flip-flop 4 that is monitored by the monitor 20, whereby the timing of the serial data input to the D flip-flop is adjusted. Therefore, even when the delay times of the constituents of the circuit are varied due to variations in the device parameters and the temperature, it is possible to normally operate the D flip-flop 4 using the timing-adjusted serial data, whereby the multiplexer operates normally.
  • variable delay circuit 10 since the variable delay circuit 10 includes the selector 22 that selects one of the buffer lines 210 comprising the buffers 21 in different numbers and having different delay times, the delay time of the variable delay circuit 10 is easily varied by switching the buffer lines 210 of the selector 22, whereby a normally operating multiplexer is provided even when the delay times of the constituents of the circuit are varied.
  • variable delay circuit 10 is connected to the data input terminal of the D flip-flop 4 in the final output stage.
  • variable delay circuit is connected to the data input terminals of the MUX blocks constituting any of other output stages, except the first output stage.
  • the variable delay circuit must be connected to the data input terminals of all of the D flip-flops constituting the output stage.
  • FIG 3 is a block diagram illustrating a circuit structure of a multiplexer in accordance with a second embodiment of the present invention.
  • Reference numeral 101 designates a multiplexer according to this second embodiment of the invention.
  • the multiplexer 101 comprises 2:1 MUX blocks 1, 2, and 3, a variable delay circuit 10, a D flip-flop 4, 1/2 frequency dividers 5 and 5b, a monitor 20, and a control circuit 30. More specifically, the 2:1 MUX block 1 receives parallel data 3 and 1 and outputs parallel data ODD.
  • the 2:1 MUX block 2 receives parallel data 2 and 0 and outputs parallel data EVEN.
  • the 2:1 MUX block 3 receives the parallel data ODD and EVEN output from the 2:1 MUX blocks 1 and 2, respectively, and outputs serial data SIG 1 .
  • the D flip-flop 4 receives the serial data SIG 1 output from the 2:1 MUX block 3.
  • the monitor 20 is connected to an output terminal of the D flip-flop 4.
  • the monitor 20 monitors the serial data output from the D flip-flop 4 and compares the serial data with an expected value that is input to the monitor 20 in advance.
  • a measuring instrument or a combination of a measuring instrument and a computer is employed as the monitor 20.
  • the variable delay circuit 10 receives a high-speed clock CLK supplied from the outside of the multiplexer and delays the high-speed clock CLK.
  • the variable delay circuit 10 controls the delay time of the input signal at variable values.
  • the control circuit 30 is connected to the variable delay circuit 10 and controls the variable delay circuit 10 with a control signal that determines the delay time.
  • the 1/2 frequency divider 5 divides the frequency of the high-speed clock CLK and produces a clock 1/2CLK.
  • the clock 1/2CLK is input to the 2:1 MUX block 3 and the 1/2 frequency divider 5b.
  • the 1/2 frequency divider 5b divides the frequency of the clock 1/2CLK and produces a clock 1/4CLK.
  • the clock 1/4CLK is input to the 2:1 MUX blocks 1 and 2.
  • variable delay circuit 10 is connected to the data input terminal of the D flip-flop 4 in the final output stage, in this second embodiment it is connected to the clock input terminal of the D flip-flop 4, whereby the clock signal input to the D flip-flop 4 is delayed at variable values.
  • variable delay circuit 10 is connected to the clock input terminal of the D flip-flop 4 in the final output stage.
  • variable delay circuit is connected to the frequency-divided clock input terminals of the MUX blocks constituting any of other output stages.
  • the variable delay circuit must be connected to the frequency-divided clock input terminals of all of the D flip-flops constituting the output stage.
  • a control signal supplied from the control circuit 30 is input to the variable delay circuit 10 to adjust the timing of the data input SIG 1 and produce a data input SIG 2 , and the data input SIG 2 is input to the D flip-flop 4, whereby the D flip-flop 4 is normally operated.
  • the high-speed clock CLK is divided by the frequency dividers 5 and 5b to produce a clock 1/2CLK having a frequency equivalent to 1/2 of the frequency of the high-speed clock CLK and a clock 1/4CLK having a frequency equivalent to 1/4 of the frequency of the high-speed clock CLK.
  • first stage 2:1 MUX blocks 1 and 2 using the clock 1/4CLK, four bit parallel data 3, 2, 1, and 0 are converted into two bit parallel data ODD and EVEN.
  • the second stage 2:1 MUX block 3 using the clock 1/2CLK, the two bit parallel data ODD and EVEN are converted into serial data SIG 1 . Then, this serial data SIG 1 is input to the D flip-flop 4 in the final output stage.
  • known parallel data 3, 2, 1, 0 for test are input to a multiplexer identical to the multiplexer 101 according to the second embodiment and being kept at a temperature proximate to an actual operating temperature, and an output from the final output stage is monitored using the monitor 20.
  • the delay time ⁇ T of the high-speed clock CLK in the variable delay circuit 10 is adjusted in response to a control signal supplied from the control circuit 30 so that the monitored value becomes the same as an expected value for the serial data output obtained from the parallel data for test.
  • the delay times of the constituents of the circuit are unfavorably varied due to variations in the process parameters and the temperature, so that the timing of the high-speed clock CLK and the data input SIG 1 to be input to the D flip-flop 4 is deviated from the design timing, whereby the D flip-flop 4 is not normally operated.
  • the delay time of the variable delay circuit 10 is adjusted in advance. Therefore, even when the timing of the high-speed clock CLK and the data input SIG 1 to be input to the D flip-flop 4 is deviated from the design timing and the data changing point of the data input SIG 1 is located between the setup time and the hold time of the D flip-flop 4, since the deviation of the timing is adjusted by delaying the high-speed clock CLK in the variable delay circuit 10, the changing point of the output from the D flip-flop 4 is prevented from being placed between the setup time and the hold time of the D flip-flop 4. As a result, the deviation of the timing in the final output stage, i.e., the D flip-flop 4, is avoided, whereby the multiplexer 101 is normally operated.
  • control of the output signal using the control circuit according to the result of the monitoring may be manually performed.
  • control of the output signal may be automated conjointly with the result of the monitoring in advance.
  • variable delay circuit 10 is connected to the clock input terminal of the D flip-flop 4 in the final output stage, and the delay time of the variable delay circuit 10 is controlled to adjust the timing of the clock input to the D flip-flop 4. Therefore, even when the delay times of the constituents of the circuit are varied due to variations in the device parameters of the temperature and the timing of the data input is deviated from the timing of the clock input or the divided clock input, since the delay time of the variable delay circuit is adjusted by the control circuit according to the result of the monitoring so that the deviation is prevented, the D flip-flop provided with the variable delay circuit is normally operated.
  • variable delay circuit 10 includes the selector 22 that selects one of the buffer lines 210 comprising the buffers 21 in different numbers and having different delay times, the delay time of the variable delay circuit 10 is easily varied by switching the buffer lines 210 in the selector 22. Therefore, a normally operating multiplexer is realized even when the delay times of the constituents of the circuit are varied.
  • FIG. 10 is a block diagram illustrating a circuit structure of a multiplexer in accordance with a third embodiment of the present invention.
  • Reference numeral 102 designates a multiplexer according to the third embodiment of the invention.
  • the multiplexer 102 comprises 2:1 MUX blocks 1, 2, and 3, variable delay circuits 10a and 10b, a 1/2 frequency divider 5b, a monitor 20, and a control circuit 30. More specifically, the 2:1 MUX block 1 receives parallel data 3 and 1 and outputs serial data.
  • the 2:1 MUX block 2 receives parallel data 2 and 0 and outputs serial data.
  • the variable delay circuits 10a and 10b receive the serial data output from the 2:1 MUX blocks 1 and 2 and delay the serial data, respectively. These variable delay circuits 10a and 10b are identical to the variable delay circuit 10 according to the first and second embodiments.
  • control circuit 30 is connected to the variable delay circuits 10a and 10b and controls the variable delay circuits 10a and 10b with a control signal that determines the delay time.
  • the variable delay circuits 10a and 10b output data ODD and data EVEN, respectively, and these data ODD and EVEN are input to the 2:1 MUX block 3.
  • the monitor 20 is connected to an output terminal of the 2:1 MUX block 3.
  • the monitor 20 monitors the serial data output from the 2:1 MUX block 3 and compares the serial data with an expected value that is input to the monitor 20 in advance.
  • a measuring instrument or a combination of a measuring instrument and a computer is employed as the monitor 20.
  • the 1/2 frequency divider 5 divides the frequency of the high-speed clock CLK supplied from the outside of the multiplexer and produces a clock 1/2CLK.
  • the clock 1/2CLK is input to the 2:1 MUX blocks 1 and 2.
  • a variable delay circuit is included in a multiplexer in which serial data is synchronized with a clock input in a D flip-flop at the final output stage.
  • variable delay circuits are connected to the data input terminals of the m:1 MUX block in the final output stage, i.e., the n-th stage.
  • variable delay circuits 10a and 10b are connected to the data input terminals of the MUX block 3 in the final output stage.
  • variable delay circuits are connected to the clock input terminals or the frequency-divided clock input terminals of the MUX blocks constituting any output stage.
  • the variable delay circuit must be connected to the clock input terminals or the frequency-divided clock input terminals of all of the D flip-flops constituting the output stage.
  • variable delay circuits are connected to the data input terminals of the MUX blocks constituting any of other output stages, except the first output stage, is also within the scope of the invention. In this case, the variable delay circuits must be connected to the data input terminals of all of the D flip-flops constituting the output stage.
  • variable delay circuit 10 is included in a multiplexer in which the serial data SIG 1 are synchronized with the clock CLK by the D flip-flop 4 in the final output stage
  • the final output stage is constituted by the 2:1 MUX block 3 and the variable delay circuits 10a and 10b are connected to the data input terminals of the 2:1 MUX blocks 3 in the final output stage.
  • the high-speed clock CLK is divided by the frequency divider 5b to produce a clock 1/2CLK having a frequency equivalent to 1/2 of the frequency of the high-speed clock CLK.
  • the first stage 2:1 MUX blocks 1 and 2 using the clock 1/2CLK, four bit parallel data 3, 2, 1, and 0 are converted into two bit parallel data. These two bit parallel data are delayed in the variable delay circuits 10a and 10b, respectively, producing two bit parallel data ODD and EVEN. These parallel data ODD and EVEN are converted into serial data by the 2:1 MUX block 3 and this serial data is output from the multiplexer 102.
  • known parallel data 3, 2, 1, and 0 for test are input to a multiplexer identical to the multiplexer 102 according to the third embodiment and being kept at a temperature proximate to an actual operating temperature, and an output from the final output stage is monitored using the monitor 20.
  • the delay times of the output data from the 2:1 MUX blocks 1 and 2 in the variable delay circuits 10a and 10b are controlled in response to a control signal output from the control circuit 30 so that the monitored value becomes equivalent to an expected value for the serial data output obtained from the parallel data for test.
  • the delay times of the constituents of the circuit are unfavorably varied due to variations in the process parameters and the temperature, so that the timing of the high-speed clock CLK and the parallel data ODD and EVEN to be input to the 2:1 MUX block 3 is unfavorably deviated from the design timing.
  • the delay time of the variable delay circuits 10a and 10b is adjusted in advance. Therefore, even when the timing of the high-speed clock CLK and the parallel data ODD and EVEN to be input to the m:1 MUX block 3 is deviated from the design timing and the changing point of the parallel data ODD and EVEN is placed in the switching time of the 2:1 MUX block 3, since the deviation of the timing of the parallel data is adjusted by delaying the parallel data in the variable delay circuits 10a and 10b, the changing point of the parallel data ODD and EVEN is prevented from being placed in the switching time of the 2:1 MUX block 3. As a result, the deviation of the timing in the final output stage, i.e., the 2:1 MUX block 3, is avoided, whereby the multiplexer 102 is normally operated.
  • control of the output signal from the control circuit according to the result of the monitoring may be manually performed.
  • control of the output signal may be automated conjointly with the result of the monitoring in advance.
  • variable delay circuits 10a and 10b are connected to the data input terminals of the 2:1 MUX block 3 in the final output stage, and the delay time is controlled to adjust the timing of the data input to the 2:1 MUX block 3. Therefore, as in the first embodiment of the invention, even when the delay times of the constituents of the circuit are varied due to variations in the device parameters and the temperature and the timing of the data input, clock input, or frequency-divided clock input is deviated, since the delay time of the variable delay circuit is adjusted in advance by the control circuit according to the result of the monitoring so that the deviation is adjusted, the 2:1 MUX block provided with the variable delay circuit is normally operated.
  • variable delay circuit 10a (10b) since the variable delay circuit 10a (10b) includes the selector 22 that selects one of the buffer lines 210 comprising the buffers 21 in different numbers and having different delay times, the delay time of the variable delay circuit is easily varied by switching the buffer lines 210 of the selector 22, whereby a normally operating multiplexer is provided even when the delay times of the constituents of the circuit are varied.
  • FIG. 4 is a block diagram illustrating a circuit structure of a demultiplexer in accordance with a fourth embodiment of the present invention.
  • Reference numeral 300 designates a demultiplexer.
  • the demultiplexer 300 comprises a D flip-flop 14, a variable delay circuit 10, a control circuit 30, 1:2 DEMUX blocks 13, 11, and 12, a monitor 20, and 1/2 frequency dividers 15 and 15b. More specifically, the D flip-flop 14 receives a serial data input and outputs serial data SIG 1 .
  • the variable delay circuit 10 that can control delay time of an input signal at variable values receives the serial data SIG 1 output from the D flip-flop 14 and outputs serial data SIG 2 .
  • the control circuit 30 is connected to the variable delay circuit 10 and controls the variable delay circuit 10 with a control signal that determines the delay time.
  • the 1:2 DEMUX block 13 receives the serial data SIG 2 output from the variable delay circuit 10 and converts the serial data SIG 2 into two bit parallel data ODD and EVEN.
  • the 1:2 DEMUX blocks 11 and 12 receive the two bit parallel data ODD and EVEN, respectively, and convert the data ODD and EVEN into four bit parallel data 3, 1, 2, and 0.
  • the monitor 20 monitors the outputs from the 1:2 DEMUX blocks 11 and 12 in the final output stage and compares the monitor outputs with expected values which are input in advance.
  • a high-speed clock CLK supplied from the outside of the demultiplexer is input to the D flip-flop 14 and to the 1/2 frequency divider 15.
  • the 1/2 frequency divider 15 divides the frequency of the high-speed clock CLK and produces a clock 1/2CLK.
  • the clock 1/2CLK is input to the 1:2 DEMUX block 13 and to the 1/2 frequency divider 15b.
  • the 1/2 frequency divider 15b divides the frequency of the clock 1/2CLK and produces a clock 1/4CLK.
  • the 1:2 DEMUX blocks 11 and 12 receive the clock 1/4CLK.
  • the demultiplexer according to the fourth embodiment further includes a monitor 20 for monitoring outputs from the 1:m DEMUX blocks 13a in the final output stage, a variable delay circuit 10 connected between the data output terminal of the D flip-flop 14 in the first stage and the data input terminal of the 1:m DEMUX block 13a in the second stage, and a control circuit 30 for controlling the variable delay circuit 10, whereby the variable delay circuit 10 is controlled in response to a control signal that is output from the control circuit 30 according to the result of the monitoring to adjust the delay time at variable values.
  • the demultiplexer 300 is a 1:4 demultiplexer
  • the monitor 20, the variable delay circuit 10, and the control circuit 30 may be applied to a demultiplexer including n stages of 1:m DEMUX blocks as shown in figure 20 with the same operating principle and the same effects.
  • Figures 5(a)-5(l) are diagrams illustrating a timing chart of the demultiplexer 300 in accordance with a fourth embodiment of the invention. More specifically, figures 5(i)-5(l) show the timings of the parallel data 3, 2, 1, and 0 output from the demultiplexer, respectively, figures 5(b), 5(e), and 5(h) show the timings of the clocks CLK, 1/2CLK, and 1/4CLK, respectively, figures 5(f) and 5(g) show the timings of the parallel data ODD and EVEN, respectively, figure 5(c) shows the timing of the serial data SIG 1 , figure 5(d) shows the timing of the serial data SIG 2 , and figure 5(a) shows the timing of the serial data input to the demultiplexer.
  • the same reference characters as show in figures 17(a)-17(k) denote the same or corresponding elements.
  • Reference character ⁇ T denotes the delay time in the variable delay circuit 10.
  • the frequency dividers 15 and 15b receive the high-speed clock CLK and produce a clock 1/2CLK having a frequency equivalent to 1/2 of the frequency of the high-speed clock CLK and a clock 1/4CLK having a frequency equivalent to 1/4 of the frequency of the high-speed clock CLK, respectively.
  • the D flip-flop 14 receives the serial data input to the demultiplexer 300, synchronizes the serial data with the high-speed clock CLK, and outputs serial data SIG 1 .
  • the serial data SIG 1 is input to the variable delay circuit 10.
  • the variable delay circuit 10 delays the serial data SIG 1 by ⁇ T and outputs serial data SIG 2 .
  • serial data SIG 2 is input to the 1:2 DEMUX block 13 in the next stage and converted into two bit parallel data ODD and EVEN.
  • the two bit parallel data ODD and EVEN are input to the 1:2 DEMUX blocks 11 and 12 in the final stage, respectively, and converted into four bit parallel data 3, 1, 2, and 0. Finally, the four bit parallel data are output from the demultiplexer 300.
  • demultiplexer 300 known serial data for test is input to a demultiplexer identical to the demultiplexer 300 according to this fourth embodiment and being kept at a temperature proximate to an actual operating temperature, and the outputs from the final output stage are monitored using the monitor 20.
  • the delay time ⁇ T of the data in the variable delay circuit 10 is controlled in response to a control signal supplied from the control circuit 30 so that the monitored value becomes equivalent to an expected value for the data output obtained from the serial data for test.
  • the delay times of the constituents of the circuit are unfavorably varied due to variations in the process parameters and the temperature, so that the timing of the serial data SIG 1 and the clock 1/2CLK to be input to the 1:2 DEMUX block 13 is deviated from the design timing, whereby the D flip-flops 7 and 8 constituting the 1:2 DEMUX block 13 are not operated normally.
  • the delay time of the variable delay circuit 10 is adjusted in advance. Therefore, even when the timing of the clock 1/2CLK and the data input SIG 1 is deviated from the design timing and the changing point of the data input SIG 1 is located between the setup time and the hold time of the D flip-flops 7 and 8 constituting the 1:2 DEMUX block 13, since the deviation of the timing of the serial data SIG 1 is adjusted by the variable delay circuit 10 and the timing-adjusted serial data SIG 2 is input to the 1:2 DEMUX block 13, the changing point of the data input SIG 2 is prevented from being located between the setup time and the hold time of the D flip-flops 7 and 8, whereby the deviation of the timing of the data input SIG 2 and the clock 1/2CLK to be input to the 1:2 DEMUX block 13 is avoided. As a result, the demultiplexer 300 is operated normally.
  • the control of the output signal from the control circuit according to the result of the monitoring may be manually performed. Alternatively, the control of the output signal may be automated conjointly with
  • the first stage includes the D flip-flop for timing control that synchronizes the serial input with the clock input CLK
  • each of the m i-2 DEMUX blocks in the i-th stage is connected to the prior stage so that one of the parallel data output from the prior stage is input to the DEMUX block as serial data.
  • variable delay circuit that can delay the data input, the clock input, or the frequency-divided clock input by a variable delay time is connected to the data input terminal of one of the second to n-th stages, the frequency-divided clock input terminal of one of the second to n-th stages, or the clock input terminal of the first stage. Since the timing of the data input, the clock input, or the frequency-divided clock input is adjusted by the variable delay circuit, even when the timing of the above-described input is deviated due to variations in the delay time of the constituents of the circuit, the timing is adjusted by the variable delay circuit, whereby the D flip-flops in the stage with the variable delay circuit are normally operated.
  • variable delay circuit 10 is connected to the data input terminal of the 1:2 DEMUX block 13 in the second stage, and the outputs from the DEMUX blocks 11 and 12 in the final stage are monitored by the monitor 20.
  • the delay time in the variable delay circuit 10 is adjusted by the control circuit 30 according to the monitored values, whereby the timing of the serial data SIG 1 output from the D flip-flop 14 is adjusted in the variable delay circuit 10. Therefore, even when the delay times of the constituents of the circuit are varied due to variations in the device parameters or the temperature, the D flip-flop constituting the second stage 1:2 DEMUX block 13 is normally operated by the timing-adjusted serial data.
  • variable delay circuit 10 includes the selector 22 that selects one of the buffer lines 210 comprising the buffers 21 in different numbers and having different delay times, the delay time of the variable delay circuit 10 is easily varied by switching the buffer lines 210 of the selector 22. Therefore, a demultiplexer that is easily adjusted to the normal operating state is provided even when the delay times of the constituents of the circuit are varied.
  • variable delay circuit 10 is connected to the data input terminal of the 1:2 DEMUX block 13 in the second output stage.
  • variable delay circuits are connected to the data input terminals of the DEMUX blocks constituting any of other output stages, except the first stage.
  • the variable delay circuits must be connected to the data input terminals of all of the D flip-flops constituting the output stage.
  • FIG. 6 is a block diagram illustrating a circuit structure of a demultiplexer in accordance with a fifth embodiment of the present invention.
  • a demultiplexer 301 according to the fifth embodiment comprises a D flip-flop 14, a variable delay circuit 10, a control circuit 30, 1:2 DEMUX blocks 11, 12, and 13, a monitor 20, and 1/2 frequency dividers 15 and 15b. More specifically, the D flip-flop 14 receives a serial data input and outputs serial data SIG 1 .
  • the 1:2 DEMUX block 13 receives the serial data SIG 1 and converts the serial data SIG 1 into two bit parallel data ODD and EVEN.
  • the 1:2 DEMUX blocks 11 and 12 receive the two bit parallel data ODD and EVEN, respectively, and convert the data ODD and EVEN into four bit parallel data 3, 1, 2, and 0.
  • the monitor 20 monitors the outputs from the 1:2 DEMUX blocks 11 and 12 in the final output stage and compares the monitored outputs with expected values which are input in advance.
  • a high-speed clock CLK supplied from the outside of the demultiplexer is input to the D flip-flop 14 and to the 1/2 frequency divider 15.
  • the 1/2 frequency divider 15 divides the frequency of the high-speed clock CLK and produces a clock 1/2CLK.
  • the clock 1/2CLK is input to the variable delay circuit 10 that can control the delay time of the input signal at variable values.
  • the variable delay circuit 10 delays the clock 1/2CLK and outputs the clock to the 1:2 DEMUX block 13.
  • the control circuit 30 is connected to the variable delay circuit 10.
  • the control circuit 30 controls the variable delay circuit 10 with a control signal that determines the delay time.
  • the 1/2 frequency divider 15b divides the frequency of the clock 1/2CLK output from the 1/2 frequency divider 15 and produces a clock 1/4CLK.
  • the clock 1/4 CLK is input to the 1:2 DEMUX blocks 11 and 12.
  • the demultiplexer 301 according to this fifth embodiment is fundamentally identical to the demultiplexer 300 according to the fourth embodiment except that the variable delay circuit 10 is connected to the clock input terminal of the 1:m DEMUX block 13 in the second stage and the variable delay circuit 10 delays the frequency-divided clock input to the 1:m DEMUX block 13 at variable values.
  • the clock 1/2CLK is delayed, i.e., adjusted, by the variable delay circuit 10 and the adjusted clock is input to the clock input terminal of the 1:2 DEMUX block 13, whereby the timing of the clock 1/2CLK and the data input SIG 1 is approximated to the design timing.
  • the frequency dividers 15 and 15b produce a clock 1/2CLK having a frequency equivalent to 1/2 of the frequency of the high-speed clock CLK and a clock 1/4CLK having a frequency equivalent to 1/4 of the frequency of the high-speed clock CLK, respectively.
  • the D flip-flop 14 synchronizes the serial data input to the demultiplexer 301 with the high-speed clock CLK and outputs the serial data SIG 1 .
  • the serial data SIG 1 is input to the 1:2 DEMUX block 13 in the next stage.
  • the clock 1/2CLK is delayed by ⁇ T in the variable delay circuit 10 and the delayed 1/2CLK is input to the 1:2 DEMUX block 13.
  • the 1:2 DEMUX block 13 synchronizes the serial data SIG 1 with the delayed 1/2CLK and converts the serial data SIG 1 into two bit parallel data ODD and EVEN. Finally, the two bit parallel data ODD and EVEN are input to the 1:2 DEMUX blocks 11 and 12, respectively, and are converted into four bit parallel data 3, 2, 1, and 0.
  • known serial data for test is input to a demultiplexer identical to the demultiplexer 301 and being kept at a temperature proximate to an actual operating temperature, and the outputs from the final output stage are monitored using the monitor 20.
  • the delay time ⁇ T of the data in the variable delay circuit 10 is adjusted in response to a control signal supplied from the control circuit 30 so that the monitored value becomes equivalent to an expected value for the data output obtained from the serial data for test.
  • the delay times of the constituents of the circuit are unfavorably varied due to variations in the process parameters and the temperature, so that the timing of the serial data SIG 1 and the clock 1/2CLK to be input to the 1:2 DEMUX block 13 is unfavorably deviated from the design timing, whereby the D flip-flops 7 and 8 constituting the 1:2 DEMUX block 13 are not operated normally.
  • the delay time of the variable delay circuit 10 is adjusted in advance. Therefore, even when the timing of the clock 1/2CLK and the data input SIG 1 is deviated from the design timing and the changing point of the data input SIG 1 is located between the setup time and the hold time of the D flip-flops 7 and 8 constituting the 1:2 DEMUX block 13, since the deviation of the timing of the clock 1/2CLK is adjusted by the variable delay circuit 10 and the timing-adjusted clock 1/2CLK is input to the 1:2 DEMUX block 13, the changing point of the data input SIG 1 is prevented from being located between the setup time and the hold time of the D flip-flops 7 and 8, whereby the deviation of the timing of the data input SIG 1 and the clock 1/2CLK to be input to the 1:2 DEMUX block 13 in the second stage is avoided. As a result, the demultiplexer 301 is operated normally.
  • the control of the output signal from the control circuit according to the result of the monitoring may be manually performed. Alternatively, the control of the output signal may be automated
  • variable delay circuit 10 is connected to the clock input terminal of the 1:2 DEMUX block 13 in the second stage, and the outputs from the 1:2 DEMUX blocks 11 and 12 in the final output stage are monitored by the monitor 20.
  • the delay time of the variable delay circuit 10 is adjusted by the control circuit 30 according to the monitored values, whereby the timing of the clock 1/2CLK that is output from the 1/2 frequency divider 15 is adjusted in the variable delay circuit 10.
  • the D flip-flop constituting the 1:2 DEMUX block 13 in the second stage is normally operated by the timing-adjusted clock, resulting in a normally operated demultiplexer.
  • variable delay circuit 10 includes the selector 22 that selects one of the buffer lines 210 comprising the buffers 21 in different numbers and having different delay times, the delay time of the variable delay circuit 10 is easily varied by switching the buffer lines 210 of the selector 22. Therefore, a demultiplexer that is easily adjusted to the normal operating state is provided even when the delay times of the constituents of the circuit are varied.
  • variable delay circuit 10 is connected to the frequency-divided clock input terminal of the 1:2 DEMUX block 13 in the second output stage.
  • variable delay circuits are connected to the clock input terminals or the frequency-divided clock input terminals of the 1:2 DEMUX blocks constituting any of other output stages.
  • the variable delay circuits 10 must be connected to the clock input terminals or the frequency-divided-clock input terminals of all of the D flip-flops constituting the output stage.
  • FIG 11 is a block diagram illustrating a demultiplexer in accordance with a sixth embodiment of the present invention.
  • a demultiplexer 302 comprises variable delay circuits 10a and 10b, a control circuit 30, 1:2 DEMUX blocks 11, 12, and 13, a monitor 20, and a 1/2 frequency divider 15b. More specifically, the 1:2 DEMUX block 13 receives serial data and converts the serial data into two bit parallel data ODD and EVEN. The parallel data ODD and EVEN are input to the variable delay circuits 10a and 10b, respectively, and delayed in the variable delay circuits.
  • the variable delay circuits 10a and 10b are identical to the variable delay circuit 10 shown in figure 7 and are capable of controlling the delay time of the input signal at variable values.
  • the control circuit 30 is connected to the variable delay circuits 10a and 10b and controls the variable delay circuits 10a and 10b with a control signal that determines the delay time.
  • the 1:2 DEMUX blocks 11 and 12 receive the delayed parallel data ODD and EVEN, respectively, and convert the parallel data into four bit parallel data 3, 1, 2, and 0.
  • the monitor 20 monitors the outputs from the 1:2 DEMUX blocks 11 and 12 in the final output stage and compares the monitored values with expected values that are input to the monitor in advance.
  • the 1/2 frequency divider 15b receives a high-speed clock CLK and divides the frequency of the clock CLK to produce a clock 1/2CLK.
  • the clock 1/2CLK is input to the 1:2 DEMUX blocks 11 and 12.
  • the demultiplexer 302 according to this sixth embodiment is fundamentally identical to the demultiplexer 300 according to the fourth embodiment except that the demultiplexer 302 includes the 1:2 DEMUX block 13 in the first stage and the variable delay circuits 10a and 10b that are connected to the data input terminals of the 1:2 DEMUX blocks 11 and 12 in the second stage, respectively, whereas the demultiplexer 300 according to the fourth embodiment includes the D flip-flop 14 that synchronizes the serial data input with the high-speed clock CLK in the first stage and the variable delay circuit 10 that is connected to the data input terminal of the 1:2 DEMUX block 13 in the second stage. Also in this sixth embodiment, the data input to the second stage 1:2 DEMUX blocks 11 and 12 are delayed at variable values in the variable delay circuits 10a and 10b, respectively.
  • the 1:2 DEMUX block 13 in the first stage synchronizes the serial data input with the high-speed clock CLK and converts the serial data into two bit parallel data ODD and EVEN.
  • the two bit parallel data ODD and EVEN are delayed in the variable delay circuits 10a and 10b, and the delayed parallel data ODD and EVEN are input to the 1:2 DEMUX blocks 11 and 12 in the next stage, respectively. Since the clock 1/2CLK having a frequency equivalent to the half of the frequency of the high-speed clock CLK is input to the 1:2 DEMUX blocks 11 and 12 as a clock signal, the delayed parallel data ODD and EVEN are synchronized with the clock 1/2CLK and converted into four bit parallel data 3, 2, 1, and 0. Finally, the four bit parallel data are output from the demultiplexer 302.
  • known serial data for test is input to a demultiplexer identical to the demultiplexer 302 and being kept at a temperature proximate to an actual operating temperature, and the outputs from the final output stage are monitored using the monitor 20.
  • the delay time ⁇ T of the data in the variable delay circuits 10a and 10b is adjusted in response to a control signal supplied from the control circuit 30 so that the monitored value becomes equivalent to an expected value for the data output obtained from the serial data for test.
  • the delay times of the constituents of the circuit are unfavorably varied due to variations in the process parameters and the temperature, so that the timing of the serial data SIG 1 and the clock 1/2CLK to be input to the 1:2 DEMUX block 13 is unfavorably deviated from the design timing, whereby the D flip-flops 7 and 8 constituting the 1:2 DEMUX blocks 11 and 12 are not operated normally.
  • the delay time of the variable delay circuits 10a and 10b is adjusted in advance. Therefore, even when the timing of the two bit parallel data and the clock 1/2CLK to be input to the 1:2 DEMUX blocks 11 and 12 is deviated from the design timing and the changing point of the two bit data is located between the setup time and the hold time of the D flip-flops 7 and 8 constituting the 1:2 DEMUX blocks 11 and 12, since the variable delay circuits 10a and 10b delay the two bit parallel data so that the timing of the two bit parallel data and the clock 1/2CLK is adjusted and the delayed two bit data are input to the 1:2 DEMUX blocks 11 and 12, the changing point of the two bit data is prevented from being placed between the setup time and the hold time of the D flip-flops 7 and 8 in the 1:2 DEMUX blocks 11 and 12, whereby the deviation of the timing of the two bit data and the clock 1/2CLK to be input to the 1:2 DEMUX blocks 11 and 12 is avoided.
  • the demultiplexer 302 is normally operated.
  • the control of the output signal from the control circuit according to the result of the monitoring may be manually performed.
  • the control of the output signal may be automated conjointly with the result of the monitoring in advance.
  • variable delay circuits 10a and 10b are connected to the data input terminals of the 1:2 DEMUX blocks 11 and 12 in the second stage, respectively, and the outputs from the 1:2 DEMUX blocks 11 and 12 are monitored by the monitor 20.
  • the delay time of the variable delay circuits 10a and 10b is adjusted by the control circuit 30 according to the monitored values, whereby the timing of the two bit parallel data output from the 1:2 DEMUX block 13 is adjusted.
  • the D flip-flops constituting the second stage 1:2 DEMUX blocks 11 and 12 are normally operated by the timing-adjusted parallel data, resulting in a normally operated demultiplexer.
  • variable delay circuits 10a and 10b are connected to the data input terminals of the DEMUX blocks 11 and 12 constituting the second output stage.
  • variable delay circuits are connected to the clock input terminals or the frequency-divided clock input terminals of the DEMUX blocks constituting any output stage. In this case, the variable delay circuits must be connected to the clock input terminals or the frequency-divided clock input terminals of all of the D flip-flops constituting the output stage.
  • variable delay circuits are connected to the data input terminals of the DEMUX blocks constituting any of other output stages, except the first stage. In this case, the variable delay circuits must be connected to the data input terminals of all of the D flip-flops constituting the output stage.
  • variable delay circuit 10 includes the selector 22 that selects one of the buffer lines 210 comprising the buffers 21 in different numbers and having different delay times, the delay time of the variable delay circuit 10 is easily varied by switching the buffer lines 210 of the selector 22. Therefore, a demultiplexer that is easily adjusted to the normal operating state is provided even when the delay times of the constituents of the circuit are varied.
  • FIG. 8 is a block diagram illustrating a variable delay circuit used in a multiplexer or a demultiplexer in accordance with a seventh embodiment of the present invention.
  • a variable delay circuit 40 comprises a plurality of variable delay buffers 41 connected in series, a data input terminal 42 to which data to be delayed is input, a data output terminal 43 from which delayed data is output, and a control signal input terminal 44.
  • the number of the variable delay buffers 41 depends on the length of the delay time.
  • the data input terminal 42 is connected to an input terminal of the first stage variable delay buffer 41, and the data output terminal 43 is connected to an output terminal of the final stage variable delay buffer 41.
  • the control signal input terminal 44 is connected to control signal input terminals of the variable delay buffers 41 and supplies delay time control signals to the variable delay buffers 41.
  • FIG. 9 is a block diagram illustrating the circuit structure of the variable delay buffer 41 shown in figure 8.
  • the variable delay buffer 41 comprises a terminal 54 to which a supply voltage V DD is applied, diodes 45a to 45c each having an anode and a cathode, resistors 46a and 46b, field effect transistors (hereinafter referred to as FETs) 47 to 53 each having a gate, a drain, and a source, a terminal 55 to which a supply voltage V SS is applied, and data output terminals 56 and 57.
  • Reference numerals 47a to 51a designate gate terminals of the FETs 47 to 51, respectively.
  • the anode of the diode 45a is connected to the supply voltage V DD
  • the cathode of the diode 45a is connected to an end of the resistor 46a and to an end of the resistor 46b.
  • the other end of the resistor 46a is connected to the drain of the FET 47
  • the other end of the resistor 46b is connected to the drain of the FET 48.
  • a data input IN is input to the gate terminal 47a of the FET 47
  • a data input IN ⁇ is input to the gate terminal 48a of the FET 48.
  • the sources of the FETs 47 and 48 are connected to the drain of the FET 49.
  • the source of the FET 49 is connected to the supply voltage V SS .
  • the drain of the FET 52 is connected to the supply voltage V DD , and the gate of the FET 52 is connected to the junction of the resistor 46b and the FET 48.
  • the anode of the diode 45b is connected to the source of the FET 52.
  • the drain of the FET 53 is connected to the supply voltage V DD , and the gate of the FET 53 is connected to the junction of the resistor 46b and the FET 47.
  • the anode of the diode 45c is connected to the source of the FET 53.
  • the cathodes of the diodes 45b and 45c are connected to the data output terminals 56 and 57, respectively. Data outputs OUT and OUT ⁇ are output from the data output terminals 56 and 57, respectively.
  • the drain and the source of the FET 50 are connected to the data output terminal 56 and the supply voltage V SS , respectively.
  • the drain and the source of the FET 51 are connected to the data output terminal 57 and the supply voltage V SS ,
  • the FETs 49, 50, and 51 are current supply transistors, and gate voltages V CS1 , V CS2 , and V CS3 are applied to the gate terminals 49a, 50a, and 51a, respectively.
  • the gate terminals 49a and 50a are connected to the control signal input terminal 44 shown in figure 8, and the gate voltages V CS2 and V CS3 are controlled by the control circuit 30.
  • variable delay circuit 40 comprising the variable delay buffers 41 as shown in figure 8 is employed.
  • variable delay circuit 40 includes a plurality of variable delay buffers 41 between the data input terminal 42 to which the data SIG 1 is input and the data output terminal 43 from which the data SIG 2 is output, and the delay time of the data in the variable delay buffers is controlled in response to controlled signals applied to the control signal input terminal 44 from the control circuit 30.
  • the variable delay buffer 41 is a source follower buffer as shown in figure 9.
  • the data differentially input to the data input terminals 47a and 48a are differentially amplified in the FETs 47 and 48 and sent to the FETs 53 and 52, respectively.
  • the data are subjected to impedance conversion in the FETs 53 and 52 and output from the data output terminals 57 and 56, respectively.
  • variable delay buffer 41 the magnitude of the current flowing in the source follower buffer comprising the FETs 52 and 53 is controlled by simultaneously changing the gate voltages V CS2 and V CS3 at the gate terminals 50a and 50b of the FETs 50 and 51, respectively, using the control circuit 30, whereby the delay times of the data OUT and OUT ⁇ that are output from the data output terminals 56 and 57, respectively, are controlled.
  • the variable delay circuit 40 comprises a plurality of variable delay buffers 41 which control the delay time as described above, so that the delay times as many as the number of the buffers 41 are accumulated. Therefore, the data SIG 1 input to the data input terminal 42 is delayed by a time interval according to the number of the variable delay buffers 41 which are connected in series and the control signals applied to the control signal input terminal, and the delayed data is output from the data output terminal 43 as a data output SIG 2 .
  • the variable delay circuit 40 comprises a plurality of variable delay buffers 41, and the delay time of the data in the variable delay circuit 40 is controlled by the control circuit 30. Therefore, the delay time of the variable delay circuit 40 is easily controlled by switching the control signal from the control circuit 30. As a result, a multiplexer or a demultiplexer that can be adjusted to the normal operating state even when the delay times of the constituents of the circuit are varied is provided.
  • the delay time of the variable delay buffers 41 is controlled by varying the gate voltages V CS2 and V CS3 of the FETs 50 and 51 using the control circuit 30.
  • the control of the delay time may be performed by varying the gate voltage V CS1 at the gate terminal 49a of the FET 49 to change the logical amplitude of the variable delay buffer 41. Also in this case, the same effects as described above are achieved.
  • variable delay circuit 40 includes the SCFL (Source Coupled FET Logic) variable delay buffers 41.
  • SCFL Source Coupled FET Logic
  • BFL Buffered FET Logic
  • ECL emitter Coupled FET Logic
  • variable delay buffer 41 a double-phase driving source follower buffer may be employed with the same effects as described above.
  • the delay time of the variable delay buffer 41 is controlled by simultaneously controlling the gate voltages V CS2 and V CS3 with a control signal
  • the delay time may be controlled by separately controlling the gate voltages V CS2 and V CS3 and changing the cross point of the gate voltages V CS2 and V CS3 . Also in this case, the same effects as described above are achieved.
  • variable delay buffer 41 is controlled with the gate voltages V CS2 and V CS3
  • the delay time may be controlled by varying the supply voltages V DD and V SS using the control circuit 30 to control the magnitude of current.
  • the seventh embodiment of the invention a multiplexer similar to the multiplexer according to the first embodiment and employing the delay control circuit 40 comprising the variable delay buffers 41 in place of the delay control circuit 10 is described.
  • the delay control circuit 40 according to this seventh embodiment may be applied to the multiplexers according to the second and third embodiments and the demultiplexers according to the fourth to sixth embodiments with the same effects as described above.
EP96108607A 1995-08-10 1996-05-30 Multiplexer und Demultiplexer Withdrawn EP0759664A3 (de)

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JP7204577A JPH0955667A (ja) 1995-08-10 1995-08-10 マルチプレクサ，及びデマルチプレクサ

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EP0759664A3 EP0759664A3 (de) 1998-01-07

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EP0759664A3 (de) 1998-01-07

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