EP0730214A2 - Mirroir de courant en technologie MOS avec étages cascade réglables - Google Patents

Mirroir de courant en technologie MOS avec étages cascade réglables Download PDF

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Publication number
EP0730214A2
EP0730214A2 EP96102646A EP96102646A EP0730214A2 EP 0730214 A2 EP0730214 A2 EP 0730214A2 EP 96102646 A EP96102646 A EP 96102646A EP 96102646 A EP96102646 A EP 96102646A EP 0730214 A2 EP0730214 A2 EP 0730214A2
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EP
European Patent Office
Prior art keywords
current
input
output
circuit node
source
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP96102646A
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German (de)
English (en)
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EP0730214A3 (fr
EP0730214B1 (fr
Inventor
Ulrich Dr.-Ing. Theus
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TDK Micronas GmbH
Original Assignee
Deutsche ITT Industries GmbH
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Filing date
Publication date
Application filed by Deutsche ITT Industries GmbH filed Critical Deutsche ITT Industries GmbH
Publication of EP0730214A2 publication Critical patent/EP0730214A2/fr
Publication of EP0730214A3 publication Critical patent/EP0730214A3/fr
Application granted granted Critical
Publication of EP0730214B1 publication Critical patent/EP0730214B1/fr
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/26—Current mirrors
    • G05F3/262—Current mirrors using field-effect transistors only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the invention relates to a current mirror in MOS technology with widely controllable cascode stages, comprising a current bank which is controlled by a control circuit from a differential current which is tapped at a circuit node between the current mirror input and an associated, high-resistance cascode output, cf. the preamble of claim 1.
  • V DS ⁇ (V GS - V T ) with the n-channel transistor V DS ⁇ (V GS - V T ) with the p-channel transistor.
  • the main cause of the critical operating state of the n-channel current mirror in FIG. 1 is the gate potential of the common n-channel current bank control line, which is connected directly to the current mirror input. Since the series connection of the two drain-source current paths of the cascoded current mirror input is also located at this connection point, it can be seen immediately that the gate potential of the current bank transistor t1, which is also referred to below as a current mirror control transistor is referred to, the drain-source voltage of the cascode transistor t2 is higher than its drain potential.
  • V DSt2 denotes the drain-source voltage of the cascode transistor t2
  • V Tt1 denotes the threshold voltage of the current bank transistor t1.
  • the size of the threshold voltage V T is predetermined by the technology, whereby its negative temperature coefficient unfortunately just runs counter to the positive temperature coefficient of the effective gate voltage - for the same current but increasing crystal temperature.
  • the known circuit according to FIG. 2 provides a certain remedy, in which the gate electrode of the current mirror control transistor is controlled by a control circuit, the input of which is fed by a signal tapped at the current mirror input.
  • the input current path of the actual current mirror is separated electronically and a differential current is formed from the supplied current mirror input current and the output current of the current mirror control transistor. If the differential current becomes zero, then the input current supplied is equal to the output current of the current mirror control transistor and thus the setpoint of the control process is reached.
  • This measure sets the drive voltage for the gate connection of the current mirror control transistor and thus the potential of the common current bank control line to an uncritical value.
  • a simple examination of the resulting potential relationships shows that the potential of the common current bank control line can be significantly lower than the potential of the auxiliary voltage source and thus the desired saturation state for the current mirror control transistor and for the cascode stages of the current mirror is ensured.
  • An essential disadvantage of the circuit shown in FIG. 2, which contains a feedback operational amplifier as a control circuit, is the critical stability behavior, which can lead to control loop vibrations without suitable damping measures.
  • the circuit for stabilization requires at least one additional capacitor, which is particularly disadvantageous when the circuit is monolithically integrated.
  • the object of the invention characterized in claim 1 is therefore to provide an improved control for a current mirror in MOS technology with widely controllable cascode stages, with the aim of keeping the circuitry required low and the speed of the current mirror as high as possible.
  • control circuit contains, as an essential unit, a current-controlled current source, the control input of which is connected to the differential current tap in the current mirror input and the current output of which is connected to the common current bank control line, the control time constant being determined by a capacitive load on the Power source output is set.
  • the use of a current source in the control circuit has the advantage that the capacitive load of the common power bank control line, which can vary in size depending on the size and number of connected gate electrodes, represents the dominant pole point of the entire control loop and therefore essentially the control loop behavior certainly.
  • the other pole positions are less effective.
  • an additional internal or external capacity is not necessary due to the capacitive load of the common power bank control line.
  • the stability behavior also depends on the loop gain and thus on the current transformation ratio of the current-controlled current source. It is therefore advantageous if the current transformation ratio does not exceed the value 10, a preferred value being approximately 1, so that the input and output currents are approximately the same size.
  • the current transfer ratio can easily be set via the W / L ratio of the transistors coupled to the current source and current bank.
  • the potential of the low-impedance power source control input is determined in the type of gate circuit whose reference input, the gate terminal, is connected to a reference voltage and whose low-impedance signal input, the source terminal, forms the current source control input. It is pointed out that the input and output of the current source, and thus also the output of the voltage follower, operate in a bidirectional direction, ie the direction of flow of the respective currents can be positive or negative.
  • Such a current source can, for example, contain two interacting complementary current mirrors, an arrangement which particularly takes into account CMOS technology.
  • Such an arrangement connects, for example, an n- and a p-channel current mirror to one another such that the output of the p-channel current mirror is connected to the input of the n-channel current mirror directly or via cascode transistors.
  • the output of the n-channel current mirror is connected to the input of the p-channel current mirror directly or via cascode transistors.
  • Currents can be coupled in with low resistance and with high resistance via the cascode transistors in the two cross current paths.
  • Such a current mirror arrangement is therefore particularly suitable for the formation of a differential current, the differential current being able to be positive or negative. Capacitive influences on the frequency behavior of current mirrors are known per se from DE 42 01 155 C1, which relates to a switchable current mirror with MOS transistors of the same channel type in each case.
  • the known current mirror in FIG. 1 causes an input current ie generated by a source, not shown, to be fed to an n-channel current bank mb with the transistors t1, t3 is mirrored as the output current ia.
  • a cascode transistor t4 is connected between the current mirror output om and the drain electrode of the transistor t3.
  • the input current ie is also conducted via a cascode transistor t2, which lies between the current mirror input em and the drain connection of the current bank transistor t1, which also serves as a current mirror control transistor.
  • the common gate potential of the cascode transistors t2, t4 is connected to an auxiliary voltage uh, which is formed by means of an auxiliary current ih and an n-channel transistor t5 connected as a diode.
  • the common current bank control line cl of the current bank mb is connected to the drain electrode of the cascode transistor t2. It can easily be seen that the series connection of the two n-channel transistors t2, t1 makes the drain potential of the current bank transistor t1 too small in comparison to its gate potential under certain operating conditions, so that the required saturation of the transistors t1 and t2 is no longer present, as a result of which the current symmetry between the current bank transistors t1, t3 and possibly further current bank transistors is no longer maintained.
  • the main disadvantage of FIG. 1 - namely the relatively high gate potential of the current bank transistor t1 is eliminated by the common current bank control line being controlled by a control circuit r at the actual current mirror m.
  • the auxiliary voltage uh for the two cascode transistors t2, t4 is identical to the implementation according to FIG. 1. More complex circuits which serve to stabilize the auxiliary voltage uh are known, but have nothing to do with the actual invention.
  • the common current bank control line is connected to the output of an operational amplifier op, the non-inverting input of which is coupled to the current mirror input em and the inverting input of which is coupled to a reference voltage Ur.
  • the non-inverting input is connected to the common ground reference line M via an RC element R, C.
  • the drain-source current i1 which is controlled by the current bank control transistor t1 and also flows via the cascode transistor t2, depends in its size on the output voltage of the operational amplifier op.
  • the current mirror input em is fed by the arbitrary input current ie from a source, not shown. If both currents ie, i1 are not equal, then this must be one Differential current id result, which can be tapped at a first circuit node k1 or must be fed into this point.
  • the operational amplifier used here as usual, it is assumed that the output voltage is independent of the common mode voltage at the two operational amplifier inputs.
  • this decoupling means that the voltage at the current mirror input em can also be higher than the voltage of the current bank control line.
  • the RC element R, C is necessary to ensure the stability of the circuit. Due to the control effect, the drain-source current i1 changes and adjusts to the input current ie. The control goal is achieved when no residual current id flows and the current bank control line cl has reached its correct potential. Of course, with the size of the current i1, the output current ia of the current bank mb and thus the actual current level m has also changed proportionally.
  • the circuit according to FIG. 2 is very complex, the behavior of the circuit being satisfactory for stationary or slowly changing input currents. However, if the input currents change quickly and the output currents should generally follow these changes, the timing behavior of the control loop must be taken into account.
  • the critical factor here is the distribution of the poles and zeros of the closed control loop in the complex frequency level, which are coupled to the capacitances c1, c2, c3.
  • the first circuit node k1 is, for example, a high-resistance decoupling point and, together with the associated parasitic capacitance c1, forms a first pole point.
  • a second pole is formed by the negative feedback operational amplifier op and the RC element R, C, the frequency negative feedback of the operational amplifier by the capacitor c2 being indicated schematically.
  • its output signal is in every case 90 ° out of phase with its input signal.
  • the gate capacitances c3 of the current bank transistors t1, t3 and associated parasitic capacitances represent a third pole, which is effective in connection with the output resistance of the operational amplifier.
  • the three time constants of the pole points cause a phase shift that can easily cause the control loop to oscillate. This is particularly critical if the resulting ones Zero points / poles for the control loop are adjacent in frequency and the loop gain there is still large enough.
  • FIG. 3 shows an exemplary embodiment of a current mirror according to the invention. Circuit parts which are identical to those in FIG. 1 or FIG. 2 are represented with the same reference numerals, in particular the circuit parts of the actual current level m.
  • the input current path of the current mirror m is separated and a differential current id is formed from the input current ie and the current i1 from the current bank mb, which regulates the potential of the current bank control line cl via a control circuit r.
  • the control circuit r contains a current-controlled current source q, the low-resistance control input of which is fed with the differential current id and the high-resistance output, the circuit node k3, is connected directly to the current bank control line cl.
  • the use of a current source q to control the current bank transistors t1, t3 is an essential point of the invention, because it is generally assumed that MOS transistors are voltage and not current-controlled via the gate electrodes and their control should therefore be as low-resistance as possible , especially if the gate capacities are to be charged or discharged very quickly.
  • the controlled output current of the current source q is used in the current bank mb as the gate current ig for the gate capacitances c3, in order to track the current bank mb to the fluctuations in the input current ie.
  • the drive potential u3 of the current bank transistors t1, t3 is changed by the gate current ig.
  • the control target is reached, that is to say the input current ie is equal to the current bank current i1
  • the differential current id tapped at the first circuit node k1 has become zero, as a result of which the output current ig of the current source q also becomes zero.
  • the gate control potential u3 has then reached its setpoint - the control process is complete.
  • both the differential current id and the gate current ig must not be unidirectional, but rather the currents must be able to flow in a positive or negative direction.
  • This is achieved by implementing the current source q in FIG. 3.
  • the circuit implemented in CMOS technology is very advantageous since the current consumption is low due to the small number of cross current paths.
  • a four-transistor cell t6, t7, t8, t9 is inserted as a voltage follower sf into the current source q in such a way that all four transistors have a double function.
  • the voltage follower sf serves to determine the potential of the voltage level of the first circuit node k1, and thus the input em of the actual current mirror m. This is achieved by connecting the voltage follower input k4 to a reference voltage source Ur, the potential u4 of which is transmitted to the output k2 of the voltage follower sf.
  • the symmetrical design of the four-transistor cell with the n-channel transistors t6, t7 and the p-channel transistors t8, t9 has the effect that positive or negative currents can be tapped at the output k2 of the voltage follower sf.
  • the differential current id fed into the circuit node k2 is reflected back into the cross-current path pf with the circuit node k2 via two interacting complementary current mirrors m1, m2.
  • the differential current id injected into the circuit node k2 disturbs the predetermined current balance of the interacting current mirrors m1, m2 and generates a differential current ig which can be tapped at a circuit node k3. This is the gate current ig.
  • the high-resistance tap k3 is formed by the common connection point of the drain connections of an n-channel transistor t13 and the p-channel transistor t9.
  • the n-channel transistor t13 is the output transistor of the n-channel current mirror m2 and the transistor t9 is the p-channel output transistor of the four transistor cell.
  • the circuit node k3 thus represents the output of the current source q.
  • the common connection point k1, k2 is shown in FIG. 3 and the associated description as a separate circuit node k1, shown.
  • the potential u4 of the reference voltage source Ur determines the level u2 of the current mirror input em.
  • the gate drive potential for the cascode stages t2, t4 can easily be set lower than the current mirror input voltage u2 by appropriate selection of the auxiliary voltage uh.
  • the output voltage u3 the Current source q corresponds to the entire range of voltage u2 except for the saturation voltages of transistors t13 and t9.
  • the quiescent current of the two current mirrors m1, m2 connected in the chain is set by the current source currents i6, i8 in the input of the voltage follower sf.
  • An internal coupling of the two current sources makes currents i6 and i8 the same size. Since the potentials of the circuit nodes k2 and k4 are equal to one another, the n-channel transistors t6, t7 and the p-channel transistors t8, t9 can each be regarded as current mirrors which show the current source current i6 and the equally large current i8 mirror the respective output.
  • the differential current id which is supplied to the circuit node k3 in one direction via the current mirror m1, m2 and in the other direction via the transistor t9.
  • the current mirrors m1, m2 each have a current transmission ratio of 1: 1
  • the tapped output current ig is identical to the supplied differential current id.
  • More complex current source circuits can also be implemented, which have a current transformation ratio different from 1 between the input and output, for example between 0.1 and 10. This influences the charging or discharging of the current bank transistors t1, t3, but also changes the stability reserve.
  • the schematic representation of the auxiliary voltage source t5, the reference voltage source Ur and the current sources for the currents i6, i8 in FIG. 3 does not preclude known measures for improving the respective circuit function, for example the use of bandgap circuits to generate stable voltages or currents.
  • 3 shows only a single output current path for the current ie from the actual current level m. Other current outputs, also with any current transformation ratios, are not shown for the sake of clarity.
  • the exemplary embodiment in FIG. 3 contains q CMOS transistors in the current-controlled current source.
  • a current-controlled current source is also in pure n or. P-channel technology can be implemented.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Electromagnetism (AREA)
  • Nonlinear Science (AREA)
  • Automation & Control Theory (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Amplifiers (AREA)
  • Control Of Electrical Variables (AREA)
EP96102646A 1995-03-01 1996-02-22 Mirroir de courant en technologie MOS avec étages cascade réglables Expired - Lifetime EP0730214B1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE19507155 1995-03-01
DE19507155A DE19507155C1 (de) 1995-03-01 1995-03-01 Stromspiegel in MOS-Technik mit weit aussteuerbaren Kaskodestufen

Publications (3)

Publication Number Publication Date
EP0730214A2 true EP0730214A2 (fr) 1996-09-04
EP0730214A3 EP0730214A3 (fr) 1997-07-16
EP0730214B1 EP0730214B1 (fr) 2001-10-17

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EP96102646A Expired - Lifetime EP0730214B1 (fr) 1995-03-01 1996-02-22 Mirroir de courant en technologie MOS avec étages cascade réglables

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US (1) US5654629A (fr)
EP (1) EP0730214B1 (fr)
JP (1) JP3880649B2 (fr)
KR (1) KR960036010A (fr)
DE (2) DE19507155C1 (fr)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5801523A (en) * 1997-02-11 1998-09-01 Motorola, Inc. Circuit and method of providing a constant current
JP3315652B2 (ja) * 1998-09-07 2002-08-19 キヤノン株式会社 電流出力回路
DE19903577C2 (de) * 1999-01-29 2000-11-23 Micronas Intermetall Gmbh Schaltungsanordnung eines integrierten Stromspiegels
US7348850B2 (en) * 2003-10-15 2008-03-25 Nxp B.V. Electronic circuit for amplification of a bipolar signal
JP4170963B2 (ja) * 2004-07-22 2008-10-22 浜松ホトニクス株式会社 Ｌｅｄ駆動回路
US8786359B2 (en) * 2007-12-12 2014-07-22 Sandisk Technologies Inc. Current mirror device and method
JP5163437B2 (ja) * 2008-11-12 2013-03-13 ソニー株式会社 差動出力回路および通信装置
US20110050198A1 (en) * 2009-09-01 2011-03-03 Zhiwei Dong Low-power voltage regulator
FR2964274B1 (fr) * 2010-08-26 2013-06-28 St Microelectronics Sa Convertisseur a decoupage
TWI461702B (zh) * 2012-04-27 2014-11-21 Powerforest Technology Corp 極低啟動電流電源偵測裝置
FR3103333A1 (fr) * 2019-11-14 2021-05-21 Stmicroelectronics (Tours) Sas Dispositif pour générer un courant

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4583037A (en) * 1984-08-23 1986-04-15 At&T Bell Laboratories High swing CMOS cascode current mirror
US4983929A (en) * 1989-09-27 1991-01-08 Analog Devices, Inc. Cascode current mirror
US5099205A (en) * 1990-11-29 1992-03-24 Brooktree Corporation Balanced cascode current mirror
EP0606123A1 (fr) * 1993-01-06 1994-07-13 Philips Electronics Uk Limited Montage de circuit électrique
EP0613072A1 (fr) * 1993-02-12 1994-08-31 Koninklijke Philips Electronics N.V. Circuit intégré comportant un miroir de courant en cascade

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4201155C1 (fr) * 1992-01-17 1993-01-28 Texas Instruments Deutschland Gmbh, 8050 Freising, De
NL9201053A (nl) * 1992-06-15 1994-01-03 Koninkl Philips Electronics Nv Switched capacitor ladingspomp, alsmede zaagtandoscillator voorzien van een dergelijke switched capacitor ladingspomp.

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4583037A (en) * 1984-08-23 1986-04-15 At&T Bell Laboratories High swing CMOS cascode current mirror
US4983929A (en) * 1989-09-27 1991-01-08 Analog Devices, Inc. Cascode current mirror
US5099205A (en) * 1990-11-29 1992-03-24 Brooktree Corporation Balanced cascode current mirror
EP0606123A1 (fr) * 1993-01-06 1994-07-13 Philips Electronics Uk Limited Montage de circuit électrique
EP0613072A1 (fr) * 1993-02-12 1994-08-31 Koninklijke Philips Electronics N.V. Circuit intégré comportant un miroir de courant en cascade

Also Published As

Publication number Publication date
DE59607907D1 (de) 2001-11-22
EP0730214A3 (fr) 1997-07-16
KR960036010A (ko) 1996-10-28
EP0730214B1 (fr) 2001-10-17
JPH08274550A (ja) 1996-10-18
DE19507155C1 (de) 1996-08-14
JP3880649B2 (ja) 2007-02-14
US5654629A (en) 1997-08-05

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