EP0730214A2 - Current mirror in MOS technology with adjustable cascade stages - Google Patents

Abstract

The current mirror has a current bank including input and output side widely controllable cascade stages (t2,t4). A regulating circuit (r,p) generates the fixed potential of the cascade stages. A differential current (id) is fed to the control input of the regulating circuit. A first circuit node (k1) lies between a current mirror input and a first cascade stage (t2) coupled to a corresponding output of the current bank (mb). The regulation circuit includes a current controlled current source (q). The control input of the source, at a second circuit node (k2) is connected to the first node (k1). The output of the source, at a third node, is connected to a common control line (c1) for the current bank (mb). A capacitive load (c3), particularly one formed by capacitively charging the control line (c1), is connected to the third node (k3) to adjust a regulation time constant.

Description

The invention relates to a current mirror in MOS technology with widely controllable cascode stages, comprising a current bank which is controlled by a control circuit from a differential current which is tapped at a circuit node between the current mirror input and an associated, high-resistance cascode output, cf. the preamble of claim 1.

In monolithically integrated circuits, especially in analog working stages, current mirrors with the same or different current ratios and with one or more current outputs are used for a large number of auxiliary functions. In order to make the output characteristics of the current mirrors as independent of the voltage as possible, i.e. as high as possible, the individual current mirror outputs are designed as cascode stages, the fixed potential for the control electrodes of the cascode transistors being generated by means of an auxiliary voltage source. A very simple, often used current mirror with cascode stages in MOS technology is shown in FIG. 1. A disadvantage of this known circuit is that the saturation of some transistors is not guaranteed under special operating and technology-dependent conditions. The saturation range for an n- or p-channel transistor is defined by the known saturation equations: $$\begin{array}{c}\begin{array}{c}{\text{V}}_{\text{DS}}{\text{≧ (V}}_{\text{GS}}{\text{- V}}_{\text{T}}\text{) with the n-channel transistor and}\\ {\text{V}}_{\text{DS}}{\text{≦ (V}}_{\text{GS}}{\text{- V}}_{\text{T}}\text{) with the p-channel transistor.}\end{array}\end{array}$$

wobei V_DSt2 die Drain-Source-Spannung des Kaskodetransistors t2 und V_Tt1 die Schwellenspannung des Strombanktransistors t1 bezeichnet.
Die Größe der Schwellenspannung V_T ist durch die Technologie vorgegeben, wobei ihr negativer Temperaturkoeffizient dem positiven Temperaturkoeffizient der effektiven Gate-Spannung - für gleichen Strom aber zunehmende Kristalltemperatur - leider gerade entgegenläuft.The main cause of the critical operating state of the n-channel current mirror in FIG. 1 is the gate potential of the common n-channel current bank control line, which is connected directly to the current mirror input. Since the series connection of the two drain-source current paths of the cascoded current mirror input is also located at this connection point, it can be seen immediately that the gate potential of the current bank transistor t1, which is also referred to below as a current mirror control transistor is referred to, the drain-source voltage of the cascode transistor t2 is higher than its drain potential. Since the transistors t1 and t2 are both to be operated in saturation, it follows from the saturation equations: $${\text{V}}_{\text{DSt2}}{\text{<V}}_{\text{Tt1}}$$

where V _{DSt2 denotes} the drain-source voltage of the cascode transistor t2 and V _{Tt1 denotes} the threshold voltage of the current bank transistor t1.
The size of the threshold voltage V _T is predetermined by the technology, whereby its negative temperature coefficient unfortunately just runs counter to the positive temperature coefficient of the effective gate voltage - for the same current but increasing crystal temperature.

The known circuit according to FIG. 2 provides a certain remedy, in which the gate electrode of the current mirror control transistor is controlled by a control circuit, the input of which is fed by a signal tapped at the current mirror input. For this purpose, the input current path of the actual current mirror is separated electronically and a differential current is formed from the supplied current mirror input current and the output current of the current mirror control transistor. If the differential current becomes zero, then the input current supplied is equal to the output current of the current mirror control transistor and thus the setpoint of the control process is reached. This measure sets the drive voltage for the gate connection of the current mirror control transistor and thus the potential of the common current bank control line to an uncritical value. A simple examination of the resulting potential relationships shows that the potential of the common current bank control line can be significantly lower than the potential of the auxiliary voltage source and thus the desired saturation state for the current mirror control transistor and for the cascode stages of the current mirror is ensured.

An essential disadvantage of the circuit shown in FIG. 2, which contains a feedback operational amplifier as a control circuit, is the critical stability behavior, which can lead to control loop vibrations without suitable damping measures.

On the other hand, the usual damping measures influence the frequency behavior of the current mirror, so that it becomes too slow for many signal applications. In addition, the circuit for stabilization requires at least one additional capacitor, which is particularly disadvantageous when the circuit is monolithically integrated.

The object of the invention characterized in claim 1 is therefore to provide an improved control for a current mirror in MOS technology with widely controllable cascode stages, with the aim of keeping the circuitry required low and the speed of the current mirror as high as possible.

This object is achieved in accordance with the characterizing features of patent claim 1 in that the control circuit contains, as an essential unit, a current-controlled current source, the control input of which is connected to the differential current tap in the current mirror input and the current output of which is connected to the common current bank control line, the control time constant being determined by a capacitive load on the Power source output is set.

The use of a current source in the control circuit has the advantage that the capacitive load of the common power bank control line, which can vary in size depending on the size and number of connected gate electrodes, represents the dominant pole point of the entire control loop and therefore essentially the control loop behavior certainly. The other pole positions are less effective. As a rule, an additional internal or external capacity is not necessary due to the capacitive load of the common power bank control line.

The stability behavior also depends on the loop gain and thus on the current transformation ratio of the current-controlled current source. It is therefore advantageous if the current transformation ratio does not exceed the value 10, a preferred value being approximately 1, so that the input and output currents are approximately the same size. The current transfer ratio can easily be set via the W / L ratio of the transistors coupled to the current source and current bank.

The potential of the low-impedance power source control input is determined in the type of gate circuit whose reference input, the gate terminal, is connected to a reference voltage and whose low-impedance signal input, the source terminal, forms the current source control input. It is pointed out that the input and output of the current source, and thus also the output of the voltage follower, operate in a bidirectional direction, ie the direction of flow of the respective currents can be positive or negative. Such a current source can, for example, contain two interacting complementary current mirrors, an arrangement which particularly takes into account CMOS technology. Such an arrangement connects, for example, an n- and a p-channel current mirror to one another such that the output of the p-channel current mirror is connected to the input of the n-channel current mirror directly or via cascode transistors. In the same way, the output of the n-channel current mirror is connected to the input of the p-channel current mirror directly or via cascode transistors. Currents can be coupled in with low resistance and with high resistance via the cascode transistors in the two cross current paths. Such a current mirror arrangement is therefore particularly suitable for the formation of a differential current, the differential current being able to be positive or negative. Capacitive influences on the frequency behavior of current mirrors are known per se from DE 42 01 155 C1, which relates to a switchable current mirror with MOS transistors of the same channel type in each case.

• Fig. 1 zeigt einen bekannten Stromspiegel mit Kaskodestufen,
• Fig. 2 zeigt einen bekannten Stromspiegel mit Kaskodestufen, wobei das Gate-Potential der eigentlichen Strombank von einer Regelschaltung erzeugt wird und
• Fig. 3 zeigt ein vorteilhaftes Ausführungsbeispiel eines Stromspiegels mit Kaskodestufen, wobei die Pegelregelung der Strombank nach der Erfindung erfolgt.

The invention and further advantageous embodiments are now explained in more detail with reference to the figures of the drawing:

• 1 shows a known current mirror with cascode stages,
• FIG. 2 shows a known current mirror with cascode stages, the gate potential of the actual current bank being generated by a control circuit and
• 3 shows an advantageous exemplary embodiment of a current mirror with cascode stages, the level control of the current bank taking place according to the invention.

The known current mirror in FIG. 1 causes an input current ie generated by a source, not shown, to be fed to an n-channel current bank mb with the transistors t1, t3 is mirrored as the output current ia. To decouple the output current ia from the respective output voltage, a cascode transistor t4 is connected between the current mirror output om and the drain electrode of the transistor t3. For reasons of symmetry, the input current ie is also conducted via a cascode transistor t2, which lies between the current mirror input em and the drain connection of the current bank transistor t1, which also serves as a current mirror control transistor. The common gate potential of the cascode transistors t2, t4 is connected to an auxiliary voltage uh, which is formed by means of an auxiliary current ih and an n-channel transistor t5 connected as a diode. The common current bank control line cl of the current bank mb is connected to the drain electrode of the cascode transistor t2. It can easily be seen that the series connection of the two n-channel transistors t2, t1 makes the drain potential of the current bank transistor t1 too small in comparison to its gate potential under certain operating conditions, so that the required saturation of the transistors t1 and t2 is no longer present, as a result of which the current symmetry between the current bank transistors t1, t3 and possibly further current bank transistors is no longer maintained.

In Fig. 2, the main disadvantage of FIG. 1 - namely the relatively high gate potential of the current bank transistor t1 is eliminated by the common current bank control line being controlled by a control circuit r at the actual current mirror m. The auxiliary voltage uh for the two cascode transistors t2, t4 is identical to the implementation according to FIG. 1. More complex circuits which serve to stabilize the auxiliary voltage uh are known, but have nothing to do with the actual invention. 2, the common current bank control line is connected to the output of an operational amplifier op, the non-inverting input of which is coupled to the current mirror input em and the inverting input of which is coupled to a reference voltage Ur. The non-inverting input is connected to the common ground reference line M via an RC element R, C. The drain-source current i1, which is controlled by the current bank control transistor t1 and also flows via the cascode transistor t2, depends in its size on the output voltage of the operational amplifier op. In contrast, the current mirror input em is fed by the arbitrary input current ie from a source, not shown. If both currents ie, i1 are not equal, then this must be one Differential current id result, which can be tapped at a first circuit node k1 or must be fed into this point. In the operational amplifier used here, as usual, it is assumed that the output voltage is independent of the common mode voltage at the two operational amplifier inputs. This ensures that the control voltage for the current bank control line is independent of the voltage at the current mirror input em. In particular, this decoupling means that the voltage at the current mirror input em can also be higher than the voltage of the current bank control line. The RC element R, C is necessary to ensure the stability of the circuit. Due to the control effect, the drain-source current i1 changes and adjusts to the input current ie. The control goal is achieved when no residual current id flows and the current bank control line cl has reached its correct potential. Of course, with the size of the current i1, the output current ia of the current bank mb and thus the actual current level m has also changed proportionally.

As already stated, the circuit according to FIG. 2 is very complex, the behavior of the circuit being satisfactory for stationary or slowly changing input currents. However, if the input currents change quickly and the output currents should generally follow these changes, the timing behavior of the control loop must be taken into account. The critical factor here is the distribution of the poles and zeros of the closed control loop in the complex frequency level, which are coupled to the capacitances c1, c2, c3. The first circuit node k1 is, for example, a high-resistance decoupling point and, together with the associated parasitic capacitance c1, forms a first pole point. A second pole is formed by the negative feedback operational amplifier op and the RC element R, C, the frequency negative feedback of the operational amplifier by the capacitor c2 being indicated schematically. In the normal frequency range of the operational amplifier, its output signal is in every case 90 ° out of phase with its input signal. Finally, the gate capacitances c3 of the current bank transistors t1, t3 and associated parasitic capacitances represent a third pole, which is effective in connection with the output resistance of the operational amplifier. The three time constants of the pole points cause a phase shift that can easily cause the control loop to oscillate. This is particularly critical if the resulting ones Zero points / poles for the control loop are adjacent in frequency and the loop gain there is still large enough. As a remedy, either the loop gain is reduced or a dominant pole point is generated by increasing the capacitance c2, or a pole point is partially compensated by a zero point, here the RC element R, C. However, all measures adversely affect the control behavior because the control speed is slowed down.

3 shows an exemplary embodiment of a current mirror according to the invention. Circuit parts which are identical to those in FIG. 1 or FIG. 2 are represented with the same reference numerals, in particular the circuit parts of the actual current level m. As in FIG. 2, the input current path of the current mirror m is separated and a differential current id is formed from the input current ie and the current i1 from the current bank mb, which regulates the potential of the current bank control line cl via a control circuit r. The control circuit r contains a current-controlled current source q, the low-resistance control input of which is fed with the differential current id and the high-resistance output, the circuit node k3, is connected directly to the current bank control line cl. The use of a current source q to control the current bank transistors t1, t3 is an essential point of the invention, because it is generally assumed that MOS transistors are voltage and not current-controlled via the gate electrodes and their control should therefore be as low-resistance as possible , especially if the gate capacities are to be charged or discharged very quickly. The controlled output current of the current source q is used in the current bank mb as the gate current ig for the gate capacitances c3, in order to track the current bank mb to the fluctuations in the input current ie. The drive potential u3 of the current bank transistors t1, t3 is changed by the gate current ig. If the control target is reached, that is to say the input current ie is equal to the current bank current i1, then the differential current id tapped at the first circuit node k1 has become zero, as a result of which the output current ig of the current source q also becomes zero. The gate control potential u3 has then reached its setpoint - the control process is complete.

The described mode of operation of the control process makes it clear that both the differential current id and the gate current ig must not be unidirectional, but rather the currents must be able to flow in a positive or negative direction. This is achieved by implementing the current source q in FIG. 3. The circuit implemented in CMOS technology is very advantageous since the current consumption is low due to the small number of cross current paths. In particular, a four-transistor cell t6, t7, t8, t9 is inserted as a voltage follower sf into the current source q in such a way that all four transistors have a double function. The voltage follower sf serves to determine the potential of the voltage level of the first circuit node k1, and thus the input em of the actual current mirror m. This is achieved by connecting the voltage follower input k4 to a reference voltage source Ur, the potential u4 of which is transmitted to the output k2 of the voltage follower sf. The symmetrical design of the four-transistor cell with the n-channel transistors t6, t7 and the p-channel transistors t8, t9 has the effect that positive or negative currents can be tapped at the output k2 of the voltage follower sf. Since the output k2 of the voltage follower sf is also the control input of the current source q, the differential current id fed into the circuit node k2 is reflected back into the cross-current path pf with the circuit node k2 via two interacting complementary current mirrors m1, m2. The differential current id injected into the circuit node k2 disturbs the predetermined current balance of the interacting current mirrors m1, m2 and generates a differential current ig which can be tapped at a circuit node k3. This is the gate current ig. The high-resistance tap k3 is formed by the common connection point of the drain connections of an n-channel transistor t13 and the p-channel transistor t9. The n-channel transistor t13 is the output transistor of the n-channel current mirror m2 and the transistor t9 is the p-channel output transistor of the four transistor cell. The circuit node k3 thus represents the output of the current source q. In order to be able to better describe the functioning of the actual current level m and the current source q in a separate form, the common connection point k1, k2 is shown in FIG. 3 and the associated description as a separate circuit node k1, shown.

As described, the potential u4 of the reference voltage source Ur determines the level u2 of the current mirror input em. The gate drive potential for the cascode stages t2, t4 can easily be set lower than the current mirror input voltage u2 by appropriate selection of the auxiliary voltage uh. The output voltage u3 the Current source q corresponds to the entire range of voltage u2 except for the saturation voltages of transistors t13 and t9.

The quiescent current of the two current mirrors m1, m2 connected in the chain is set by the current source currents i6, i8 in the input of the voltage follower sf. An internal coupling of the two current sources makes currents i6 and i8 the same size. Since the potentials of the circuit nodes k2 and k4 are equal to one another, the n-channel transistors t6, t7 and the p-channel transistors t8, t9 can each be regarded as current mirrors which show the current source current i6 and the equally large current i8 mirror the respective output. These currents are superimposed on the differential current id, which is supplied to the circuit node k3 in one direction via the current mirror m1, m2 and in the other direction via the transistor t9. If the current mirrors m1, m2 each have a current transmission ratio of 1: 1, the tapped output current ig is identical to the supplied differential current id. More complex current source circuits can also be implemented, which have a current transformation ratio different from 1 between the input and output, for example between 0.1 and 10. This influences the charging or discharging of the current bank transistors t1, t3, but also changes the stability reserve. 3 is very large, since the dominant time constant is formed by the gate capacitance c3 of the current bank control line cl in connection with the high-resistance connection point k3. This is because the parasitic capacitance c1 coupled to the circuit node k1 only "sees" the low-impedance output k2 of the voltage follower sf.

The schematic representation of the auxiliary voltage source t5, the reference voltage source Ur and the current sources for the currents i6, i8 in FIG. 3 does not preclude known measures for improving the respective circuit function, for example the use of bandgap circuits to generate stable voltages or currents. 3 shows only a single output current path for the current ie from the actual current level m. Other current outputs, also with any current transformation ratios, are not shown for the sake of clarity. The exemplary embodiment in FIG. 3 contains q CMOS transistors in the current-controlled current source. Of course, a current-controlled current source is also in pure n or. P-channel technology can be implemented.

Claims (7)

Current mirror in MOS technology with a power bank (mb) which contains cascode levels (t2, t4) which can be widely controlled on the input and output sides, - A control circuit (r, p) which generates the fixed potential of the cascode stages (t2, t4) and whose control input is supplied with a differential current (id), and a first circuit node (k1), which lies between a current mirror input (em) and a first cascode stage (t2) coupled to an associated output of the current bank (mb) and at which the differential current (id) can be tapped,
characterized in that - The control circuit (r) contains a current-controlled current source (q), whose control input, the second circuit node (k2), with the first circuit node (k1) and whose output, the third circuit node (k3), with a common control line (cl) for the power bank (mb) is connected, and - A capacitive load (c3), which is formed in particular by the capacitive load of the common control line (cl), is connected to the third circuit node (k3) for setting a control time constant. Current mirror according to claim 1, characterized in that the current source (q) between its input and output, the second or third circuit node (k2 or k3), has a current transformation ratio which is between 0.1 and 10, in particular in the range of 1 lies. Current mirror according to claim 2, characterized in that the current source (q) for determining the potential at the second circuit node (k2) contains a voltage follower (sf) whose input, a fourth circuit node (k4), is connected to a reference voltage source (Ur) and whose low-resistance output is identical to the input (k2) of the current source (q). Current mirror according to claim 3, characterized in that the current source (q) contains two interacting complementary current mirrors (m1, m2). Current mirror according to claim 4, characterized in that a current path (pf) of the cooperating complementary current mirrors (m1, m2) contains the output of the voltage follower (sf) by inserting a complementary pair of transistors (t7, t9) in series connection into the current path (pf) whose common source connection forms the second circuit node (k2) and whose gate connections are each connected to the fourth circuit node (k4) via a MOS diode (t6 or t8). Current mirror according to Claim 5, characterized in that the third circuit node (k3) serving as the output of the current-controlled current source (q) is formed by the common drain connection between two complementary, series-connected transistors (t9, t13) in the current path (pf) . Current mirror according to one of Claims 3 to 6, characterized in that the voltage follower (sf) contains a four-transistor cell composed of two complementary transistor pairs (t6, t8 or t7, t9), the transistors of which are paired with one another in their electrical properties, irrespective of the conductivity type.

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