EP0596565B1 - Novel device configuration with multiple HV-LDMOS transistors and a floating well circuit - Google Patents

Novel device configuration with multiple HV-LDMOS transistors and a floating well circuit Download PDF

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Publication number
EP0596565B1
EP0596565B1 EP93203015A EP93203015A EP0596565B1 EP 0596565 B1 EP0596565 B1 EP 0596565B1 EP 93203015 A EP93203015 A EP 93203015A EP 93203015 A EP93203015 A EP 93203015A EP 0596565 B1 EP0596565 B1 EP 0596565B1
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EP
European Patent Office
Prior art keywords
voltage
circuit
floating
floating well
well
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
EP93203015A
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German (de)
English (en)
French (fr)
Other versions
EP0596565A3 (en
EP0596565A2 (en
Inventor
Michael Amato
Satyendranath Mukherjee
Paul Veldman
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koninklijke Philips NV
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Koninklijke Philips Electronics NV
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Publication of EP0596565A2 publication Critical patent/EP0596565A2/en
Publication of EP0596565A3 publication Critical patent/EP0596565A3/en
Application granted granted Critical
Publication of EP0596565B1 publication Critical patent/EP0596565B1/en
Anticipated expiration legal-status Critical
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/811—Combinations of field-effect devices and one or more diodes, capacitors or resistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/85—Complementary IGFETs, e.g. CMOS
    • H10D84/856—Complementary IGFETs, e.g. CMOS the complementary IGFETs having different architectures than each other, e.g. high-voltage and low-voltage CMOS

Definitions

  • This invention relates to a novel semiconductor device comprising a semiconductor body configuration which combines a plurality of HV-LDMOS transistors, a plurality of resistors, and a floating circuit well into a single structure.
  • FIGS 1 to 4 show circuit diagrams and a cross-section through a silicon wafer accommodating at least two insulated LDMOS level shift transistors and a floating well with circuitry.
  • Such a device is constructed by means well known in the art and includes a substrate 7 of a first conductivity type, preferably with p polarity, a buried layer 8 with opposite conductivity, preferably with n+ polarity connected to an epitaxial layer, preferably of n- polarity. Above the buried layer 8, the epitaxial layer 6 is arranged.
  • the regions 40 and 41 forming the body, 26 and 28 forming the source, and 27 forming the drain of the LDMOS transistor 3, and the regions 42 and 43 forming the body, 31 and 33 forming the source, and 32 forming the drain of the LDMOS transistor 5, as well as the p+ regions (p-iso regions) 12, 13, 14 and 15 separating the n-epitaxial layer 6 into isolated n-epitaxial regions 45, 46 and 47, are provided.
  • the reference numerals 34 and 37 represent the gate electrodes.
  • the p+ regions 13 and 14 isolate the LDMOS devices 3 and 5, respectively, from the floating-well circuitry.
  • the N-MOS device formed inside P-well 10, and the P-MOS device formed inside N-well 11 form part of the circuitry inside floating well 1.
  • the high voltage interconnect 2, 4 is made from the drain 27, 32 of the LDMOS transistor 3, 5 to the N-well portion 11 and the P-well portion 10 of the floating well, crossing over the LDMOS transistor 3, 5 and junction 35, 36.
  • the circuit in the well floats from 0 volts up to 1000 V.
  • Turn on/turn off signals are generated by a voltage drop V R1 , V R2 at the resistors R 1 and R 2 whereby V R1 , V R2 is 0 - 20 volts.
  • the high voltage interconnects are necessary to connect the drain terminals of the LDMOS transistors to the resistors R 1 and R 2 in the floating well.
  • a low voltage signal is provided to a level shifter which transfers it to a higher level.
  • a voltage signal must be referenced to the output of an inverter stage. As this output voltages goes up and down, the signal applied floats with it.
  • the n-epitaxial regions can be tied to a node having essentially a positive DC voltage with respect to the output of, for example, a half-bridge circuit, and supply a signal between the control-and reference-electrode of an NPN or N-channel FET (MOS-FET, IGBT) device having its reference electrode essentially connected to the output of said half-bridge circuit, via a high-voltage crossover and the circuitry in the floating well.
  • MOS-FET, IGBT N-channel FET
  • the term "reference electrode essentially connected to the output” is meant to cover a ripple on the DC voltate and an indirect connection of the reference electrode to the output of the half-bridge, eg.
  • control electrode is meant to indicate a base and gate; and “reference electrode” indicates an emitter, source or cathode (N-channel).
  • Figs. 1 and 2 show circuit diagrams which illustrate the input/output electronics of the floating well.
  • a bootstrap-capacitor 50 maintains a voltage between node 59 and 60 of typically between 5 and 20 Vdc; node 60 being positive with respect to node 59.
  • the state of the voltage at node 58 with respect to node 59 can be changed in the following way: By applying a pulse of voltage of well controlled magnitude to the control electrode of level-shift transistor 3, this device will sink a pulse of current into its drain 27. This will result in a pulse-shaped voltage drop across resistor 51, relatively independent of the momentary voltage level of node 59 and 60. As there is no current flow through the other level-shift transistor 5 at that time, the voltage across resistor 52 will be essentially 0. As soon as the difference between the voltage across resistors 51 and 52 exceeds the hysteresis-level built into comparator 53, the output of comparator 53 will go high with respect to node 59. The non-inverting buffer formed by the transistors 54, 55, 56 and 57 will consequently pull output node 58 up to essentially the same voltage as node 60, thereby making node 58 positive with respect to node 59.
  • a pulse of voltage of well controlled magnitude can be applied to the control electrode of transistor 5. This will result in a pulse-shaped flow of current into drain 32 of transistor 5, and consequently result in a voltage drop across resistor 52. As there is no flow of current into drain 27 of transistor 3, the voltage drop across resistor 51 will be 0. As soon as the difference between the voltages across resistors 51 and 52 exceeds the hysteresis-level built into comparator 53, the output of comparator 53 will go low with respect to node 59. The non-inverting buffer formed by the transistors 54, 55, 56 and 57 will consequently pull output node 58 down to essentially the same voltage as node 59.
  • the circuit illustrated in Figure 2 acts in an identical fashion, with the pulsating current sources formed by transistors 3 and 5 being replaced by the cascoded current sources formed by transistor 63 and 64, or 65 and 66, respectively.
  • Transistor 64 and 66 act as current sources, and can be standard N-MOS low-voltage devices or can even be replaced by low-voltage NPN bipolar devices.
  • Transistors 63 and 65 are LDMOS devices, and are used to support the high voltage. Figure 2 shows two embodiments of these LDMOS devices; one with the body connected to the source (transistor 63) and one with the body connected to ground (transistor 65).
  • a level shift circuit with a double-diffused MOSFET and a high voltage bipolar transistor is known from US-A-4 859 878.
  • a floating region having a resistive element is known from JP-A-63018660.
  • An object of the present invention is to provide a circuit for a floating well and level shifter from ground potential to the floating well wherein high-voltage interconnect cross-overs and the problems associated therewith are substantially eliminated.
  • Another object of the invention is to provide a device wherein there is a reduction of capacitances and chip size.
  • a semiconductor or integrated circuit comprising a semiconductor body defined by a plurality of superimposed layers with opposite conductivity types and at least one insulating oxide layer, at least one and prefereably at least two high voltage LDMOS transistors, at least one and preferably at least two sense resistors, and a floating circuit well are combined into an integrated circuit on a single silicon chip in which the high-voltage cross-overs are substantially eliminated, and in which a low-voltage level shift signal to the floating well is provided through the high voltage region of the floating well itself (instead of through the high-voltage region of a separate circuit which signal is brought to the resistors in the floating well via a cross-over).
  • a device wherein the level shift current sources are incorporated in the same N-well as the floating well circuitry, i.e. a built-in resistor is present in the n-epi layer.
  • This built-in resistor with "parasitic" resistance may be used to convert the level shift signal current to a voltage signal that is sensed by circuitry in the floating well.
  • the device of the invention lets current flow to the low voltage area through the gate-channel down to the ground and uses that current to generate a signal, i.e. the current flows from an n+ region through a n- epi resistor to a sense node.
  • the structures of the invention are eminently suitable for eliminating problems associated with high-voltage interconnect crossovers discussed above and provides enhanced integrated circuit devices as further described and claimed hereinbelow.
  • the invention further comprises improved and enhanced structures of the type just described but wherein the connection between the drain of the current sources and the floating well is spaced by a predetermined distance L1 and/or is spaced by a predetermined distance L1 over an area of reduced cross-section with a width W1, preferably a necked-in area, whereby the parasitic resistance between the current sources and the floating well is increased considerably.
  • Such enhanced structures may embody circular LDMOS current sources of minimum dimensions thereby allowing the current sources to be located anywhere along the floating well including locations adjacent to or opposite the floating well.
  • a sense resistor inside the floating well may be used which is voltage independent and by which the parasitic resistance is maximized.
  • the parasitic resistor may be increased to a very high value and when so valued, the voltage independent sense resistor inside the floating well is used.
  • the structure comprises two LDMOS level shift transistors 103, 105 comprising an epitaxial layer 106 of relatively high resistivity, (eg., a N-conductivity type layer) grown on a p-substrate 107 substantially as described above with respect to Figs. 1 to 4.
  • an epitaxial layer 106 of relatively high resistivity eg., a N-conductivity type layer
  • the drain 127, 132 of the level shift current sources formed by the LDMOS devices 103, 105 are spaced apart from the floating well 101 by a distance L1, and the high-voltage interconnect has been eliminated.
  • the level shift current sources are placed in the same n-epitaxial region as the floating well circuitry, wherein the parasitic resistance R 1 , R 2 between the drain n-region 119, 124 of the current sources and the n-regions 108, 182 and 183 is created and functionally utilized.
  • the metal regions 127 and 132 form the drain of LDMOS 103 and 105 respectively.
  • the n+ regions 119 and 124 form one of the terminals of the resistors R1 and R2 (151 and 152, 180 and 181), where the n+ regions 182 and 183, together with n-buried layer 108 form the other terminal of the resistors R1 and R2 (151 and 152, 180 and 181); these latter terminals are electrically equivalent to circuit-node 60.
  • the resistance of R1 and R2 (151 and 152, 180 and 181) is formed by the part of the n-epitaxial layer 106 between region 119 and 108, 182 or between region 124 and 108, 183 respectively.
  • a high-voltage structure which comprises a circuit 100 which comprises a floating well 101 connected to LDMOS level shift transistors 103 and 105 via R 1 and R 2 sense resistors 180 and 181 and in which high-voltage interconnects are eliminated although low voltage cross-overs 171 and 172 between the floating well and transistors for sensing purposes are retained. Since these are not of high voltage, the problems discussed above relative to high voltage cross-overs are eliminated. In this structure, all interconnects run above the silicon in a low voltage metal connection with less than 20V necessitating low voltage junctions.
  • the need for high-voltage interconnect is circumvented by putting the level shift current sources in the same n-epitaxial portion as the floating well circuitry and using the parasitic resistance between the drain of the current source and the n+ buried layer 108 of the floating well as best seen in Fig. 7.
  • a preferred layout of this embodiment is illustrated in Fig. 8.
  • to meet the minimum resistance that may be required for an application it is necessary to create sufficient spacing between the floating well circuitry and the drain of the current sources. Such a spacing is represented by L1 in the Fig. 8 illustration.
  • L1 in the Fig. 8 illustration.
  • it are optimally placed at opposite sides of the floating well circuit.
  • the invention also comprises several steps for increasing the parasitic resistance and increasing the flexibility of the layout of the resulting structures.
  • one or both of the distances L1 and W1 between the current sources and the floating well are reduced and the cross-sectional areas 30, 31 of the interconnect regions are accordingly reduced.
  • the interconnect regions are necked-in as illustrated in Fig. 9. This reduction in cross-sectional area has been found to increase the parasitic resistance between the current sources and the floating well considerably. This necking-in also considerably reduces the interference between the two HV-LDMOS structures, allowing them to be placed everywhere along the periphery of the floating well instead of opposite each other.
  • the length of the drift region Ld is essentially the same as that for the floating well circuit.
  • the oxide 9 underneath the metal 171 can support at least partially the voltage between metal and the p-iso 13, 14, p- buried 190 and p-substrate 107 portions of the device. This means that the depletion in the n-epitaxial, p-substrate and p-buried portions only has to support the required breakdown voltage, minus the voltage that is supported by the oxide. This discovery makes it possible to educe the drift region length Ld to that value that will support this lower voltage.
  • the Ld length may be reduced from 50 ⁇ m to 25 ⁇ m resulting in a smaller cross-section of the n-epitaxial region. This can be done as long as the critical field strength in the silicon at the edge of the metal as a result of curvature breakdown is not exceeded.
  • the area of the cross-section of the n-epitaxial region can be reduced even further, therefore also further increasing the parasitic resistance.
  • a field plate 192 is provided along the edge of the p-iso regions 13 and 14 for reducing the field strength.
  • resistor to convert the current drawn by the LDMOS devices, being used in a current source mode, into a voltage.
  • resistor as used herein is used in the broadest possible sense, i.e. these resistors can essentially be almost any circuit element or combination of elements having the property that a current through or change in current through the combination of these elements results in a voltage across or change in voltage across the combination of these circuit elements.
  • these elements may be any essentially non-reactive circuit elements.

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  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
EP93203015A 1992-11-04 1993-10-28 Novel device configuration with multiple HV-LDMOS transistors and a floating well circuit Expired - Lifetime EP0596565B1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US07/971,382 US5446300A (en) 1992-11-04 1992-11-04 Semiconductor device configuration with multiple HV-LDMOS transistors and a floating well circuit
US971382 1992-11-04

Publications (3)

Publication Number Publication Date
EP0596565A2 EP0596565A2 (en) 1994-05-11
EP0596565A3 EP0596565A3 (en) 1997-06-04
EP0596565B1 true EP0596565B1 (en) 2000-07-26

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EP93203015A Expired - Lifetime EP0596565B1 (en) 1992-11-04 1993-10-28 Novel device configuration with multiple HV-LDMOS transistors and a floating well circuit

Country Status (5)

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US (1) US5446300A (enrdf_load_stackoverflow)
EP (1) EP0596565B1 (enrdf_load_stackoverflow)
JP (1) JPH06260601A (enrdf_load_stackoverflow)
DE (1) DE69329097T2 (enrdf_load_stackoverflow)
TW (1) TW244394B (enrdf_load_stackoverflow)

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JP4775357B2 (ja) * 1995-04-12 2011-09-21 富士電機株式会社 高耐圧ｉｃ
JP4013785B2 (ja) * 1995-04-12 2007-11-28 富士電機デバイステクノロジー株式会社 高耐圧ｉｃ
JP3565181B2 (ja) * 1995-06-28 2004-09-15 富士電機デバイステクノロジー株式会社 高耐圧ｉｃ
JP3228093B2 (ja) * 1995-06-28 2001-11-12 富士電機株式会社 高耐圧ｉｃ
DE69530216T2 (de) * 1995-12-19 2004-02-12 Consorzio Per La Ricerca Sulla Microelettronica Nel Mezzogiorno - Corimme Monolithische Halbleiteranordnung mit Randstruktur und Verfahren zur Herstellung
JP3917211B2 (ja) * 1996-04-15 2007-05-23 三菱電機株式会社 半導体装置
DE69834321T2 (de) * 1998-07-31 2006-09-14 Freescale Semiconductor, Inc., Austin Halbleiterstruktur für Treiberschaltkreise mit Pegelverschiebung
DE19919130B4 (de) * 1999-04-27 2005-10-06 Infineon Technologies Ag Monolithisch integrierte Halbleiteranordnung mit einem Steuerbereich und einem spannungsaufnehmenden Bereich
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JP4610786B2 (ja) * 2001-02-20 2011-01-12 三菱電機株式会社 半導体装置
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JP4545548B2 (ja) * 2004-10-21 2010-09-15 ルネサスエレクトロニクス株式会社 半導体集積回路及び半導体装置
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KR101463076B1 (ko) * 2008-03-28 2014-12-05 페어차일드코리아반도체 주식회사 레벨 시프트 소자들을 구비하는 고압 반도체소자 및 그의제조방법
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TWI448055B (zh) 2010-06-07 2014-08-01 Richtek Technology Corp 切換式電源供應器之控制電路及其控制方法以及用於其中之電晶體元件
JP6379509B2 (ja) * 2014-02-18 2018-08-29 セイコーエプソン株式会社 回路装置及び電子機器
TWI595653B (zh) * 2016-09-13 2017-08-11 立積電子股份有限公司 用於增加信號振幅範圍的電晶體
TWI876658B (zh) * 2023-11-06 2025-03-11 世界先進積體電路股份有限公司 高壓半導體裝置

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Also Published As

Publication number Publication date
JPH06260601A (ja) 1994-09-16
EP0596565A3 (en) 1997-06-04
DE69329097D1 (de) 2000-08-31
US5446300A (en) 1995-08-29
EP0596565A2 (en) 1994-05-11
DE69329097T2 (de) 2001-03-22
TW244394B (enrdf_load_stackoverflow) 1995-04-01

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