EP0296760B1 - A static random access memory circuit - Google Patents

A static random access memory circuit Download PDF

Info

Publication number
EP0296760B1
EP0296760B1 EP88305509A EP88305509A EP0296760B1 EP 0296760 B1 EP0296760 B1 EP 0296760B1 EP 88305509 A EP88305509 A EP 88305509A EP 88305509 A EP88305509 A EP 88305509A EP 0296760 B1 EP0296760 B1 EP 0296760B1
Authority
EP
European Patent Office
Prior art keywords
pulse
data
address
bit lines
detecting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
EP88305509A
Other languages
German (de)
English (en)
French (fr)
Other versions
EP0296760A2 (en
EP0296760A3 (en
Inventor
Hiroaki Eva-Green-Katsura 4G Okuyama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Publication of EP0296760A2 publication Critical patent/EP0296760A2/en
Publication of EP0296760A3 publication Critical patent/EP0296760A3/en
Application granted granted Critical
Publication of EP0296760B1 publication Critical patent/EP0296760B1/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/414—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the bipolar type
    • G11C11/416—Read-write [R-W] circuits 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G11C11/419—Read-write [R-W] circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/18—Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals

Definitions

  • This invention relates to a static random access memory (RAM) circuit, especially a static RAM circuit in which the data stored in a memory cell is read out by detecting the transit of address signal level.
  • RAM static random access memory
  • Fig. 3 shows a block diagram of conventional static RAM circuit and Fig. 4 shows the timing chart thereof.
  • Address signals AD0, AD1 from the input terminals 1, 2 are supplied to an address decoder 3 and a detecting pulse generator 4.
  • the address decoder 3 is comprised of two inverter I1, I2 and four AND gates A1 - A4, and word line selection signals AD 0 ⁇ AD 1, AD 0 ⁇ AD1, AD0 ⁇ AD 1 and AD0 ⁇ AD1 from the AND gates A1, A2, A3 and A4 are supplied to one input terminal of AND gates A5, A6, A7 and A8 respectively. These word line selection signals select any one of a plurality of word lines sequentially.
  • the detecting pulse generator 4 is comprised of two detecting circuits D0, D1 and an OR gate O1.
  • the detecting circuit D0 detects a transit of the level of address signal AD0. That is, when the address signal AD0 changes from "H" level to "L” level or “L” level to “H” level, the detecting circuit D1 detects such transition and generates an address transit pulse (ATP0) as shown in Fig. 4.
  • the detecting circuit D1 detects a transit of the level of address signal AD1 as same as the detecting circuit D0 and generates an address transit pulse (ATP1).
  • an address transit pulse (ATP) is delivered from the OR gate O1 as shown in Fig. 4.
  • the pulse width of the address transit pulse (ATP) is equal to the sum of the pulse width of the address transit pulses ATP0 and ATP1.
  • a word line enable pulse generator 5 detects an end edge of the address transit pulse (ATP) and generates a word line enable pulse (WLE) as shown in Fig. 4.
  • the word line enable pulse (WLE) is supplied to another input terminal of the AND gates A5 - A8. Consequently, anyone of a plurality of word lines (a word line 6 in this case) selected by the AND gates A5 - A8 is enabled as shown in Fig. 4 "WL".
  • the word line enable pulse (WLE) is supplied to the data transfer circuit 7 and the sense amplifier 8. Therefore, these circuits 7, 8 are enabled at the same time when the selected word line 6 is enabled.
  • the data stored in the memory cell 9 is readout to a bit line 10a so that the difference of the signal level between a couple of bit lines 10a and 10b as shown in Fig. 4 "BL".
  • the level difference between the bit lines 10a, 10b is transferred to a sense amplifier 8 as a readout data through a data transfer circuit 7.
  • the data is amplified by the sense amplifier 8, and sense amplified outputs (SAO, SAO ) shown in Fig. 4 as "SAO" are supplied to an output buffer 11 and latched by the output buffer 11. After that the output data (DATA) is supplied to the output terminal 12.
  • Figs. 3 and 4 although only two address signals AD0, AD1 and only one memory cell 9 are shown. However, in a practical static RAM circuits, a plurality of memory cells are arranged in matrix, and a plurality of address signals are supplied to the input terminals so as to select necessary memory cells among a plurality of memory cells sequentially.
  • the word line enable pulse is generated by detecting the end edge of the address transit pulse (ATP).
  • the address signals AD0, AD1, etc.
  • the address signals AD0, AD1, etc.
  • skew the pulse timing of the address transit pulses
  • ATP the pulse timing of the address transit pulse
  • WLE the word line enable pulse
  • the word line enabling timing (i.e. term “t2" in Fig. 4 is not determined by the operation speed of the address decoder 3 but determined by that of the detecting pulse generator 4 and the word line anable pulse generator 5.
  • WLE word line enable pulse
  • ATP address transit pulse
  • EP-A-0 090 590 a static random access memory circuit comprising a plurality of memory cells for storing data arranged in matrix, a plurality of word lines for selecting said plurality of memory cells, a plurality of bit lines for transferring the data readout from said plurality of memory cells, data output means coupled to said plurality of bit lines for supplying the data transferred from said plurality of bit lines to output terminals, address decode means for decoding address signals and generating a plurality of word line selection signals for selecting any one of said plurality of word lines sequentially, detecting pulse generating means for detecting the transition of the level of said address signals and generating an address transition pulse, pulse generating means for generating a pulse by detecting a trailing edge of said address transition pulse, and means for enabling said data output means by said pulse.
  • the memory of this document connects the word line selection signals of the address decoder directly to the word lines.
  • the present invention provides a static random access memory circuit comprising: a plurality of memory cells for storing data arranged in matrix; a plurality of word lines for selecting said plurality of memory cells; a plurality of bit lines for transferring the data readout from said plurality of memory cells; data output means coupled to said plurality of bit lines for supplying the data transferred from said plurality of bit lines to output terminals; address decode means for decoding address signals and generating a plurality of word line selection signals for selecting any one of said plurality of word lines sequentially; detecting pulse generating means for detecting the transition of the level of said address signals and generating an address transition pulse; pulse generating means for generating a first pulse by detecting a leading edge of said address transit pulse; and means for selecting any one of said plurality of word lines by using one of said plurality of word line selection signals and for enabling said selected word line by said first pulse so that the data stored in the selected memory cells are readout to the corresponding bit lines from among said plurality of bit lines.
  • a static RAM circuit of this invention another enable pulse is generated by detecting an end edge of the address transit pulse (ATP), and said another enable pulse is supplied to a data output circuit coupled to the bit lines in a memory cell matrix so as to prevent from transferring the data readout by "skew” phenomenon and to transfer a data readout from a memory cell selected and enabled by a definite transition of an address signal.
  • ATP address transit pulse
  • Fig. 1 shows an embodiment of the static RAM circuit and Fig. 2 shows a timing chart of the static RAM circuit shown in Fig. 1.
  • the blocks given the reference number 1 - 4 and 6 - 12 have substantially the same function as that of a conventional static RAM circuit shown in Fig. 3.
  • Address signals AD0, AD1 are decoded by the address decoder 3, and word line selection signals are supplied to one input terminal of the AND gates A5, A6, A7 and A8 respectively for selecting anyone of a plurality of word lines sequentially.
  • the detecting pulse generator 4 detects transitions of the address signals AD0, AD1 and generates an address transit pulse (ATP).
  • Pulse generator 13 detects a start edge of the address transit pulse (ATP) and generates a word line enable pulse (WLE).
  • the pulse generator 13 detects an end edge of the address transit pulse (ATP) and generates a sense amplifier enable pulse (SAE) as shown in Fig. 2.
  • the word line anable pulse (WLE) is supplied to another input terminal of the AND gates A5, A6, A7 and A8.
  • WLE word line enable pulse
  • anyone of a plurality of word lines (word line 6 in this case) selected by the word line selection signals is enabled by the word line enable pulse (WLE).
  • WLE word line enable pulse
  • the pulse generator 13 generates the sense amplifier enable pulse (SAE) by detecting an end edge of the address transit pulse (ATP), and the data transfer circuit 7 and the sense amplifier 8 are enabled by the sense amplifier enable pulse (SAE).
  • SAE sense amplifier enable pulse
  • the word line 6 has been selected and enabled by the definite transition of the address signal as shown in Fig. 2 "WL”
  • the data stored in the memory cell 9 has been readout to the bit line 10a. Therefore, the level difference between a couple of the bit lines 10a, 10b is transferred to the sense amplifier 8 and amplified.
  • the sense amplifier outputs (SAO, SAO ) are supplied to the output buffer 11 and latched.
  • WLE word line enable pulse
  • SAE sense amplifier enable pulse
  • both the data transfer circuit 7 and the sense amplifier 8 are disabled, and the output signals (SAO, SAO ) of the sense amplifier 8 disappear.
  • the output data (DATA) supplied to the output terminal 12 is maintained after the extinction of the sense amplifier outputs (SAO, SAO ). Therefore, there are no waste of unnecessary current in the memory cells, the data transfer circuit 7 and the sense amplifier 8. Thus, the total current consumption is reduced.
  • the selected word line is enabled by the word line enable pulse (WLE) generated by detecting the start edge of the address transit pulse (ATP). Therefore, the term “t1" shown in Fig. 2 can be shorten, and thereby, it becomes possible to achieve a higher speed access operation.
  • the circuits such as the data transfer circuit 7 or the sense amplifier 8 which follow the bit lines 10a, 10b are enabled by the sense amplifier enable pulse (SAE) generated by the end edge of the address transit pulse (ATP). Accordingly, even if "skew” is caused, and the data stored in the memory cells are readout instantaneously, these transient data are prevented from transferring to the output buffer 11.
  • Figs. 1 and 2 as well as in Figs. 3 and 4, only two address signals AD0, AD1 and only one memory cell 9 are shown in order to simplify the construction and the operation.
  • a plurality of memory cells are arranged in matrix, and a plurality of address signals are supplied to the input terminals so as to select anyone of said plurality of memory cells sequentially.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Static Random-Access Memory (AREA)
EP88305509A 1987-06-22 1988-06-16 A static random access memory circuit Expired - Lifetime EP0296760B1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP154745/87 1987-06-22
JP62154745A JPH0812756B2 (ja) 1987-06-22 1987-06-22 スタチックｒａｍ回路

Publications (3)

Publication Number Publication Date
EP0296760A2 EP0296760A2 (en) 1988-12-28
EP0296760A3 EP0296760A3 (en) 1990-11-28
EP0296760B1 true EP0296760B1 (en) 1993-02-10

Family

ID=15590983

Family Applications (1)

Application Number Title Priority Date Filing Date
EP88305509A Expired - Lifetime EP0296760B1 (en) 1987-06-22 1988-06-16 A static random access memory circuit

Country Status (5)

Country Link
US (1) US4947379A (ja)
EP (1) EP0296760B1 (ja)
JP (1) JPH0812756B2 (ja)
KR (1) KR910009439B1 (ja)
DE (1) DE3878320T2 (ja)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2527050B2 (ja) * 1989-10-27 1996-08-21 日本電気株式会社 半導体メモリ用センスアンプ回路
JP2925600B2 (ja) * 1989-11-07 1999-07-28 富士通株式会社 半導体記憶装置
US5327394A (en) * 1992-02-04 1994-07-05 Micron Technology, Inc. Timing and control circuit for a static RAM responsive to an address transition pulse
JPH05325569A (ja) * 1992-05-27 1993-12-10 Toshiba Corp 半導体記憶装置
US5349566A (en) * 1993-05-19 1994-09-20 Micron Semiconductor, Inc. Memory device with pulse circuit for timing data output, and method for outputting data
KR0141933B1 (ko) * 1994-10-20 1998-07-15 문정환 저전력의 스테이틱 랜덤 억세스 메모리장치
KR0136668B1 (ko) * 1995-02-16 1998-05-15 문정환 메모리의 펄스 발생회로
JPH08293198A (ja) * 1995-04-21 1996-11-05 Nec Ic Microcomput Syst Ltd 半導体記憶装置
JPH09282889A (ja) * 1996-04-09 1997-10-31 Toshiba Corp 半導体装置
KR100218307B1 (ko) * 1996-07-01 1999-09-01 구본준 반도체 메모리소자의 칼럼디코딩회로
KR100253282B1 (ko) * 1997-04-01 2000-05-01 김영환 메모리소자의소모전력자동감소회로
SE514107C2 (sv) * 1999-05-05 2001-01-08 Valmet Karlstad Ab Arrangemang för positionering av en värmare vid en vals och en pressanordning med ett sådant arrangemang
US7000065B2 (en) * 2002-01-02 2006-02-14 Intel Corporation Method and apparatus for reducing power consumption in a memory bus interface by selectively disabling and enabling sense amplifiers
KR100439839B1 (ko) * 2002-05-31 2004-07-12 주식회사 한일농원 닭고기 육포의 제조방법
US20040128416A1 (en) * 2002-12-11 2004-07-01 Tsvika Kurts Apparatus and method for address bus power control
US7152167B2 (en) * 2002-12-11 2006-12-19 Intel Corporation Apparatus and method for data bus power control
KR100642759B1 (ko) * 2005-01-28 2006-11-10 삼성전자주식회사 선택적 리프레쉬가 가능한 반도체 메모리 디바이스
KR100761848B1 (ko) * 2006-06-09 2007-09-28 삼성전자주식회사 반도체 장치에서의 데이터 출력장치 및 방법
US8279659B2 (en) * 2009-11-12 2012-10-02 Qualcomm Incorporated System and method of operating a memory device

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58169383A (ja) * 1982-03-30 1983-10-05 Fujitsu Ltd 半導体記憶装置
JPS5954093A (ja) * 1982-09-21 1984-03-28 Toshiba Corp 半導体記憶装置
JPS5963094A (ja) * 1982-10-04 1984-04-10 Fujitsu Ltd メモリ装置
JPS60154709A (ja) * 1984-01-25 1985-08-14 Toshiba Corp クロツク信号発生回路
JPS60254485A (ja) * 1984-05-31 1985-12-16 Nec Corp スタテイツク型半導体記憶装置
US4712194A (en) * 1984-06-08 1987-12-08 Matsushita Electric Industrial Co., Ltd. Static random access memory
JPS6124091A (ja) * 1984-07-12 1986-02-01 Nec Corp メモリ回路
US4728820A (en) * 1986-08-28 1988-03-01 Harris Corporation Logic state transition detection circuit for CMOS devices

Also Published As

Publication number Publication date
EP0296760A2 (en) 1988-12-28
KR890001091A (ko) 1989-03-18
DE3878320T2 (de) 1993-05-27
KR910009439B1 (ko) 1991-11-16
US4947379A (en) 1990-08-07
JPH0812756B2 (ja) 1996-02-07
JPS63318000A (ja) 1988-12-26
EP0296760A3 (en) 1990-11-28
DE3878320D1 (de) 1993-03-25

Similar Documents

Publication Publication Date Title
EP0296760B1 (en) A static random access memory circuit
US6556472B2 (en) Static RAM with optimized timing of driving control signal for sense amplifier
EP0107415B1 (en) A static memory circuit
KR910003382B1 (ko) 레지스터를 구비한 반도체 메모리 장치
EP0186906A2 (en) Semiconductor memory attaining high data read speed and having high noise margin
US6333881B1 (en) Semiconductor memory
JPH08195085A (ja) データメモリ内のセンス増幅
US6388937B2 (en) Semiconductor memory device
US7599237B2 (en) Memory device and method for precharging a memory device
US5268874A (en) Reading circuit for semiconductor memory
EP0226616B1 (en) Asynchronous row and column control
KR19980025009A (ko) 스태틱형 반도체 메모리 소자
JPH07211077A (ja) 半導体記憶装置
US6219283B1 (en) Memory device with local write data latches
JPH07201179A (ja) 半導体メモリ・システム
JPS62293596A (ja) 連想記憶装置
EP0547890A2 (en) A read/write memory with interlocked write control
KR910014938A (ko) 향상된 di/dt 제어가 가능한 집적회로 메모리
US6067264A (en) High speed semiconductor memory device
KR100388317B1 (ko) 반도체메모리소자
KR100305648B1 (ko) 고속동작용디램
US6414879B1 (en) Semiconductor memory device
EP1193714B1 (en) High-speed bank select multiplexer latch
EP0199458B1 (en) Memory circuit having an improved writing scheme
EP0714100A2 (en) Synchronous memory device

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

AK Designated contracting states

Kind code of ref document: A2

Designated state(s): DE FR GB

PUAL Search report despatched

Free format text: ORIGINAL CODE: 0009013

AK Designated contracting states

Kind code of ref document: A3

Designated state(s): DE FR GB

17P Request for examination filed

Effective date: 19910219

17Q First examination report despatched

Effective date: 19920413

GRAA (expected) grant

Free format text: ORIGINAL CODE: 0009210

AK Designated contracting states

Kind code of ref document: B1

Designated state(s): DE FR GB

REF Corresponds to:

Ref document number: 3878320

Country of ref document: DE

Date of ref document: 19930325

ET Fr: translation filed
PLBE No opposition filed within time limit

Free format text: ORIGINAL CODE: 0009261

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT

26N No opposition filed
REG Reference to a national code

Ref country code: GB

Ref legal event code: IF02

REG Reference to a national code

Ref country code: GB

Ref legal event code: 732E

REG Reference to a national code

Ref country code: FR

Ref legal event code: TP

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: DE

Payment date: 20070614

Year of fee payment: 20

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: GB

Payment date: 20070613

Year of fee payment: 20

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: FR

Payment date: 20070608

Year of fee payment: 20

REG Reference to a national code

Ref country code: GB

Ref legal event code: PE20

Expiry date: 20080615

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: GB

Free format text: LAPSE BECAUSE OF EXPIRATION OF PROTECTION

Effective date: 20080615