EP0255125B1 - Integrated circuit having two circuit blocks therein independently energized through different power supply terminals - Google Patents

Integrated circuit having two circuit blocks therein independently energized through different power supply terminals Download PDF

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Publication number
EP0255125B1
EP0255125B1 EP87111006A EP87111006A EP0255125B1 EP 0255125 B1 EP0255125 B1 EP 0255125B1 EP 87111006 A EP87111006 A EP 87111006A EP 87111006 A EP87111006 A EP 87111006A EP 0255125 B1 EP0255125 B1 EP 0255125B1
Authority
EP
European Patent Office
Prior art keywords
power supply
diode
circuit
supply terminals
terminals
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
EP87111006A
Other languages
German (de)
English (en)
French (fr)
Other versions
EP0255125A2 (en
EP0255125A3 (en
Inventor
Kazuki Yoshitake
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Publication of EP0255125A2 publication Critical patent/EP0255125A2/en
Publication of EP0255125A3 publication Critical patent/EP0255125A3/en
Application granted granted Critical
Publication of EP0255125B1 publication Critical patent/EP0255125B1/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0255—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements

Definitions

  • This invention relates to a semiconductor integrated circuit having at least two circuit blocks therein which are independently energized through different power supply terminals and, more particularly, to a protection structure incorporated therein against an application of abnormally high electrostatic voltage to signal terminals.
  • a semiconductor integrated circuit having plural number of circuit blocks each including an electric circuit of MOS field effect transistors
  • power is supplied to energize respective circuit blocks through different power supply terminals which are allocated to the respective circuit blocks and formed on the same IC chip.
  • This structure is advantageous in suppressing noise on power wiring that is generated by a current flowing through the power supply wiring and an impedance thereof.
  • the separated power supply terminals decrease the current flowing through each power supply wiring to reduce the voltage change on the power supply wiring based on a change in the current. Such voltage change is applied to the circuit block as noise.
  • either high or low power voltage terminals are respectively connected to different power wirings, and the remaining power voltage terminals are connected through semiconductor substrate.
  • the chip is provided with signal terminals such as input terminals and output terminals which are mainly protected from applicable electrostatic charges by gate protection diodes connected between the respective signal terminals and the power terminals.
  • the resistance of the semiconductor substrate in the discharging path is from several hundreds ohms to several tens kilo-ohms to prolong the time of discharge.
  • the resistance of the substrate generates a large voltage drop, and produces a large difference in electric potential on the substrate. Therefore, a large voltage is applied to gate insulator films of MOS field effect transistors connected to the signal terminal and breaks them down.
  • a low impedance discharging path between power terminals of different circuit blocks.
  • Such a low impedance discharging path may include a pair of diodes connected in forward and reverse directions between the power supply terminals.
  • a semiconductor integrated circuit includes a semiconductor body, at least two circuit blocks formed in the semiconductor body, each of the circuit blocks having two power supply terminals and at least one signal terminal for receiving an input signal, respective ones of the two power supply terminals in different circuit blocks being coupled through first and second diodes so connected between these two power supply terminals that an anode of the first diode and a cathode of the second diode are connected in common and a cathode of the first diode and an anode of the second diode are connected in common.
  • Additional parallel connection of third and fourth diodes with an anode of the third diode and a cathode of the fourth diode being connected in common and a cathode of the third diode and an anode of the fourth diode being connected in common may be inserted between the respective others of the two power supply terminals in different circuit blocks.
  • Power protection diodes having such a breakdown voltage that circuit elements can be protected from voltages applicable between two power supply terminals may be respectively connected between the two power supply terminals in the same circuit block.
  • Gate protection diodes may be inserted between the signal terminals and the power supply terminals.
  • the parallel connection of first and second diodes is connected between two power supply terminals which are electrically coupled through the semiconductor body, that is, a semiconductor substrate or a well region formed in the substrate. Therefore, if a large number of electrostatic charges flow between power supply or signal terminals in different circuit blocks, a voltage generated by the impedance of the semiconductor body is limited by the parallel connection of the first and second diodes. Thus, a high voltage is not produced in the integrated circuit by the electrostatic charges and therefore circuit elements in the integrated circuit are protected from being broken-down.
  • a MOS integrated circuit having two independent circuit blocks has the circuit blocks 2 and 3 on a single semiconductor substrate 1.
  • the circuit blocks 2 and 3 separately has positive power supply terminals 6 and 8, ground or negative power supply terminals 7 and 8, and several signal terminals 5 and 10.
  • the power supply terminals 6 and 8 and the power supply terminals 7 and 9 are not respectively connected to each other.
  • the power supply terminals 6 and 8 or the power supply terminals 7 and 9 are generally connected through the semiconductor substrate 1.
  • the power supply terminals 6 and 8 are connected through the semiconductor substrate 1 which is equivalently shown by the resistor 4 which is a resistance component of the semiconductor substrate 1.
  • the signal terminals 5 and 10 are respectively connected to the power supply terminals 6 and 7 and the power supply terminals 8 and 9 through gate protection diodes 14-1 and 13-1 and gate protection diodes 14-2 and 13-2, respectively.
  • the equivalent circuit of the terminals 5 to 10, the resistor 4 and the gate protection diodes 13-1, 13-2, 14-1 and 14-2 is shown in Fig. 2.
  • the preferred embodiment of the present invention has two separate circuit blocks 2 and 3 made of P-channel type and N-channel type MOS field effect transistors, on the semiconductor substate 1, as shown in Fig. 3.
  • the circuit block 2 has a power supply terminal 6, a ground terminal 7 and several signal terminals (only an input terminal 5 is shown in Fig. 3).
  • the other circuit block 3 also has a power supply terminal 8, a ground terminal 9 and several signal terminals (only an input terminal 10 is shown in Fig. 3).
  • the same power voltages are separately supplied to the power supply terminals 6 and 8. This separate power supply is effective for preventing a generation of noise in response to a large power current. Wiring for power supply has some impedance component.
  • the input terminals 5 and 10 are respectively connected to the power terminals 6 and 8 through gate protection diodes 14-1 and 14-2 and further connected to the ground terminals 7 and 9 through gate protection diodes 13-1 and 13-2, respectively.
  • Those gate protection diodes protect MOS field effect transistors having gates connected to the input terminals 5 and 10 from dielectric breakdown of their gate insulator films.
  • the ground terminals 7 and 9 are electrically separated on the semiconductor substrate 1.
  • the power source terminals 6 and 8 are also separated in circuit diagram but are coupled through the semiconductor substrate 1.
  • the resistance component of the substrate 1 between the power supply terminals 6 and 8 is shown with a resistor 4.
  • the integrated circuit shown in Fig. 3 has two additional protections.
  • One is a protection from applying abnormally high voltage between the power supply terminal and the ground terminal in the same circuit block.
  • power protection diodes 12-1 and 12-2 having a breakdown voltage a little higher than a power source voltage are respectively connected between the power supply terminal 6 and the ground terminal 7 and between the power supply terminal 8 and the ground terminal 9.
  • the other is a protection of circuit element from being damaged when electrostatic charges discharge between terminals in different circuit blocks.
  • parallel connections 11 and 11' of the diodes are respectively connected between the power supply terminals 6 and 8 and between the ground terminals 7 and 9.
  • anode and cathode of one diode are respectively connected with cathode and anode of the other diode. The function of those parallel connections 11 and 11' will be described in the latter.
  • the equivalent circuit of the diodes shown in Fig. 3 and the resistor 4 is shown in Fig. 4 with terminals 5 to 10.
  • the parallel connection 11 is inserted in parallel with the resistor 4 which is the resistance component of the semiconductor substrate 1 between the power supply terminals 6 and 8.
  • the other parallel connection 11' is inserted between the ground terminals 7 and 9.
  • the diode 12-1 is inserted between the power source terminal 6 and the ground terminal 7 in parallel with a series connection of the gate protection diodes 13-1 and 14-1.
  • the other diode 12-2 is also inserted between the power source terminal 8 and the ground terminal 9 in parallel with a series connection of the gate protection diodes 13-2 and 14-2.
  • the input terminals 5 and 10 are respectively connected at a connecting point of the gate protection diodes 13-1 and 14-1 and another connecting point of the gate protecting diodes 13-2 and 14-2.
  • All terminals 5 to 10 are in electrically floating condition, before the integrated circuit is mounted on electrical apparatus. Electrical charges may be applied to any of the terminals 5 to 10 and discharge through the integrated circuit to any other terminal. If such electrostatic charges are applied to the power supply terminal 6 and discharge to the other power supply terminal 8, the charges bypass the resistor 4 which is a resistance component of the semiconductor substrate by flowing through the parallel connection 11. The charges flow through one of diodes in the parallel connection 11 in a forward direction with a low impedance. Thus charges quickly discharge. Moreover, the forward biased diode clamps the voltage between the power supply terminals 6 and 8. Any large voltage is not produced in the integrated circuit. Thus, the applied electrostatic charges are quickly discharged without damaging any circuit element in the integrated circuit. The above-explained discharge is equally applicable to the case where electrostatic charges are applied to one of the ground terminals 7 and 9 and discharge to the other of them.
  • first of such routes is the gate protection diode 13-1 - the parallel connection 11' - the gate protection diode 13-2.
  • Second is the gate protection diode 14-1 - the parallel connection 11 - the gate protection diode 14-2.
  • the gate protection diodes 13-1 and 14-2 break down with a low voltage and show a low impedance.
  • One of diodes in the parallel connection 11 is forward biased by the discharge flow, similar to one of diodes in the other connection 11'.
  • the voltage between input terminals 5 and 10 is clamped at a total voltage of a breakdown voltage of the gate protection diode 13-1 or 14-2 and two forward biased voltage of one diode in the parallel connection 11' or 11 and the gate protection diode 14-1 or 13-2.
  • the impedance between the input terminals 5 and 10 is small, due to the breakdown of the gate protection diode 13-1 or 14-2 and the forward bias of other diodes. Thus, charges quickly discharge without damaging any circuit element in the integrated circuit.
  • the third of such discharging route is the gate protection diode 14-1 - the parallel connection 11 - the power protection diode 12-2 - the gate protection diode 13-2.
  • the fourth is the gate protection diode 14-1 - the power protection diode 12-1 - the parallel connection 11' - the gate protection diode 13-2.
  • the power protection diodes 12-1 and 12-2 break down at a voltage a little higher than the power voltage and shows a low impedance.
  • the charges quickly discharge with a voltage of the breakdown voltage of the power protection diode 12-1 or 12-2 and two forward biased voltage between the input terminals 5 and 10.
  • the parallel connections 11 and 11' and the power protection diodes 12-1 and 12-2 may be formed in a semiconductor device 51, as shown in Fig. 5.
  • An N-type silicon substrate 51 having an impurity concentration of 1015 ⁇ 1016 cm ⁇ 3 is used.
  • Two P-type well regions 52 and 53 are formed with an impurity concentration of 1016 ⁇ 1017 cm ⁇ 3.
  • Those P-type well regions 52 and 53 are exclusively used for forming the parallel connection 11'.
  • N+-type regions 61 and 64 to 66 are formed on the substrate 51 and N+-type regions 62 and 63 are on the P-type well regions 52 and 53.
  • Those N+-type regions 61 to 66 are formed with an impurity concentration of about 1020 cm ⁇ 3.
  • P+-type regions 71 and 74 to 76 are formed an the substrate 51 and P+-type regions 72 and 73 are on the P-type well regions 52 and 53. Those P+-type regions 71 to 76 are formed with an impurity concentration of about 1020 cm ⁇ 3.
  • the N+-type region 61 surrounds the P+-type region 71 to form the power protection diode 12-1.
  • the N+-type region 66 surround the P+-type region 76 to form the power protection diode 12-2.
  • the N+-type regions 64 and 65 respectively surround the P+-type regions 74 and 75 to form diodes in the parallel connection 11.
  • the P+-type regions 72 and 73 respectively surround the N+-type regions 62 and 63 to form diodes in the parallel connection 11'.
  • Wirings for forming the circuit shown in Fig. 3 are made with aluminum layer 54 formed on an insulator cover film 55 having openings on the N+-type regions 61 to 66 and the P+-type regions 71 to 76.
  • the parallel connection 11' connected between the ground terminals 7 and 9 may be removed.
  • the discharging routes of applied electrostatic charges is limited, but the features of quick discharge without producing large voltage are equally achieved by the remaining parallel connection 11. That is, the features of the present invention is achieved by the parallel connection inserted between power terminals which are coupled through the substrate or well-region formed therein.
  • the above-explained embodiment uses the power supply terminals 6 and 8 and the ground terminals 7 and 9, the electrical power may be supplied through positive and negative power supply terminals or positive, ground and negative power supply terminals.
  • one of the power supply terminals including ground terminals in one circuit block is arranged to couple with corresponding one power supply terminal in different circuit block with an arrangement of a parallel connection of diodes connected between the one and the corresponding one of power supply terminals.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
EP87111006A 1986-07-30 1987-07-29 Integrated circuit having two circuit blocks therein independently energized through different power supply terminals Expired - Lifetime EP0255125B1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP180354/86 1986-07-30
JP61180354A JPH0693497B2 (ja) 1986-07-30 1986-07-30 相補型ｍｉｓ集積回路

Publications (3)

Publication Number Publication Date
EP0255125A2 EP0255125A2 (en) 1988-02-03
EP0255125A3 EP0255125A3 (en) 1990-11-22
EP0255125B1 true EP0255125B1 (en) 1993-02-10

Family

ID=16081770

Family Applications (1)

Application Number Title Priority Date Filing Date
EP87111006A Expired - Lifetime EP0255125B1 (en) 1986-07-30 1987-07-29 Integrated circuit having two circuit blocks therein independently energized through different power supply terminals

Country Status (4)

Country Link
US (1) US4855863A (ja)
EP (1) EP0255125B1 (ja)
JP (1) JPH0693497B2 (ja)
DE (1) DE3784114T2 (ja)

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EP0378613A1 (en) * 1988-06-01 1990-07-25 Anamartic Limited Wafer scale integrated circuits
EP0348895B1 (en) * 1988-06-27 1995-05-17 Nec Corporation Semiconductor memory device provided with low-noise power supply structure
JP2806532B2 (ja) * 1988-09-28 1998-09-30 日本電気アイシーマイコンシステム株式会社 半導体集積回路装置
JPH02111064A (ja) * 1988-10-20 1990-04-24 Nec Corp モノリシックｉｃの静電破壊保護回路
JP2752680B2 (ja) * 1989-01-20 1998-05-18 日本電気アイシーマイコンシステム株式会社 半導体集積回路装置の過電圧吸収回路
US5343352A (en) * 1989-01-20 1994-08-30 Nec Corporation Integrated circuit having two circuit blocks energized through different power supply systems
US5200876A (en) * 1989-04-10 1993-04-06 Matsushita Electric Industrial Co., Ltd. Electrostatic breakdown protection circuit
JP2855692B2 (ja) * 1989-09-06 1999-02-10 ソニー株式会社 Ｃｃｄ装置
JP2619119B2 (ja) * 1990-06-21 1997-06-11 株式会社東芝 半導体集積回路
EP0464751A3 (en) * 1990-07-06 1992-07-22 Kabushiki Kaisha Toshiba Semiconductor device with protection circuit
JPH0494568A (ja) * 1990-08-10 1992-03-26 Nec Ic Microcomput Syst Ltd 半導体集積回路装置
AU8529591A (en) * 1990-08-27 1992-03-17 Power Management International Solid state circuit interrupter and circuit breaker
JP3375659B2 (ja) * 1991-03-28 2003-02-10 テキサス インスツルメンツ インコーポレイテツド 静電放電保護回路の形成方法
KR930001392A (ko) * 1991-06-19 1993-01-16 김광호 반도체 메모리 장치의 전원 접지선 배선방법
US5204554A (en) * 1991-12-06 1993-04-20 National Semiconductor Corporation Partial isolation of power rails for output buffer circuits
US5272097A (en) * 1992-04-07 1993-12-21 Philip Shiota Method for fabricating diodes for electrostatic discharge protection and voltage references
US5591661A (en) * 1992-04-07 1997-01-07 Shiota; Philip Method for fabricating devices for electrostatic discharge protection and voltage references, and the resulting structures
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JP3276996B2 (ja) * 1992-09-09 2002-04-22 株式会社東芝 保護回路
TW282598B (ja) 1995-02-22 1996-08-01 Fujitsu Ltd
DE19507313C2 (de) * 1995-03-02 1996-12-19 Siemens Ag Halbleiterbauelement mit Schutzstruktur zum Schutz vor elektrostatischer Entladung
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JP2001244418A (ja) * 2000-03-01 2001-09-07 Nec Corp 半導体集積回路装置
JP4215482B2 (ja) 2002-10-22 2009-01-28 Ｎｅｃエレクトロニクス株式会社 静電保護回路及び半導体装置
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JP2005049637A (ja) * 2003-07-29 2005-02-24 Seiko Epson Corp 駆動回路及びその保護方法、電気光学装置並びに電子機器
GB2445327B (en) * 2004-02-07 2008-08-13 Samsung Electronics Co Ltd Buffer circuit having electrostatic discharge protection
WO2005076354A1 (en) * 2004-02-07 2005-08-18 Samsung Electronics Co., Ltd. Buffer circuit having electrostatic discharge protection
US7876302B2 (en) 2004-07-26 2011-01-25 Seiko Epson Corporation Driving circuit for electro-optical panel and driving method thereof, electro-optical device, and electronic apparatus having electro-optical device
JP5006580B2 (ja) 2006-05-31 2012-08-22 ルネサスエレクトロニクス株式会社 保護回路を備える半導体装置
US7362555B2 (en) * 2006-08-26 2008-04-22 Taiwan Semiconductor Manufacturing Co., Ltd. ESD protection circuit for a mixed-voltage semiconductor device
US7952844B2 (en) * 2007-06-20 2011-05-31 United Microelectronics Corp. Electrostatic discharge immunizing circuit without area penalty
JP2009105721A (ja) * 2007-10-24 2009-05-14 New Japan Radio Co Ltd レベルシフト回路
JP5175597B2 (ja) * 2007-11-12 2013-04-03 エスケーハイニックス株式会社 半導体集積回路
KR101211683B1 (ko) * 2008-12-31 2012-12-12 에스케이하이닉스 주식회사 반도체 집적회로
CN102208407A (zh) * 2010-03-31 2011-10-05 上海宏力半导体制造有限公司 复合电源电路以及双向晶闸管
CN110086434A (zh) * 2019-02-28 2019-08-02 厦门优迅高速芯片有限公司 一种提升跨阻放大电路中rssi脚抗噪能力的电路

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SE455552B (sv) * 1985-02-26 1988-07-18 Asea Ab Halvledaranordning innefattande en overspenningsskyddskrets
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US4736271A (en) * 1987-06-23 1988-04-05 Signetics Corporation Protection device utilizing one or more subsurface diodes and associated method of manufacture

Also Published As

Publication number Publication date
DE3784114T2 (de) 1993-06-09
US4855863A (en) 1989-08-08
JPH0693497B2 (ja) 1994-11-16
JPS6336557A (ja) 1988-02-17
DE3784114D1 (de) 1993-03-25
EP0255125A2 (en) 1988-02-03
EP0255125A3 (en) 1990-11-22

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