EP0178170B1 - Semiconductor device having a bonding wire and method for manufacturing it - Google Patents

Semiconductor device having a bonding wire and method for manufacturing it Download PDF

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Publication number
EP0178170B1
EP0178170B1 EP85307236A EP85307236A EP0178170B1 EP 0178170 B1 EP0178170 B1 EP 0178170B1 EP 85307236 A EP85307236 A EP 85307236A EP 85307236 A EP85307236 A EP 85307236A EP 0178170 B1 EP0178170 B1 EP 0178170B1
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EP
European Patent Office
Prior art keywords
bonding wire
copper
bonding
lead
lead frame
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
EP85307236A
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German (de)
English (en)
French (fr)
Other versions
EP0178170A2 (en
EP0178170A3 (en
Inventor
Hiroyuki C/O Patent Division Baba
Takashi C/O Patent Division Matsuzaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
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Toshiba Corp
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Publication of EP0178170A2 publication Critical patent/EP0178170A2/en
Publication of EP0178170A3 publication Critical patent/EP0178170A3/en
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Publication of EP0178170B1 publication Critical patent/EP0178170B1/en
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    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K20/00—Non-electric welding by applying impact or other pressure, with or without the application of heat, e.g. cladding or plating
    • B23K20/22—Non-electric welding by applying impact or other pressure, with or without the application of heat, e.g. cladding or plating taking account of the properties of the materials to be welded
    • B23K20/233—Non-electric welding by applying impact or other pressure, with or without the application of heat, e.g. cladding or plating taking account of the properties of the materials to be welded without ferrous layer
    • B23K20/2333—Non-electric welding by applying impact or other pressure, with or without the application of heat, e.g. cladding or plating taking account of the properties of the materials to be welded without ferrous layer one layer being aluminium, magnesium or beryllium
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    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00011—Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01007—Nitrogen [N]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01018—Argon [Ar]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01028—Nickel [Ni]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01327—Intermediate phases, i.e. intermetallics compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/157—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2924/15738—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950 C and less than 1550 C
    • H01L2924/15747—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/20—Parameters
    • H01L2924/207—Diameter ranges
    • H01L2924/2076—Diameter ranges equal to or larger than 100 microns
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S228/00—Metal fusion bonding
    • Y10S228/904—Wire bonding
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49121—Beam lead frame or beam lead device

Definitions

  • the present invention relates to a method of manufacturing a semiconductor device.
  • the invention relates to the manufacture of a semiconductor device in which one end of a bonding wire whose other end is connected to a bonding pad of a semiconductor element is in good connection to a lead frame and which displays excellent electrical properties in high temperature conditions or in high temperature, high humidity conditions.
  • a Ni plating layer 2 is formed on the surface of a lead electrode 1 made of copper, etc. and a bonding pad 5 on a semiconductor element 4 and the lead electrode 1 are connected via this Ni plating layer 2 by a bonding wire 3.
  • the semiconductor element 4 is mounted on a solder layer 7 formed on a Ni plating layer 9 on a lead frame 8.
  • the bonding wire 3, the bonding pad 5, the semiconductor element 4, the solder layer 7, and parts of the lead electrode 1 with its plating layer 2 and the lead frame 8 with its plating layer 9 are surrounded by a resin sealing body 6.
  • Japanese Patent Application No. 57-51237 discloses a bonding process technique in which a ball of required shape is formed and bonding oxidation is prevented by introducing a capillary end portion leading out from a bonding wire under a cover where a reducing atmosphere is maintained.
  • this technique requires a complex structure including a cover for maintaining a reducing atmosphere and when the bonding process is effected at a process speed of one second or less there is the problem that maintenance and control are troublesome since faults occur easily.
  • Document EP-A-0116844 is concerned with the addition of Ni to a copper frame to reduce the thickness of the intermetallic layer.
  • reference is made to an arrangement in which the intermetallic layer has a thickness of more than 0.2 micron.
  • a method of manufacturing a semiconductor device comprising a step wherein one end of bonding wire is connected to a bonding pad of a semiconductor element mounted on a lead frame of copper or a copper alloy and its other end is connected to a lead electrode of said lead frame, characterised in that said bonding wire is of aluminium and said other end of the bonding wire is fused to said lead electrode and in that heat treatment of the fusion connection consists of heating effected with said lead electrode held between heater elements and is effected to make the thickness of the reaction layer formed by said copper or copper alloy and aluminium 0.2 (micron) or more.
  • a semiconductor device manufactured in accordance with the method of this invention displays excellent electrical characteristics in high temperature conditions or in high temperature, high humidity conditions thanks to the connection of an end portion of the aluminium bonding wire to the lead electrode of copper or copper alloy in a manner such that the reaction layer thickness is made 0.2 (micron) or more.
  • a semiconductor element 22 is mounted on a mount portion of a lead frame 20 made of copper or copper alloy via a solder layer 21.
  • the copper alloy employed here may be phosphor bronze or be another copper alloy containing iron.
  • one end of 200 (microns) q) bonding wire 23 made of 99.99% pure aluminium is fused to a bonding pad 24 on the semiconductor element 22 by ultrasonic bonding process.
  • the other end of the bonding wire 23 is similarly fused by ultrasonic bonding process to a lead electrode 25 of the lead frame 20.
  • the lead electrode 25 also is formed copper or a copper alloy.
  • heat treatment is effected to make the thickness of the aluminium and copper or copper alloy reaction layer formed at the portion where the bonding wire 23 and lead electrode 25 are fused together 0.2 (micron) or more.
  • heaters 40 and 42 with a temperature of about 600°C hold the lead electrode 25 from above and below and transfer heat at a location where the lead frame 20 has been advanced to position I. Successive shifts of the lead frame 20 from the left towards the right as seen in Fig. 4 are effected about once every 1.2-1.3 second. That is, one-time contact of the heater 40 gives insufficient transfer of heat for formation of a reaction layer of 0.2 (micron) or more and so formation of a reaction layer with a thickness of 0.2 (micron) or more is brought about by the provision of heaters in a number of places combined with shifts of the lead frame 20.
  • Fig. 4 illustrates the case where there are two places, I and II.
  • the heater contact time is about 0.5 seconds and heaters are provided in five places.
  • Fig. 5 shows a cross-section of the state of Fig. 4 seen from the side.
  • the lead frame 20 is set on a pedestal 50, which is provided with a blow hole 52 for a mixed gas containing nitrogen for cooling the lead frame 20. This is in order to prevent melting of the solder layer 21 due to the lead frame 20 being heated by the heaters 40 and 42 as well as the lead electrode 25.
  • An air atmosphere may be used for the heat treatment but since the copper or copper alloy frame is oxidized as heating proceeds it is preferable to have a non-oxidizing atmosphere or a reducing atmosphere.
  • use is made of a mixed gas containing 90% N 2 and 10% H 2 .
  • the non-oxidizing gas employed here may be inert gas, be reducing gas or be mixed gas thereof.
  • the inert gas may be argon or helium and the reducing gas may be hydrogen.
  • Fig. 6 shows the relation between time and temperature for reaction layer formation.
  • the temperature of the bonding portion 26 is set at 400-450°C and heating treatment is effected to give a total amount of intermittent heating time of about 5 seconds. Heating is not limited to being intermittent heating, it being simply necessary to have a total heating time of about 5 seconds.
  • composition of the reaction layer is inferred to be AI 2 Cu, AICu.
  • mold treatment is effected to give a semiconductor device 30 in which the semiconductor element 22, lead frame 20, bonding wire 23 and lead electrode 25, etc. are sealed as an integral unit in resin sealing body 27.
  • connection of the bonding wire 23 and lead electrode 25 is effected with formation of a reaction layer that is 0.2 (micron) or more in the semiconductor device 30 thus produced, it is made possible to prevent opening faults in the bonding wire 23 and lead electrode 25 bond portion even in high temperature conditions or high temperature, high humidity conditions, and as a result there is produced a highly reliable semiconductor device 30. Also, the manufacturing process is simplified and manufacturing costs can be reduced since there is no need to effect plating treatment on the lead frame 20 and lead electrode 25.
  • the reason for making the thickness of the reaction layer formed by the aluminium and copper or copper alloy 0.2 (micron) or more is that, as is made clear from the test examples described below, products that are rejects because of opening faults occur in high temperature conditions or high temperature, high humidity conditions if the thickness is less than 0.2 (micron).
  • semiconductor elements 22 were mounted in a non-oxidizing atmosphere on lead frames 20 of copper or copper alloy on which plating layers had not been formed and then aluminium bonding wires 23 bridging bonding pads 24 of the semiconductor elements 22 and lead electrodes 25 of lead frames 20 were attached by ultrasonic bonding process.
  • mold treatment of these assemblies was effected to give semiconductor devices (Test Products 1).
  • no plating layer was formed on the surface of the lead electrodes 25 and there was no reaction layer present between the bonding wires 23 and the lead electrodes 25.
  • Test Products 2 Semiconductor devices constituting Test Products 2 were manufactured by mounting semiconductor elements 22 and bonding bonding wires 23 and lead electrodes in the same way as for Test Products 1 after thorough reduction of the lead frames 20 in a high temperature reducing atmosphere.
  • reaction layers 60 were formed between the bonding wires 23 and lead electrodes 25 as shown in Fig. 9 by heat treatment following connection of the bonding wires 23 and lead electrodes 25.
  • devices with a reaction layer 60 thickness of 0.1 (micron) or less were taken as Test Products 3, devices with 0.2-0.5 (micron) as Test Products 4, devices with 0.5-1 (micron) as Test Products 5 and devices with 1-2 (microns) as Test Products 6.
  • Test Products 3 Semiconductor devices produced in the same way as Test Products 2 after preliminary formation of Ni plating layers 70 on the lead frames 20 and lead electrodes 25 as shown in Fig. 10 were taken as Test Products 3.
  • High temperature shelf tests consisting of 500 hours, 1000 hours, 1500 hours, 2000 hours and 2500 hours or more at 150°C and 300 hours, 500 hours, 1000 hours and 1500 hours or more at 175°C were conducted on 20 each of the semiconductor device Test Products 1-7 produced in the abovedescribed manner. Investigation of occurrence of rejects because of opening faults between bonding wires 23 and lead electrodes 25 gave the results noted in the following table.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Mechanical Engineering (AREA)
  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)
EP85307236A 1984-10-09 1985-10-09 Semiconductor device having a bonding wire and method for manufacturing it Expired - Lifetime EP0178170B1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP211960/84 1984-10-09
JP59211960A JPS6189643A (ja) 1984-10-09 1984-10-09 半導体装置及びその製造方法

Publications (3)

Publication Number Publication Date
EP0178170A2 EP0178170A2 (en) 1986-04-16
EP0178170A3 EP0178170A3 (en) 1987-03-25
EP0178170B1 true EP0178170B1 (en) 1991-01-02

Family

ID=16614547

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Application Number Title Priority Date Filing Date
EP85307236A Expired - Lifetime EP0178170B1 (en) 1984-10-09 1985-10-09 Semiconductor device having a bonding wire and method for manufacturing it

Country Status (6)

Country Link
US (1) US4891333A (ja)
EP (1) EP0178170B1 (ja)
JP (1) JPS6189643A (ja)
KR (1) KR900000439B1 (ja)
CN (1) CN85107077B (ja)
DE (1) DE3581039D1 (ja)

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US5229646A (en) * 1989-01-13 1993-07-20 Mitsubishi Denki Kabushiki Kaisha Semiconductor device with a copper wires ball bonded to aluminum electrodes
JPH0817189B2 (ja) * 1989-01-13 1996-02-21 三菱電機株式会社 半導体装置の製造方法
IT1233008B (it) * 1989-09-21 1992-03-14 Sgs Thomson Microelectronics Dispositivo integrato con connessioni perfezionate fra i terminali e la piastrina di materiale semiconduttore integrante componenti elettronici
US5156999A (en) * 1990-06-08 1992-10-20 Wai-Hon Lee Packaging method for semiconductor laser/detector devices
FR2678773B1 (fr) * 1991-07-05 1997-03-14 Thomson Csf Procede de cablage entre des sorties de boitier et des elements d'hybride.
US5825623A (en) * 1995-12-08 1998-10-20 Vlsi Technology, Inc. Packaging assemblies for encapsulated integrated circuit devices
CN100397602C (zh) * 1998-10-05 2008-06-25 库利克及索法工业公司 半导体铜键合焊点表面保护
US6352743B1 (en) * 1998-10-05 2002-03-05 Kulicke & Soffa Investments, Inc. Semiconductor copper band pad surface protection
US6790757B1 (en) * 1999-12-20 2004-09-14 Agere Systems Inc. Wire bonding method for copper interconnects in semiconductor devices
EP1306898A1 (en) * 2001-10-29 2003-05-02 Dialog Semiconductor GmbH Sub-milliohm on-chip interconnection
JP3943416B2 (ja) * 2002-03-07 2007-07-11 株式会社ルネサステクノロジ 半導体装置の製造方法
CN100347853C (zh) * 2003-08-07 2007-11-07 富士通株式会社 引线框架及其制造方法以及半导体器件
KR100998042B1 (ko) * 2004-02-23 2010-12-03 삼성테크윈 주식회사 리드 프레임 및 이를 구비한 반도체 패키지의 제조방법
AT12326U1 (de) 2009-04-20 2012-03-15 Austria Tech & System Tech Verfahren zum vorbehandeln eines rahmen- bzw. trägerelements für eine herstellung einer leiterplatte, sowie rahmen- bzw. trägerelement und verwendung hiefür
US8581378B2 (en) * 2009-09-29 2013-11-12 Panasonic Corporation Semiconductor device and method of manufacturing the same
JP6239840B2 (ja) * 2013-03-27 2017-11-29 ローム株式会社 半導体装置および半導体装置の製造方法

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Also Published As

Publication number Publication date
EP0178170A2 (en) 1986-04-16
DE3581039D1 (de) 1991-02-07
CN85107077A (zh) 1986-10-01
JPH0332912B2 (ja) 1991-05-15
EP0178170A3 (en) 1987-03-25
KR860003655A (ko) 1986-05-28
JPS6189643A (ja) 1986-05-07
KR900000439B1 (ko) 1990-01-30
CN85107077B (zh) 1988-01-27
US4891333A (en) 1990-01-02

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