EP0020666A1 - Dispositif semiconducteur - Google Patents

Dispositif semiconducteur

Info

Publication number
EP0020666A1
EP0020666A1 EP80900001A EP80900001A EP0020666A1 EP 0020666 A1 EP0020666 A1 EP 0020666A1 EP 80900001 A EP80900001 A EP 80900001A EP 80900001 A EP80900001 A EP 80900001A EP 0020666 A1 EP0020666 A1 EP 0020666A1
Authority
EP
European Patent Office
Prior art keywords
semiconductor
produced
conductivity type
base region
depressions
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP80900001A
Other languages
German (de)
English (en)
Inventor
Horst SCHÄFER
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semikron GmbH and Co KG
Original Assignee
Semikron GmbH and Co KG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semikron GmbH and Co KG filed Critical Semikron GmbH and Co KG
Publication of EP0020666A1 publication Critical patent/EP0020666A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/072—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/0814—Diodes only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015—Shape
    • H01L2924/10155—Shape being other than a cuboid
    • H01L2924/10157—Shape being other than a cuboid at the active surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015—Shape
    • H01L2924/10155—Shape being other than a cuboid
    • H01L2924/10158—Shape being other than a cuboid at the passive surface

Definitions

  • the invention relates to a semiconductor device consisting of diodes connected in parallel with a parallel to the method for producing such a semiconductor arrangement.
  • Anti-parallel circuits of diodes are used in control and regulating circuits, for example in DC converters. They can consist of discrete individual elements and can be combined and connected to form a structural unit on a carrier body.
  • spatially separated layer sequences can also be arranged in an integrated manner as diode structures in a semiconductor body and interconnected in an anti-parallel manner using conductor tracks.
  • a disadvantage of the combination of discrete components is the special effort for the completion of the individual elements and for their assembly and interconnection souie the often undesirably high space requirements and the resulting restrictions in use.
  • the disadvantages of the integrated arrangement with regard to the low electrical requirements for such circuits are the high process complexity for special diffusion and flasking steps.
  • the object of the invention is to determine an anti-parallel connection of diodes with the most favorable combination of their individual elements in terms of construction and manufacture.
  • the solution to this problem in a semiconductor arrangement of the type mentioned at the outset is that it comprises a semiconductor body with a base region made up of a zone of one conductivity type and with a further region adjacent to each side of the base region, which forms a pn junction with it and corresponds to it Zone of the other side of the base region has a staggered zone of smaller surface area for each one with respect to the other spatially and electrically antiparal diode structure as well as with contact metal coatings for the electrical connection of the two dipden structures.
  • the solution to the problem further consists in a method for producing such a semiconductor arrangement, in which, in a semiconductor output wafer of one conductivity type between the main surfaces, a layer sequence from a central zone and from two additional zones, each with an intermediate pn-, by diffusion of doping material of the other conductivity type on both sides. Transition is formed in which, after masking with a pattern, the starting disk is provided on both sides with a structure of trench-shaped depressions which are parallel to one another and each arranged on a gap opposite one another and which interrupt the nearest pn transition, in each case a coating of at least one contact metal is applied to the starting disk, and in which the disk is at least along all of the depressions in semiconductor components of smaller surface area, each with anti parallel diode structures is divided.
  • the depressions can be created by etching or by ultrasonic drilling or by sawing.
  • the thin, highly doped layer of the same conductivity type provided in the surface sections of the base region exposed by the depressions can be produced by diffusion or by vapor deposition and alloying of doping metals.
  • the contact metal coatings can be produced by electroless deposition of contact metals or by vapor deposition and alloying.
  • the surfaces of the starting disc can be roughened by sandblasting.
  • contact metals are used which form an ohmic contact with the semiconductor material of the starting disk, and that the thin, highly doped layer and the contact metal coatings are produced in one process step.
  • the advantage of the invention is that a compact arrangement of an anti-parallel connection of two diodes that meets all technical requirements can be achieved with a minimum of well-known method steps.
  • FIGS. 1 and 2 show in cross section the structure of the Semiconductor arrangement according to the invention
  • FIG. 2 shows in perspective a semiconductor output disk, from which semiconductor arrangements are manufactured in the manner according to the invention. The same designations are used for the same parts in all figures.
  • the semiconductor body according to FIG. 1 consists of an np structure I corresponding to a first diode and of the identical structure II, which is spatially oppositely oriented and arranged offset in the zone plane, corresponding to a forward, anti-parallel diode. Both structures have essentially the same surface area and the same thickness.
  • both structures is a central, n-conducting base region 1, on one side of which the p-conducting zone 2 adjoins the pn junction J1 formed thereby and thereby forms the structure I, and on the other side spatially adjoining the structure I.
  • the p-type zone 3 adjoins the pn junction 32 formed thereby and thereby forms the structure II.
  • the pn junction 31 of structure I appears on both end surfaces of zone 2 and the pn junction 32 on both end surfaces of zone 3.
  • the thickness of the zones of both structures I and II and their surface area are essentially determined by the requirements for their physical and electrical properties during use.
  • the structures are only stressed in the forward direction, so that special measures for surface stabilization and for improving the blocking ability are not required.
  • transition from one structure to the other i.e. the shape of the edge surface of the further zones 2, 3 is not critical and, in accordance with the production methods provided for forming the base region of each structure, is essentially perpendicular to the zone plane of the arrangement.
  • the latter is in each case provided with a highly doped, thin surface layer 4 or 5 of the same conductivity type.
  • n + conductive In the illustrated off the corresponding sections are n + conductive.
  • Both surfaces of the semiconductor body which run in the same stepped manner furthermore each have a contact metal coating 6 or 7, which can also be formed from partial layers.
  • Aluminum, silver, nickel, for example, are considered as contact metals.
  • contact metals can be used which are suitable for forming an ohmic contact with the semiconductor material, e.g. Aluminum or a combination of gold and antimony. This makes it possible to produce the thin, highly doped layer 4 or 5 and the contact metal coating 6 or 7 in one process step.
  • the semiconductor material e.g. Aluminum or a combination of gold and antimony.
  • the semiconductor arrangement according to the invention is surprisingly simple, alternating from a layer sequence with three layer-shaped zones of opposite conductivity type, e.g. a pnp structure is possible, and that production from a larger starting body by cutting along marking lines m .. is particularly advantageous.
  • a large-area semiconductor wafer of a first conductivity type is advantageously assumed.
  • a pnp layer sequence 1, 2, 3 is produced by known, mutual diffusion of impurities of the other conduction type, for example a boron diffusion at temperatures above 1200 ° C. into an n-type output disk.
  • the output disk is provided on both sides with depressions 10 and 20 in accordance with a pattern predetermined by the surface expansion and surface shape of the semiconductor components provided.
  • the output disk is, for example, appropriately masked on both sides and subjected to an etching process in which trench-shaped depressions 10 and 20, which run parallel to each other, are arranged on a gap with respect to those on the other side and interrupt the adjacent pn junction, which as a result form an approximately meandering cross section of the disk.
  • etching solutions are used for the etching treatment of the starting disk.
  • the depressions 10, 20 can advantageously also be produced by ultrasonic drilling or by sawing.
  • a thin, highly doped surface layer 4, 5 with a thickness of up to approximately 20 ⁇ m with the conductivity type of the base region 1 is produced in the bottom surface thereof.
  • This can be done by known diffusion, for example of phosphorus or boron.
  • the surface layer 4, 5 can also be produced by vapor deposition and alloying of a contact metal with doping property, for example aluminum or gold-antimony, in a manner known per se, as a result of which, in terms of process technology, the contact metal coatings 6, 7, ie the contact electrodes of the semiconductor body, are obtained at the same time .
  • these coatings 6, 7 are produced by electroless deposition of contact metals, for example nickel, their adhesion to the semiconductor surface can be improved by sandblasting.
  • the disk is divided along the marking lines m 1 , m 2 into components with a smaller surface area, as is particularly indicated in FIG. 2. This can advantageously be done using the laser technology.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

Le dispositif semiconducteur, forme de deux diodes montees tete-beche, presente un corps semiconducteur constitue d'une region de base (1) d'un type de conductivite et de deux zones disposees chacune d'un cote de la region de base. Chaque zone (2, 3) forme avec la region de base une jonction pn (J1, J2), et partant une structure de diode (I, II), et est decalee par rapport a l'autre. Les surfaces principales, formees chacune par la region de base et une des zones, sont munies d'une couche metallique de contact (6, 7) pour la liaison electrique des deux diodes. Lors de la fabrication, on forme par diffusion, a partir d'un disque semiconducteur d'un type de conductivite, une stratification de trois zones avec a chaque fois une jonction pn intermediaire. Ensuite, a l'aide d'un masquage et dans chaque surface principale du disque, on forme des cannelures paralleles par enlevement de matiere jusqu'au dessus de la jonction pn respective, ceci de maniere a obtenir une structure striee, les stries d'un cote du disque etant decalees par rapport a celles de l'autre cote. Les deux surfaces sont metallisees et le disque est subdivise en dispositifs semiconducteurs le long des cannelures.
EP80900001A 1978-12-23 1980-07-01 Dispositif semiconducteur Withdrawn EP0020666A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE2855972A DE2855972C2 (de) 1978-12-23 1978-12-23 Halbleiteranordnung mit zwei integrierten und antiparallel geschalteten Dioden sowie Verfahren zu ihrer Herstellung
DE2855972 1978-12-23

Publications (1)

Publication Number Publication Date
EP0020666A1 true EP0020666A1 (fr) 1981-01-07

Family

ID=6058262

Family Applications (1)

Application Number Title Priority Date Filing Date
EP80900001A Withdrawn EP0020666A1 (fr) 1978-12-23 1980-07-01 Dispositif semiconducteur

Country Status (8)

Country Link
US (1) US4525924A (fr)
EP (1) EP0020666A1 (fr)
JP (1) JPS55501161A (fr)
DE (1) DE2855972C2 (fr)
GB (1) GB2064869B (fr)
IT (1) IT1126607B (fr)
SE (1) SE443476B (fr)
WO (1) WO1980001334A1 (fr)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3435306A1 (de) * 1984-09-26 1986-04-03 Siemens AG, 1000 Berlin und 8000 München Verfahren zur herstellung von laserdioden mit jutierter integrierter waermesenke
KR940016546A (ko) * 1992-12-23 1994-07-23 프레데릭 얀 스미트 반도체 장치 및 제조방법
GB2285882B (en) * 1994-01-14 1997-12-17 Westinghouse Brake & Signal Semiconductor switching devices
US6033489A (en) * 1998-05-29 2000-03-07 Fairchild Semiconductor Corp. Semiconductor substrate and method of making same

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2748041A (en) * 1952-08-30 1956-05-29 Rca Corp Semiconductor devices and their manufacture
US3039028A (en) * 1955-09-26 1962-06-12 Hoffman Electronics Corp Double based diode
US2985805A (en) * 1958-03-05 1961-05-23 Rca Corp Semiconductor devices
US3005937A (en) * 1958-08-21 1961-10-24 Rca Corp Semiconductor signal translating devices
NL125803C (fr) * 1961-01-16
US3519900A (en) * 1967-11-13 1970-07-07 Motorola Inc Temperature compensated reference diodes and methods for making same
DE1916555A1 (de) * 1969-04-01 1971-03-04 Semikron Gleichrichterbau Halbleiter-Gleichrichter-Anordnung und Verfahren zu ihrer Herstellung
US3978514A (en) * 1969-07-18 1976-08-31 Hitachi, Ltd. Diode-integrated high speed thyristor
US3706129A (en) * 1970-07-27 1972-12-19 Gen Electric Integrated semiconductor rectifiers and processes for their fabrication
FR2126904B1 (fr) * 1970-12-07 1974-04-26 Silec Semi Conducteurs
JPS567304B2 (fr) * 1972-08-28 1981-02-17
US3972113A (en) * 1973-05-14 1976-08-03 Mitsubishi Denki Kabushiki Kaisha Process of producing semiconductor devices
DE2610942C2 (de) * 1976-03-16 1983-04-28 Licentia Patent-Verwaltungs-Gmbh, 6000 Frankfurt Verfahren zum Herstellen eines Halbleiterbauelements mit in einem Halbleiterkörper monolithisch integrierten Halbleiterelementeinheiten
US4219835A (en) * 1978-02-17 1980-08-26 Siliconix, Inc. VMOS Mesa structure and manufacturing process

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO8001334A1 *

Also Published As

Publication number Publication date
GB2064869B (en) 1983-05-18
IT1126607B (it) 1986-05-21
SE8008879L (sv) 1980-12-17
SE443476B (sv) 1986-02-24
IT7928210A0 (it) 1979-12-19
DE2855972A1 (de) 1980-06-26
DE2855972C2 (de) 1984-09-27
WO1980001334A1 (fr) 1980-06-26
US4525924A (en) 1985-07-02
GB2064869A (en) 1981-06-17
JPS55501161A (fr) 1980-12-18

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Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

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AK Designated contracting states

Designated state(s): FR

17P Request for examination filed

Effective date: 19801229

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE APPLICATION IS DEEMED TO BE WITHDRAWN

18D Application deemed to be withdrawn

Effective date: 19830701

RIN1 Information on inventor provided before grant (corrected)

Inventor name: SCHAEFER, HORST