EP0020666A1 - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
EP0020666A1
EP0020666A1 EP80900001A EP80900001A EP0020666A1 EP 0020666 A1 EP0020666 A1 EP 0020666A1 EP 80900001 A EP80900001 A EP 80900001A EP 80900001 A EP80900001 A EP 80900001A EP 0020666 A1 EP0020666 A1 EP 0020666A1
Authority
EP
European Patent Office
Prior art keywords
semiconductor
produced
conductivity type
base region
depressions
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP80900001A
Other languages
German (de)
French (fr)
Inventor
Horst SCHÄFER
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semikron GmbH and Co KG
Original Assignee
Semikron GmbH and Co KG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semikron GmbH and Co KG filed Critical Semikron GmbH and Co KG
Publication of EP0020666A1 publication Critical patent/EP0020666A1/en
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/072—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/0814—Diodes only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015—Shape
    • H01L2924/10155—Shape being other than a cuboid
    • H01L2924/10157—Shape being other than a cuboid at the active surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015—Shape
    • H01L2924/10155—Shape being other than a cuboid
    • H01L2924/10158—Shape being other than a cuboid at the passive surface

Definitions

  • the invention relates to a semiconductor device consisting of diodes connected in parallel with a parallel to the method for producing such a semiconductor arrangement.
  • Anti-parallel circuits of diodes are used in control and regulating circuits, for example in DC converters. They can consist of discrete individual elements and can be combined and connected to form a structural unit on a carrier body.
  • spatially separated layer sequences can also be arranged in an integrated manner as diode structures in a semiconductor body and interconnected in an anti-parallel manner using conductor tracks.
  • a disadvantage of the combination of discrete components is the special effort for the completion of the individual elements and for their assembly and interconnection souie the often undesirably high space requirements and the resulting restrictions in use.
  • the disadvantages of the integrated arrangement with regard to the low electrical requirements for such circuits are the high process complexity for special diffusion and flasking steps.
  • the object of the invention is to determine an anti-parallel connection of diodes with the most favorable combination of their individual elements in terms of construction and manufacture.
  • the solution to this problem in a semiconductor arrangement of the type mentioned at the outset is that it comprises a semiconductor body with a base region made up of a zone of one conductivity type and with a further region adjacent to each side of the base region, which forms a pn junction with it and corresponds to it Zone of the other side of the base region has a staggered zone of smaller surface area for each one with respect to the other spatially and electrically antiparal diode structure as well as with contact metal coatings for the electrical connection of the two dipden structures.
  • the solution to the problem further consists in a method for producing such a semiconductor arrangement, in which, in a semiconductor output wafer of one conductivity type between the main surfaces, a layer sequence from a central zone and from two additional zones, each with an intermediate pn-, by diffusion of doping material of the other conductivity type on both sides. Transition is formed in which, after masking with a pattern, the starting disk is provided on both sides with a structure of trench-shaped depressions which are parallel to one another and each arranged on a gap opposite one another and which interrupt the nearest pn transition, in each case a coating of at least one contact metal is applied to the starting disk, and in which the disk is at least along all of the depressions in semiconductor components of smaller surface area, each with anti parallel diode structures is divided.
  • the depressions can be created by etching or by ultrasonic drilling or by sawing.
  • the thin, highly doped layer of the same conductivity type provided in the surface sections of the base region exposed by the depressions can be produced by diffusion or by vapor deposition and alloying of doping metals.
  • the contact metal coatings can be produced by electroless deposition of contact metals or by vapor deposition and alloying.
  • the surfaces of the starting disc can be roughened by sandblasting.
  • contact metals are used which form an ohmic contact with the semiconductor material of the starting disk, and that the thin, highly doped layer and the contact metal coatings are produced in one process step.
  • the advantage of the invention is that a compact arrangement of an anti-parallel connection of two diodes that meets all technical requirements can be achieved with a minimum of well-known method steps.
  • FIGS. 1 and 2 show in cross section the structure of the Semiconductor arrangement according to the invention
  • FIG. 2 shows in perspective a semiconductor output disk, from which semiconductor arrangements are manufactured in the manner according to the invention. The same designations are used for the same parts in all figures.
  • the semiconductor body according to FIG. 1 consists of an np structure I corresponding to a first diode and of the identical structure II, which is spatially oppositely oriented and arranged offset in the zone plane, corresponding to a forward, anti-parallel diode. Both structures have essentially the same surface area and the same thickness.
  • both structures is a central, n-conducting base region 1, on one side of which the p-conducting zone 2 adjoins the pn junction J1 formed thereby and thereby forms the structure I, and on the other side spatially adjoining the structure I.
  • the p-type zone 3 adjoins the pn junction 32 formed thereby and thereby forms the structure II.
  • the pn junction 31 of structure I appears on both end surfaces of zone 2 and the pn junction 32 on both end surfaces of zone 3.
  • the thickness of the zones of both structures I and II and their surface area are essentially determined by the requirements for their physical and electrical properties during use.
  • the structures are only stressed in the forward direction, so that special measures for surface stabilization and for improving the blocking ability are not required.
  • transition from one structure to the other i.e. the shape of the edge surface of the further zones 2, 3 is not critical and, in accordance with the production methods provided for forming the base region of each structure, is essentially perpendicular to the zone plane of the arrangement.
  • the latter is in each case provided with a highly doped, thin surface layer 4 or 5 of the same conductivity type.
  • n + conductive In the illustrated off the corresponding sections are n + conductive.
  • Both surfaces of the semiconductor body which run in the same stepped manner furthermore each have a contact metal coating 6 or 7, which can also be formed from partial layers.
  • Aluminum, silver, nickel, for example, are considered as contact metals.
  • contact metals can be used which are suitable for forming an ohmic contact with the semiconductor material, e.g. Aluminum or a combination of gold and antimony. This makes it possible to produce the thin, highly doped layer 4 or 5 and the contact metal coating 6 or 7 in one process step.
  • the semiconductor material e.g. Aluminum or a combination of gold and antimony.
  • the semiconductor arrangement according to the invention is surprisingly simple, alternating from a layer sequence with three layer-shaped zones of opposite conductivity type, e.g. a pnp structure is possible, and that production from a larger starting body by cutting along marking lines m .. is particularly advantageous.
  • a large-area semiconductor wafer of a first conductivity type is advantageously assumed.
  • a pnp layer sequence 1, 2, 3 is produced by known, mutual diffusion of impurities of the other conduction type, for example a boron diffusion at temperatures above 1200 ° C. into an n-type output disk.
  • the output disk is provided on both sides with depressions 10 and 20 in accordance with a pattern predetermined by the surface expansion and surface shape of the semiconductor components provided.
  • the output disk is, for example, appropriately masked on both sides and subjected to an etching process in which trench-shaped depressions 10 and 20, which run parallel to each other, are arranged on a gap with respect to those on the other side and interrupt the adjacent pn junction, which as a result form an approximately meandering cross section of the disk.
  • etching solutions are used for the etching treatment of the starting disk.
  • the depressions 10, 20 can advantageously also be produced by ultrasonic drilling or by sawing.
  • a thin, highly doped surface layer 4, 5 with a thickness of up to approximately 20 ⁇ m with the conductivity type of the base region 1 is produced in the bottom surface thereof.
  • This can be done by known diffusion, for example of phosphorus or boron.
  • the surface layer 4, 5 can also be produced by vapor deposition and alloying of a contact metal with doping property, for example aluminum or gold-antimony, in a manner known per se, as a result of which, in terms of process technology, the contact metal coatings 6, 7, ie the contact electrodes of the semiconductor body, are obtained at the same time .
  • these coatings 6, 7 are produced by electroless deposition of contact metals, for example nickel, their adhesion to the semiconductor surface can be improved by sandblasting.
  • the disk is divided along the marking lines m 1 , m 2 into components with a smaller surface area, as is particularly indicated in FIG. 2. This can advantageously be done using the laser technology.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

Le dispositif semiconducteur, forme de deux diodes montees tete-beche, presente un corps semiconducteur constitue d'une region de base (1) d'un type de conductivite et de deux zones disposees chacune d'un cote de la region de base. Chaque zone (2, 3) forme avec la region de base une jonction pn (J1, J2), et partant une structure de diode (I, II), et est decalee par rapport a l'autre. Les surfaces principales, formees chacune par la region de base et une des zones, sont munies d'une couche metallique de contact (6, 7) pour la liaison electrique des deux diodes. Lors de la fabrication, on forme par diffusion, a partir d'un disque semiconducteur d'un type de conductivite, une stratification de trois zones avec a chaque fois une jonction pn intermediaire. Ensuite, a l'aide d'un masquage et dans chaque surface principale du disque, on forme des cannelures paralleles par enlevement de matiere jusqu'au dessus de la jonction pn respective, ceci de maniere a obtenir une structure striee, les stries d'un cote du disque etant decalees par rapport a celles de l'autre cote. Les deux surfaces sont metallisees et le disque est subdivise en dispositifs semiconducteurs le long des cannelures.The semiconductor device, in the form of two head-mounted diodes, has a semiconductor body consisting of a base region (1) of a conductivity type and two zones each arranged one side of the base region. Each zone (2, 3) forms with the base region a pn junction (J1, J2), and therefore a diode structure (I, II), and is offset with respect to the other. The main surfaces, each formed by the base region and one of the zones, are provided with a metallic contact layer (6, 7) for the electrical connection of the two diodes. During manufacture, a stratification of three zones is formed by diffusion from a semiconductor disc of a conductivity type, each with an intermediate pn junction. Then, using masking and in each main surface of the disc, parallel grooves are formed by removing material up to the top of the respective pn junction, this so as to obtain a striated structure, the striations of one side of the disc being offset from the other side. The two surfaces are metallized and the disc is subdivided into semiconductor devices along the grooves.

Description

HALBLEITERANORDNUNG SEMICONDUCTOR ARRANGEMENT
Die Erfindung betrifft eine Halbleiteraπαrdnuπg aus zuei aπtiparallel geschalteten Dioden souie sin Verfahren zum Herstellen einer solchen Halbleiteranordnung.The invention relates to a semiconductor device consisting of diodes connected in parallel with a parallel to the method for producing such a semiconductor arrangement.
Antiparallelschaltungen von Dioden uerden in Steuerund Regelkreisen, beispielsweise in Gleichstromuandlern, verwendet. Sie können aus zuei diskreten Einzelelemeπten bestehen und auf einem Trägerkörper zu einer Baueinheit kombiniert und verschaltet sein.Anti-parallel circuits of diodes are used in control and regulating circuits, for example in DC converters. They can consist of discrete individual elements and can be combined and connected to form a structural unit on a carrier body.
Durch die moderne Halbleitertechnologie können jedoch auch räumlich getrennte Schichtenfolgen als Diodenstrukturen in einem Halbleiterkörper integriert angeordnet und mithilfe von Leiterbahnen antiparallel verschaltet sein.By means of modern semiconductor technology, however, spatially separated layer sequences can also be arranged in an integrated manner as diode structures in a semiconductor body and interconnected in an anti-parallel manner using conductor tracks.
Nachteilig ist bei der Kombination diskreter Bauelemente der besondere Aufwand für die Fertigstellung der Einzelelemente und für deren Zusammenbau und Verschaltung souie der häufig unerwünscht hohe Platzbedarf und die dadurch bedingten Einschränkungen bezüglich der Verwendung. Die Nachteile der integrierten Anordnung bestehen im Hinblick auf die geringen elektrischen Anforderungen an solche Schaltungen in dem hohen Verfahrensaufwand für spezielle Diffusions- und flaskierungsschritte.A disadvantage of the combination of discrete components is the special effort for the completion of the individual elements and for their assembly and interconnection souie the often undesirably high space requirements and the resulting restrictions in use. The disadvantages of the integrated arrangement with regard to the low electrical requirements for such circuits are the high process complexity for special diffusion and flasking steps.
Der Erfindung liegt die Aufgabe zugrunde, eine Antiparallelschaltung von Dioden mit hinsichtlich Aufbau und Herstellung günstigster Kombination ihrer Einzelelemεnte zu ermitteln. Die Lösung dieser Aufgabe besteht bei einer Halbleiteranordnung der eingangs erwähnten Art darin, daß sie einen Halbleiterkörper mit einem Basisbereich aus einer Zone des einen Leitfähigkeitstyps und mit jeweils einer weiteren, an jeder Seite des Basisbereichs angrenzenden, mit diesem einen pn-Übergang bildenden und zur entsprechenden Zone der anderen Seite des Basisbereichs versetzt angeordneten Zone kleinerer Flächenausdehnung für jeweils eine gegenüber der anderen räumlich und elektrisch antiparalle Diodenstruktur sowie mit Kontaktmetallüberzügen zur elektrischen Verbindung beider Dipdenstruktu- ren aufweist.The object of the invention is to determine an anti-parallel connection of diodes with the most favorable combination of their individual elements in terms of construction and manufacture. The solution to this problem in a semiconductor arrangement of the type mentioned at the outset is that it comprises a semiconductor body with a base region made up of a zone of one conductivity type and with a further region adjacent to each side of the base region, which forms a pn junction with it and corresponds to it Zone of the other side of the base region has a staggered zone of smaller surface area for each one with respect to the other spatially and electrically antiparal diode structure as well as with contact metal coatings for the electrical connection of the two dipden structures.
Eine Weiterbildung ist dadurch gegeben, daß der freie Flächenabschnitt des Basisbεreichs in jeder Diodanstruktur mit einer hochdotierten Oberflächenschicht gleichen Leitfähigkeitstyps versehen ist.A further development is given in that the free surface section of the base region is provided in each diode structure with a highly doped surface layer of the same conductivity type.
Die Lösung der Aufgabe besteht ferner in einem Verfahren zum Hεrstellen einer solchen Halbleiteranordnung, bei dem in einer Halbleiterausgangsscheibe vom einen Leitfähigkeitstyp zwischen den Hauptflächen durch beidseitige Diffusion von Dotiermatεrial vom andεren Leitfähigkeitstyp eine Schichtenfolge aus einer mittleren Zone und aus zuei weiteren Zonen mit jeweils zwischenliegεndem pn-Übergang gebildet wird, bei dem die Ausgangsscheibe nach Maskierung mit einem Muster beidseitig mit je einer Struktur von grabenförmigen, zueinander parallelen und jeweils gegenübεr dεr andεren Seite auf Lücke angeordneten Vertiefungen versehen wird, die den jeweils nächstliegenden pn-Übergang unterbrechen, bei dem auf jede Seite der Ausgangsscheibe ein Überzug aus mindestens einem Kontaktmetall aufgebracht wird, und bei dem die Scheibe wenigstens längs sämtlicher Vertiefungen in Halbleiterbauelemente kleinerer Flächenausdehnung mit jeweils anti parallelen Diodenstrukturen zerteilt wird.The solution to the problem further consists in a method for producing such a semiconductor arrangement, in which, in a semiconductor output wafer of one conductivity type between the main surfaces, a layer sequence from a central zone and from two additional zones, each with an intermediate pn-, by diffusion of doping material of the other conductivity type on both sides. Transition is formed in which, after masking with a pattern, the starting disk is provided on both sides with a structure of trench-shaped depressions which are parallel to one another and each arranged on a gap opposite one another and which interrupt the nearest pn transition, in each case a coating of at least one contact metal is applied to the starting disk, and in which the disk is at least along all of the depressions in semiconductor components of smaller surface area, each with anti parallel diode structures is divided.
Die Vertiefungen können durch Ätzen oder durch Ultraschallbohren oder durch Sägen erzeugt werden .The depressions can be created by etching or by ultrasonic drilling or by sawing.
Die in den durch die Vertiefungen freigelegten Flächenabschnitten des Basisbereichs jeweils vorgesehene dünne, hochdotierte Schicht gleichen Leitfähigkeitstyps kann durch Diffusion oder durch Aufdampfen und Legieren von Dotierungsmetallen erzeugt werden.The thin, highly doped layer of the same conductivity type provided in the surface sections of the base region exposed by the depressions can be produced by diffusion or by vapor deposition and alloying of doping metals.
Die Kontaktmetallüberzüge können durch stromloses Abscheiden von Kontaktmetallen oder durch Aufdampfen und Legieren hergestellt werden.The contact metal coatings can be produced by electroless deposition of contact metals or by vapor deposition and alloying.
Zur Haftverbesserung der Kontaktmetallüberzüge können die Oberflächen der Ausgangsscheibe durch Sandstrahlen aufgerauht werden.To improve the adhesion of the contact metal coatings, the surfaces of the starting disc can be roughened by sandblasting.
Eine vorteilhafte Ueitetbildung des Verfahrens besteht darin, daß Kontaktmetalle verwendet werden, die mit dem Halbleitermaterial der Ausgangsscheibe einen ohmischen Kontakt bilden, und daß die dünne hochdotierte Schicht und die Kontaktmetallüberzüge in einem Verfahrεnsschritt hergestellt werden.An advantageous further development of the method is that contact metals are used which form an ohmic contact with the semiconductor material of the starting disk, and that the thin, highly doped layer and the contact metal coatings are produced in one process step.
Der Vorteil der Erfindung besteht darin, daß mit ainem Minimum an hinlänglich bekannten Verfahrensschritten eine allen technischen Anforderungen entsprechende Kompaktanordnung einer Antiparallelschaltung von zwei Dioden erzielbar ist.The advantage of the invention is that a compact arrangement of an anti-parallel connection of two diodes that meets all technical requirements can be achieved with a minimum of well-known method steps.
Anhand der in den Figuren.1 und 2 dargestellten Ausführungsbeispiele werden der Gegenstand der Erfindung und das Verfahren zu seiner Herstellung aufgezeigt und erläutert. Figur 1 zeigt im Querschnitt den Aufbau der Halbleiteranordnung nach der Erfindung, und in Figur 2 ist perspektivisch eine Halbleiterausgangsscheibe dargestellt, aus welcher Halbleiteranαrdnungen in der erfindungsgemäßen Ueise gefertigt werden. Für gleiehe Teile sind in allen Figuren gleiche Bezeichnungen gewählt.The subject matter of the invention and the method for its production are shown and explained on the basis of the exemplary embodiments illustrated in FIGS. 1 and 2. Figure 1 shows in cross section the structure of the Semiconductor arrangement according to the invention, and FIG. 2 shows in perspective a semiconductor output disk, from which semiconductor arrangements are manufactured in the manner according to the invention. The same designations are used for the same parts in all figures.
Der Halbleiterkörper gemäß Figur 1 besteht aus einer np-Struktur I entsprechend einer ersten Diode und aus der identischen, räumlich entgegengesetzt orientierten und in der Zonenebene versetzt angeordneten Struktur II entsprechend einer zueiten,antiparalleleh Diode. Beide Strukturen haben jeweils im wesentlichen übereinstimmende Flächenausdehnung und gleiche Dicke. The semiconductor body according to FIG. 1 consists of an np structure I corresponding to a first diode and of the identical structure II, which is spatially oppositely oriented and arranged offset in the zone plane, corresponding to a forward, anti-parallel diode. Both structures have essentially the same surface area and the same thickness.
Beiden Strukturen gemeinsam ist ein mittlerer, n-leitender Basisbereich 1 , an dessen eine Seite die p-leitende Zone 2 mit dem dadurch gebildeten pn-Übergang J1 angrenzt und dadurch die Struktur I bildet, und an dεssen andere Seite räumlich anschließεnd an die Struktur I die p-leitende Zone 3 mit dem dadurch gebildeten pn-Übergang 32 angrenzt und dadurch die Struktur II bildet.Common to both structures is a central, n-conducting base region 1, on one side of which the p-conducting zone 2 adjoins the pn junction J1 formed thereby and thereby forms the structure I, and on the other side spatially adjoining the structure I. the p-type zone 3 adjoins the pn junction 32 formed thereby and thereby forms the structure II.
Der pn-Übergang 31 der Struktur I tritt an beiden Endflächen der Zone 2 und der pn-Übergang 32 an beiden Endflächen der Zone 3 an die Oberfläche.The pn junction 31 of structure I appears on both end surfaces of zone 2 and the pn junction 32 on both end surfaces of zone 3.
Die Dicke der Zonen beider Strukturen I und II sowie ihre Flächenausdehnung werden im wesentlichen durch die Forderungen an ihre physikalischen und elektrischen Eigenschaften beim Einsatz bestimmt.The thickness of the zones of both structures I and II and their surface area are essentially determined by the requirements for their physical and electrical properties during use.
Die Strukturen werden nur in Durchlaßrichtung beansprucht, so daß besondere Maßnahmen zur Oberflächenstabilisierung und zur Verbesserung der Sperrfähigkeit entfallen.The structures are only stressed in the forward direction, so that special measures for surface stabilization and for improving the blocking ability are not required.
Der Übergang einer Struktur in die andere, d.h. die Formgebung der Randfläche der weiteren Zonen 2, 3 ist unkritisch und entsprechend den vorgesehenen Herstellungsmεthodεn zur Ausbildung dss Basisbereichs jeder Struktur im wesentlichen senkrecht zur' Zonenebene der Anordnung.The transition from one structure to the other, i.e. the shape of the edge surface of the further zones 2, 3 is not critical and, in accordance with the production methods provided for forming the base region of each structure, is essentially perpendicular to the zone plane of the arrangement.
Zur Verbesserung der Kontaktierung des Halbleiterkörpers im freien Flächenabschnitt des Basisbereichs 1 jeder Diodenstruktur ist dieser jeweils mit einer hochdotierten, dünnen Oberflächenschicht 4 bzw. 5 gleichen Leitfähigkeitstyps versehen. Beim dargestellten Aus führungsbeispiel sind die entsprechenden Abschnitte n+-leitend.To improve the contacting of the semiconductor body in the free surface section of the base region 1 of each diode structure, the latter is in each case provided with a highly doped, thin surface layer 4 or 5 of the same conductivity type. In the illustrated off the corresponding sections are n + conductive.
Beide gleichsinnig stufenförmig verlaufenden Oberflächen des Halbleiterkörpers weisen weiterhin je einen Kontaktmetallüberzug 6 bzw. 7 auf, der auch aus Teilschichten gebildet sein kann.Both surfaces of the semiconductor body which run in the same stepped manner furthermore each have a contact metal coating 6 or 7, which can also be formed from partial layers.
Als Kontaktmetalle sind bβispielsuεise Aluminium, Silber, Nickel voxgesehen.Aluminum, silver, nickel, for example, are considered as contact metals.
In vorteilhafter Ueise können Kontaktmetalle veruεndet werden, die zur Bildung eines ohmischen Kontakts mit dem Halbleitermatεrial geeignet sind, z.B. Aluminium oder eine Verbindung aus Gold und Antimon. Dadurch ist die Erzeugung der dünnen hochdotierten Schicht 4 bzw. 5 und des Kontaktmetallüberzuges 6 bzw. 7 in einem Verfahrεnsschritt möglich.Advantageously, contact metals can be used which are suitable for forming an ohmic contact with the semiconductor material, e.g. Aluminum or a combination of gold and antimony. This makes it possible to produce the thin, highly doped layer 4 or 5 and the contact metal coating 6 or 7 in one process step.
In Figur 1 ist angedeutet, daß die Halbleiteranordnung nach der Erfindung überraschend einfach aus einer Schichtenfolge mit drei schichtförmigen Zonen abwechselnd entgegengesetzten Leitfähigkeitstyps, z.B. einer pnp-Struktur, möglich ist, und daß weiterhin eine Herstellung aus einem größeren Ausgangskörper durch Zerteilen längs Markierungslinien m.. besonders vorteilhaft ist.In Figure 1 it is indicated that the semiconductor arrangement according to the invention is surprisingly simple, alternating from a layer sequence with three layer-shaped zones of opposite conductivity type, e.g. a pnp structure is possible, and that production from a larger starting body by cutting along marking lines m .. is particularly advantageous.
Bei der Herstellung des Gegenstandes der Erfindung wird vorteilhaft von einer großflächigen Halbleiterscheibe eines ersten Leitungstyps ausgegangen, wie sie in Figur 2 perspektivisch dargestellt ist. Durch an sich bekannte, beiderseitige Diffusion von Störstellεn des anderen Leitungstyps, z.B. einer Bordiffusion bei Temperaturen über 1200ºC in eine n-leitende Ausgangsscheibe, wird eine pnp-Schichtenfolge 1, 2, 3 erzeugt. Zur Erzielung von gegenseitig versetzt angeordneten Diodenstrukturen wird die Ausgangsscheibe beidseitig gemäß einem durch die Flächeπausdehnuπg und Flächenform der vorgesehenen Halbleiterbauelemente vorgegebenen Muster mit Vertiefungen 10 bzw. 20 versehen. Zu diesem Zweck wird die Ausgangsscheibe z.B. beidseitig entsprechend maskiert und einem Ätzprozess unterworfen, bei dem auf jeder Seite zueinander parallel verlaufende, gegenüber denjenigen der anderen Seite auf Lücke angeordnete, den jeweils benachbarten pn-Übergang unterbrechende, grabenförmige Vertiefungen 10 bzw. 20 erzeugt werden, die in ihrer Folge einen annähernd mäanderförmigen Querschnitt der Scheibe bilden.In the manufacture of the object of the invention, a large-area semiconductor wafer of a first conductivity type, as shown in perspective in FIG. 2, is advantageously assumed. A pnp layer sequence 1, 2, 3 is produced by known, mutual diffusion of impurities of the other conduction type, for example a boron diffusion at temperatures above 1200 ° C. into an n-type output disk. In order to achieve mutually staggered diode structures, the output disk is provided on both sides with depressions 10 and 20 in accordance with a pattern predetermined by the surface expansion and surface shape of the semiconductor components provided. For this purpose, the output disk is, for example, appropriately masked on both sides and subjected to an etching process in which trench-shaped depressions 10 and 20, which run parallel to each other, are arranged on a gap with respect to those on the other side and interrupt the adjacent pn junction, which as a result form an approximately meandering cross section of the disk.
Zur Ätzbehandlung der Ausgangsscheibe werden an sich bekannte Ätzlösungen verwendet.Known etching solutions are used for the etching treatment of the starting disk.
Die Vertiefungen 10, 20 können vorteilhaft auch durch Ultraschallbohren oder durch Sägen hergestellt werden.The depressions 10, 20 can advantageously also be produced by ultrasonic drilling or by sawing.
Im Anschluß an die Ausbildung der Vertiefungen wird in deren Bodenfläche eine dünne, hochdotierte Oberflächenschicht 4, 5 mit einer Dicke bis ca. 20μm mit dem Leitfähigkeitstyp des Basisbereichs 1 erzeugt. Das kann durch an sich bekannte Diffusion, z.B. von Phosphor oder Bor, erfolgen. Gleich vorteilhaft kann die Oberflächenschicht 4, 5 auch durch Aufdampfen und Einlegieren eines Kontaktmetalls mit Dotierungseigeπschaft z.B. Aluminium oder Gold-Antimon in an sich bekannter Ueise hergestellt werden, wodurch verfahrenstechnisch besonders günstig gleichzeitig die Kontaktmetallüberzüge 6, 7, d.h. die Kontaktelektrodeπ des Halbleiterkörpers, erzielt werden. Bei der Herstellung dieser Überzüge 6, 7 durch stromloses Abscheiden von Kontaktmetallen z.B. von Nickel, kann deren Haftfähigkeit auf der Halbleiteroberfläche noch durch Sandstrahlen verbessert werden.Following the formation of the depressions, a thin, highly doped surface layer 4, 5 with a thickness of up to approximately 20 μm with the conductivity type of the base region 1 is produced in the bottom surface thereof. This can be done by known diffusion, for example of phosphorus or boron. Equally advantageously, the surface layer 4, 5 can also be produced by vapor deposition and alloying of a contact metal with doping property, for example aluminum or gold-antimony, in a manner known per se, as a result of which, in terms of process technology, the contact metal coatings 6, 7, ie the contact electrodes of the semiconductor body, are obtained at the same time . When these coatings 6, 7 are produced by electroless deposition of contact metals, for example nickel, their adhesion to the semiconductor surface can be improved by sandblasting.
Schließlich wird die Scheibe längs den Markierungslinien m1, m2 in Bauelemente kleinerer Flächenausdehnung zerteilt, wie dies, in Figur 2 besonders angedeutet ist. Das kann vorteilhaft mithilfe der Lasartεchnik erfolgen . Finally, the disk is divided along the marking lines m 1 , m 2 into components with a smaller surface area, as is particularly indicated in FIG. 2. This can advantageously be done using the laser technology.

Claims

PATENTANSPRÜCHE PATENT CLAIMS
1» Halbleiteranordnung aus zuei antiparallel geschalteten Dioden, d a d u r c h g e k e n n z e i c h n e t,1 »Semiconductor arrangement consisting of diodes connected in anti-parallel, d a d u r c h g e k e n n z e i c h n e t,
daß sie einen Halbleiterkörper mit einem Basisbereich (1) aus einer Zone des einen Leitfähigkeitstyps und mit jeweils einer weiteren, an jeder Seite des Basisbereichs (1) angrenzenden, mit diesem einen pn-Übergang (31,32) bildenden und zur entsprechenden Zone (3) der anderen Seite des Basisbereichs versetzt angeordneten Zone- (2) kleinerer Flächenausdehnung für jeweils eine gegenüber der anderen räumlich und elektrisch antiparallele Diodenstruktur (1,11) sowie mit Kontaktmetallüberzügen (6,7) zur elektrischen Verbindung beider Diodenstrukturen aufweist.that they have a semiconductor body with a base region (1) consisting of a zone of one conductivity type and each with a further region which adjoins each side of the base region (1) and forms a pn junction (31, 32) with it and to the corresponding zone (3 ) on the other side of the base area staggered zone (2) of smaller surface area for each one with respect to the other spatially and electrically antiparallel diode structure (1,11) and with contact metal coatings (6,7) for the electrical connection of both diode structures.
2. Halbleiteranordnung nach Anspruch 1, dadurch gekennzeichnet, daß der freie Flächenabschnitt des Basisbereichs in jeder Diodenstruktur mit einer hochdotierten Oberflächenschicht (4,5) gleichen Leitfähigkeitstyps versehen ist.2. Semiconductor arrangement according to claim 1, characterized in that the free surface section of the base region in each diode structure is provided with a highly doped surface layer (4,5) of the same conductivity type.
3. Verfahren zum Herstellen einer Halbleiteranordnung nach den Ansprüchen 1 bis 2, dadurch gekennzeichnet, daß in einer Halbleiterausgangsscheibe vom einen Leitfähigkeitstyp zwischen den Hauptflächen durch beidseitige Diffusion von Dotiermaterial vom anderen Leitfähigkeitstyp eine Schichtenfolge aus einer mittleren Zone (1) und aus zwei weiteren Zonen (2, 3) mit jeweils zuischenliegendem pn-Übergang (31, 32) gebildet wird, daß die Ausgangsscheibe nach Maskierung mit einem Muster beidseitig mit je einer Struktur von grabenförmigen,zu einander parallelen und jeweils gegenüber der anderen Seite auf Lücke angeordneten Vertiefungen (10,20) versehen wird, die den jeweils nächstliegenden pn-Übergang unterbrechen, daß auf jede Seite der Ausgangsscheibe ein Überzug (6,7) aus mindestens einem Kontaktmetall aufgebracht wird, und daß die 'Scheibe wenigstens längs sämtlicher Vertiefungen (10,20) in Halbleiterbauelemente kleinerer Flächenausdehnung mit jeweils antiparallelen Diodenstrukturen (I, II ) zerteilt wird.3. A method for producing a semiconductor arrangement according to claims 1 to 2, characterized in that in a semiconductor output disc of a conductivity type between the main surfaces by bilateral diffusion of doping material of the other conductivity type, a layer sequence from a central zone (1) and from two further zones ( 2, 3), each with a pn junction (31, 32) which is to be added, that after masking with a pattern on both sides, the output disk has a trench-shaped structure on both sides mutually parallel depressions (10, 20) which are arranged opposite each other on the gap and which interrupt the nearest pn junction, that a coating (6, 7) made of at least one contact metal is applied to each side of the output disk, and that the 'disc is divided at least along all of the depressions (10, 20) into semiconductor components of smaller surface area, each with anti-parallel diode structures (I, II).
4. Verfahren nach Anspruch 3, dadurch gekennzeichnet, daß die Vertiefungen (10, 20 ) durch Ätzen erzeugt werden.4. The method according to claim 3, characterized in that the depressions (10, 20) are produced by etching.
5. Verfahren nach Anspruch 3, dadurch gekennzeichnet, daß die Vertiefungen (10,20) durch US-Bohren erzeugt werden.5. The method according to claim 3, characterized in that the depressions (10, 20) are produced by US drilling.
6. Verfahren nach Anspruch 3, dadurch gekennzeichnet, daß die Vertiefungen (10, 20) durch Sägen erzeugt werden.6. The method according to claim 3, characterized in that the depressions (10, 20) are produced by sawing.
7. Verfahren nach einem der Ansprüche 4 bis 6, dadurch gekennzeichnet, daß in den freigelegten Flächenabschnitten des Basisbereichs jeweils eine dünne hochdotierte7. The method according to any one of claims 4 to 6, characterized in that in each case a thin highly doped in the exposed surface sections of the base region
Schicht (4, 5) gleichen Leitfähigkeitstyps erzeugt wird.Layer (4, 5) of the same conductivity type is generated.
8. Verfahren nach Anspruch 7, dadurch gekennzeichnet, daß die dünne hochdotierte Schicht (4,5)- durch Diffusion erzeugt wird.8. The method according to claim 7, characterized in that the thin highly doped layer (4,5) - is generated by diffusion.
9. Verfahren nach Anspruch 7, dadurch gekennzeichnet, daß die dünne hochdotierte Schicht (4,5) durch Aufdampfen und Legieren von Dotierungsmetallen erzeugt wird. 9. The method according to claim 7, characterized in that the thin, highly doped layer (4,5) is produced by vapor deposition and alloying of doping metals.
10. Verfahren nach einem der Ansprüche 3 bis 9, dadurch gekennzeichnet, daß die Kαntaktmetallüberzüge (6,7) durch stromloses Abscheiden von Kontaktmetallen hergestellt werden.10. The method according to any one of claims 3 to 9, characterized in that the contact metal coatings (6,7) are produced by electroless deposition of contact metals.
11. Verfahren nach einem der Ansprüche 3 bis 9 , dadurch gekennzei chnet , daß die Kontaktmetallüberzüge (6,7) durch Aufdampfen und Legieren hergestellt werden.11. The method according to any one of claims 3 to 9, characterized in that the contact metal coatings (6,7) are produced by vapor deposition and alloying.
12. Verfahren nach den Ansprüchen 10 oder 11, dadurch gekennzeichnet, daß zur Haftverbesserung der KαntaktmetallÜberzüge (6,7) die Oberflächen der Ausgansscheibe durch Sandstrahlen aufgerauht werden.12. The method according to claims 10 or 11, characterized in that the surfaces of the exit disk are roughened by sandblasting to improve the adhesion of the contact metal coatings (6, 7).
13. Verfahren nach einem der vorhergehenden Ansprüche, dadurch gekennzeichnet, daß Kontaktmetalle verwendet werden, die mit dem Halbleitermaterial der Ausgangsscheibe einen ohm'schen Kontakt bilden und daß die dünne hochdotierte Schicht (4,5) und die Kontaktmetallüberzüge (6,7) in einem Verfahrensschritt hergestellt werden. 13. The method according to any one of the preceding claims, characterized in that contact metals are used which form an ohmic contact with the semiconductor material of the starting disk and that the thin, highly doped layer (4,5) and the contact metal coatings (6,7) in one Process step are produced.
EP80900001A 1978-12-23 1980-07-01 Semiconductor device Withdrawn EP0020666A1 (en)

Applications Claiming Priority (2)

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DE2855972 1978-12-23
DE2855972A DE2855972C2 (en) 1978-12-23 1978-12-23 Semiconductor arrangement with two integrated and anti-parallel connected diodes and process for their production

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DE3435306A1 (en) * 1984-09-26 1986-04-03 Siemens AG, 1000 Berlin und 8000 München METHOD FOR PRODUCING LASER DIODES WITH JUTTED INTEGRATED HEAT SINK
KR940016546A (en) * 1992-12-23 1994-07-23 프레데릭 얀 스미트 Semiconductor device and manufacturing method
GB2285882B (en) * 1994-01-14 1997-12-17 Westinghouse Brake & Signal Semiconductor switching devices
US6033489A (en) * 1998-05-29 2000-03-07 Fairchild Semiconductor Corp. Semiconductor substrate and method of making same

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2748041A (en) * 1952-08-30 1956-05-29 Rca Corp Semiconductor devices and their manufacture
US3039028A (en) * 1955-09-26 1962-06-12 Hoffman Electronics Corp Double based diode
US2985805A (en) * 1958-03-05 1961-05-23 Rca Corp Semiconductor devices
US3005937A (en) * 1958-08-21 1961-10-24 Rca Corp Semiconductor signal translating devices
NL125803C (en) * 1961-01-16
US3519900A (en) * 1967-11-13 1970-07-07 Motorola Inc Temperature compensated reference diodes and methods for making same
DE1916555A1 (en) * 1969-04-01 1971-03-04 Semikron Gleichrichterbau Semiconductor rectifier arrangement and method for its production
US3978514A (en) * 1969-07-18 1976-08-31 Hitachi, Ltd. Diode-integrated high speed thyristor
US3699402A (en) * 1970-07-27 1972-10-17 Gen Electric Hybrid circuit power module
FR2126904B1 (en) * 1970-12-07 1974-04-26 Silec Semi Conducteurs
JPS567304B2 (en) * 1972-08-28 1981-02-17
US3972113A (en) * 1973-05-14 1976-08-03 Mitsubishi Denki Kabushiki Kaisha Process of producing semiconductor devices
DE2610942C2 (en) * 1976-03-16 1983-04-28 Licentia Patent-Verwaltungs-Gmbh, 6000 Frankfurt Method for producing a semiconductor component with semiconductor element units monolithically integrated in a semiconductor body
US4219835A (en) * 1978-02-17 1980-08-26 Siliconix, Inc. VMOS Mesa structure and manufacturing process

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO8001334A1 *

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