DE69917880T2 - Halbleiteranordnung aus vergossenem Kunststoff, Verfahren zu ihrer Herstellung, und Leiterrahmen - Google Patents

Halbleiteranordnung aus vergossenem Kunststoff, Verfahren zu ihrer Herstellung, und Leiterrahmen Download PDF

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Publication number
DE69917880T2
DE69917880T2 DE69917880T DE69917880T DE69917880T2 DE 69917880 T2 DE69917880 T2 DE 69917880T2 DE 69917880 T DE69917880 T DE 69917880T DE 69917880 T DE69917880 T DE 69917880T DE 69917880 T2 DE69917880 T2 DE 69917880T2
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Germany
Prior art keywords
making
semiconductor device
same
lead frame
molded plastic
Prior art date
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Expired - Lifetime
Application number
DE69917880T
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English (en)
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DE69917880D1 (de
Inventor
Masanori Minamio
Kunikazu Takemura
Yuichiro Yamada
Fumito Ito
Takahiro Matsuo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP04604099A external-priority patent/JP3535760B2/ja
Priority claimed from JP11095185A external-priority patent/JP3007632B1/ja
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Publication of DE69917880D1 publication Critical patent/DE69917880D1/de
Application granted granted Critical
Publication of DE69917880T2 publication Critical patent/DE69917880T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565Moulds
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    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49503Lead-frames or other flat leads characterised by the die pad
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    • H01L2224/29001Core members of the layer connector
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
DE69917880T 1999-02-24 1999-11-04 Halbleiteranordnung aus vergossenem Kunststoff, Verfahren zu ihrer Herstellung, und Leiterrahmen Expired - Lifetime DE69917880T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP04604099A JP3535760B2 (ja) 1999-02-24 1999-02-24 樹脂封止型半導体装置,その製造方法及びリードフレーム
JP11095185A JP3007632B1 (ja) 1999-04-01 1999-04-01 樹脂封止型半導体装置およびその製造方法

Publications (2)

Publication Number Publication Date
DE69917880D1 DE69917880D1 (de) 2004-07-15
DE69917880T2 true DE69917880T2 (de) 2004-10-07

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DE69927532T Expired - Lifetime DE69927532T2 (de) 1999-02-24 1999-11-04 Halbleiteranordnung aus vergossenem Kunststoff
DE69932268T Expired - Lifetime DE69932268T2 (de) 1999-02-24 1999-11-04 Halbleiteranordnung aus vergossenem Kunststoff und Verfahren zu Ihrer Herstellung
DE69917880T Expired - Lifetime DE69917880T2 (de) 1999-02-24 1999-11-04 Halbleiteranordnung aus vergossenem Kunststoff, Verfahren zu ihrer Herstellung, und Leiterrahmen

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DE69927532T Expired - Lifetime DE69927532T2 (de) 1999-02-24 1999-11-04 Halbleiteranordnung aus vergossenem Kunststoff
DE69932268T Expired - Lifetime DE69932268T2 (de) 1999-02-24 1999-11-04 Halbleiteranordnung aus vergossenem Kunststoff und Verfahren zu Ihrer Herstellung

Country Status (4)

Country Link
US (2) US6208020B1 (de)
EP (3) EP1032037B1 (de)
DE (3) DE69927532T2 (de)
TW (1) TW428295B (de)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE112018003393B4 (de) 2017-08-30 2023-05-04 Hitachi Astemo, Ltd. Verfahren zur Herstellung eines Leistungshalbleiters

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US20020110354A1 (en) * 1997-01-09 2002-08-15 Osamu Ikeda Image recording and editing apparatus, and method for capturing and editing an image
US6229200B1 (en) 1998-06-10 2001-05-08 Asat Limited Saw-singulated leadless plastic chip carrier
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EP1335428A2 (de) 2003-08-13
US20010007780A1 (en) 2001-07-12
US6338984B2 (en) 2002-01-15
EP1335427A3 (de) 2003-10-08
DE69932268D1 (de) 2006-08-17
DE69927532T2 (de) 2006-03-16
TW428295B (en) 2001-04-01
EP1335427B1 (de) 2005-09-28
DE69932268T2 (de) 2006-11-09
EP1032037A2 (de) 2000-08-30
EP1032037B1 (de) 2004-06-09
EP1335428A3 (de) 2003-10-08
DE69917880D1 (de) 2004-07-15
EP1335427A2 (de) 2003-08-13
US6208020B1 (en) 2001-03-27
DE69927532D1 (de) 2006-02-09
EP1335428B1 (de) 2006-07-05

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