CN100452381C - 导线架式半导体封装件及其导线架 - Google Patents

导线架式半导体封装件及其导线架 Download PDF

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CN100452381C
CN100452381C CNB2005100734773A CN200510073477A CN100452381C CN 100452381 C CN100452381 C CN 100452381C CN B2005100734773 A CNB2005100734773 A CN B2005100734773A CN 200510073477 A CN200510073477 A CN 200510073477A CN 100452381 C CN100452381 C CN 100452381C
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李建唐
杨宗显
林明正
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Siliconware Precision Industries Co Ltd
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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Abstract

一种导线架式半导体封装件及其导线架，该封装件包括：分别具有多个长管脚与短管脚的导线架、至少一个接置在该芯片预置区上的芯片、分别电性连接该芯片上的焊垫与其周围对应的长管脚与短管脚的多条焊线封装胶体；发明的导线架式半导体封装件及其导线架通过长管脚凹槽的设计，使得封胶制程中胶体模流可顺畅流动，因此封装胶体的模流可完全填充在导线架内每一间隙中，不会在间隙中出现模流孔洞，解决了现有技术中封装胶体模流难以填充在相邻长管脚间隙的问题，进而可提高结构强度，改善封装件可靠性。

Description

导线架式半导体封装件及其导线架
技术领域
本发明是关于一种导线架式半导体封装件及其导线架，特别是关于一种用于无芯片座式导线架的半导体封装件及其导线架。
背景技术
薄型小尺寸封装(Thin Small Outline Package，TSOP)是发展非常成熟的封装技术，如图1所示，它将半导体芯片50接置在两侧设有多个管脚51的导线架52上，再利用封装胶体53包覆该芯片50与焊线，从而利用相对两侧外露的管脚51与外界电性连接。
同时，为进一步方便芯片与管脚的电性连接，并提高电性效能与品质，此封装技术也可改为将芯片直接接置在相邻管脚上，成为COLTSOP(Chip on Lead TSOP)，如图2A、图2B所示，制备未具有芯片座的导线架60，该导线架60是由多个对应并排的长管脚61与短管脚62组成，将芯片63粘置在这些加长的长管脚61上进行封装，如美国专利第5,780,925号案揭示的即为此类改良式封装件。
然而，此类封装件在模压制程中会产生严重的品质问题，大大降低其结构的可靠性；如图3所示，该结构中长管脚61的延伸方向与模流的流向相互垂直，所以封装胶体的模流将无法完全填充在每一长管脚61的间隙，特别是位于芯片63正下方的相邻长管脚61间隙的空间，更是模流难以流入填充的区域；因此，模压制程完成后，这些长管脚61间隙空间会出现多个模流未填充的孔洞(Void)64，容易在后续高温制程因受热出现气爆(Popcorn)现象，导致胶体裂缝与整体封装结构的破坏。
美国专利第6,753,206号案提出的封装结构也属于此类封装件，如图4所示，在这些长管脚70的上、下表面堆栈芯片71，此现有技术虽采用各长管脚70间填充不导电胶的方式，但由于其间隙空间极小，注胶的胶量难以控制，所以仍可能出现填充不完全的孔洞，同样会有上述结构品质的问题。
因此，对于无芯片座导线架而言，虽可借由将芯片直接接置在相邻长管脚上方便电性连接，但是如果无法解决模压制程中模流无法在各长管脚间隙填充的问题，则令此技术难以量产也难以商品化，进而也难以发挥电性设计上的优越性。
综上所述，如何开发一种导线架式半导体封装件及其导线架，能够使模流充分填充在各管脚与芯片间的间隙空间，已为此类相关研发领域迫切待解的课题。
发明内容
为克服上述现有技术的缺点，本发明的主要目的在于提供一种封装胶体的模流可完全填充在导线架内每一间隙的导线架式半导体封装件及其导线架。
本发明的还一目的在于提供一种各管脚间不会出现模流孔洞的导线架式半导体封装件及其导线架。
本发明的另一目的在于提供一种具有高可靠性的导线架式半导体封装件及其导线架。
本发明的再一目的在于提供一种在封胶制程中胶体模流可顺畅流动的导线架式半导体封装件及其导线架。
为达上述及其它目的，本发明的导线架式半导体封装件包括：导线架，分别具有多个长管脚与短管脚，且该多个长管脚上定义有一芯片预置区，同时，该芯片预置区内至少部分长管脚表面具有一凹槽；至少一个芯片，接置在该芯片预置区上，且覆盖这些凹槽；多条焊线，分别用于电性连接该芯片上的焊垫与其周围对应的长管脚与短管脚；以及封装胶体，用于包覆该芯片、多条焊线、部分长管脚与部分短管脚，并填充在这些凹槽内。
本发明的导线架则包括：导线架框体；多个短管脚，与该导线架框体连接；以及多个长管脚，与该导线架框体连接，且该多个长管脚定义有一芯片预置区，同时，该芯片预置区内至少部分长管脚表面具有一凹槽。
上述多个凹槽形成该封装胶体模流的通道，可令该封装胶体模流借由该凹槽流到相邻长管脚间的间隙空间；同时，该多个凹槽是以半蚀刻方式形成的，且该凹槽的宽度小于该芯片预置区的宽度，该凹槽的深度较佳约为该长管脚高度的一半。
综上所述，本发明通过长管脚凹槽的设计，使得封胶制程中胶体模流可顺畅流动，因此封装胶体的模流可完全填充在导线架内每一间隙中，不会在间隙中出现模流孔洞，解决了现有技术中封装胶体模流难以填充在相邻长管脚间隙的问题，进而可提高结构强度，改善封装件可靠性。
附图说明
图1是现有TSOP封装件的示意图；
图2A是现有COL TSOP封装件的俯视图；
图2B是现有COL TSOP封装件的剖视图；
图3是图2A、图2B图所示的现有封装件在模压制程出现孔洞的俯视图；
图4是美国专利第6,753,206号揭示的现有封装件剖视图；
图5A是本发明的导线架俯视图；
图5B是本发明的导线架剖视图；
图6A是本发明的导线架式封装件俯视图；
图6B是本发明的导线架式封装件剖视图；以及
图7是本发明实施例2剖视图。
具体实施方式
实施例1
以下通过特定的具体实例说明本发明的实施方式。
如图5A、图5B所示，本发明的导线架式半导体封装件的导线架包括：导线架框体10、多个短管脚11以及多个长管脚12。该导线架框体10是方形，多个短管脚11与该导线架框体10连接，多个长管脚12与该导线架框体10连接，这些长管脚12与短管脚11分别对应排列；其中，该多个长管脚12上定义有一芯片预置区15(虚线区域)，同时，该芯片预置区15内的部分长管脚12的表面具有一凹槽20，令该长管脚12的中间区段呈现一凹陷区域。
该多个凹槽20是以半蚀刻(Half-Etching)方式形成的，且该凹槽20的宽度小于该芯片预置区15的宽度，该凹槽20的深度较佳约为该长管脚12高度的一半；因此这些凹槽20围置而成的方形区域的面积将略小于该芯片预置区15，在接置芯片25后被该芯片25所覆盖，进而在后续封胶制程时形成封装胶体30模流的通道，使封装胶体30模流借由这些凹槽20流到相邻长管脚12间的间隙空间18，充满这些空间。
如图6A、图6B所示，本发明的导线架式半导体封装件包括：导线架100、至少一个芯片25、多条焊线35以及封装胶体30。该导线架100具有多个长管脚12与短管脚11，这些长管脚12与短管脚11分别对应排列，且该多个长管脚12上定义有一芯片预置区15，该芯片预置区15内的部分长管脚12表面形成有一凹槽20。
该多个凹槽20是以半蚀刻方式形成的，其形状与尺寸并无限制，但该凹槽20的宽度小于该芯片预置区15的宽度，且其深度较佳约为该长管脚12高度的一半；因此，这些凹槽20围置而成的区域面积将略小于该芯片预置区15。
该多个长管脚12上接置有一芯片25，该芯片25接置在该芯片预置区15上，且覆盖住这些凹槽20，此时，该凹槽20的表面与芯片25的下表面间具有一间隙d(如图6B所示)，该间隙d在后续封胶制程时形成封装胶体30模流的通道，封装胶体30模流可借由这些凹槽20流到相邻长管脚12间的间隙空间18，并充满这些空间。
该多条焊线35是金线，分别电性连接该芯片25上的焊垫(未标出)与其周围的对应长管脚12或短管脚11，使该芯片25上的信号可传递到两相对侧的长管脚12、短管脚11(一侧为长管脚12，一侧为短管脚11)，然后再传递到外部如印刷电路板等电子装置。
该封装胶体30用于包覆该芯片25、多条焊线35、部分长管脚12与部分短管脚11，该封装胶体30在注胶过程中，利用该芯片25与凹槽20间的模流通道，填充在这些凹槽20内，进而流入每一长管脚12间的间隙空间18，使这些间隙空间18均完全被填充，不再出现孔洞。
实施例2
本发明的设计也可用于多芯片的结构中，如图7所示，它是在这些长管脚12的上、下两表面均接置芯片25，这些长管脚12受芯片25覆盖的区域也同样蚀刻有凹槽20，作为封装胶体30模流的通道，供模流流过并填充间隙，解决现有技术的问题。
综上所述，本发明是根据模流流动方向，在芯片下方的长管脚表面蚀刻凹槽，进而借由这些凹槽形成封装胶体模流的通道，使相邻长管脚间的间隙空间均可完全充满胶体模流，至于凹槽的尺寸、形状、数量，乃至具有凹槽的长管脚个数和排列，可根据不同结构与尺寸而加以变化。
因此，通过本发明的长管脚凹槽设计，可解决现有技术中封装胶体模流难以填充在相邻长管脚间隙的问题，进而可提高结构强度，发挥并改善封装件可靠性的功效。

Claims (14)

1.一种导线架式半导体封装件，其特征在于，该封装件包括：
导线架，分别具有多个长管脚与短管脚，且该多个长管脚上定义有一芯片预置区，同时，该芯片预置区内至少部分长管脚表面具有一凹槽；
至少一个芯片，接置在该芯片预置区上，且覆盖这些凹槽；
多条焊线，分别用于电性连接该芯片上的焊垫与其周围对应的长管脚与短管脚；以及
封装胶体，用于包覆该芯片、多条焊线、部分长管脚与部分短管脚，并填充在这些凹槽内。
2.如权利要求1所述的导线架式半导体封装件，其特征在于，该多个凹槽形成该封装胶体模流的通道。
3.如权利要求2所述的导线架式半导体封装件，其特征在于，该封装胶体模流借由该凹槽流到相邻长管脚间的间隙空间。
4.如权利要求1所述的导线架式半导体封装件，其特征在于，该多个凹槽是以半蚀刻方式形成的。
5.如权利要求1所述的导线架式半导体封装件，其特征在于，该凹槽的宽度小于该芯片预置区的宽度。
6.如权利要求1所述的导线架式半导体封装件，其特征在于，该凹槽的深度为该长管脚高度的一半。
7.如权利要求1所述的导线架式半导体封装件，其特征在于，相邻长管脚间的间隙空间均填充有该封装胶体。
8.如权利要求1所述的导线架式半导体封装件，其特征在于，该长管脚的上、下两表面均可接置芯片。
9.一种导线架，其特征在于，该导线架包括：
导线架框体；
多个短管脚，与该导线架框体连接；以及
多个长管脚，与该导线架框体连接，且该多个长管脚定义有一芯片预置区，该芯片预置区内至少部分长管脚表面具有一凹槽，同时，该多个长管脚与接置在该芯片预置区上的芯片电性连接。
10.如权利要求9所述的导线架，其特征在于，该多个凹槽形成封装胶体模流的通道。
11.如权利要求10所述的导线架，其特征在于，该封装胶体模流是借由该凹槽流到相邻长管脚间的间隙空间。
12.如权利要求9所述的导线架，其特征在于，该多个凹槽是以半蚀刻方式形成的。
13.如权利要求9所述的导线架，其特征在于，该凹槽的宽度小于该芯片预置区的宽度。
14.如权利要求9所述的导线架，其特征在于，该凹槽的深度为该长管脚高度的一半。
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6191488B1 (en) * 1998-10-06 2001-02-20 Oki Electric Industry Co., Ltd. Flip chip type semiconductor package and method of injecting resin into device thereof
US6208020B1 (en) * 1999-02-24 2001-03-27 Matsushita Electronics Corporation Leadframe for use in manufacturing a resin-molded semiconductor device
CN1466201A (zh) * 2002-06-28 2004-01-07 矽品精密工业股份有限公司 芯片座具凹部的半导体封装件

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6191488B1 (en) * 1998-10-06 2001-02-20 Oki Electric Industry Co., Ltd. Flip chip type semiconductor package and method of injecting resin into device thereof
US6208020B1 (en) * 1999-02-24 2001-03-27 Matsushita Electronics Corporation Leadframe for use in manufacturing a resin-molded semiconductor device
CN1466201A (zh) * 2002-06-28 2004-01-07 矽品精密工业股份有限公司 芯片座具凹部的半导体封装件

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