CN101540308B - 半导体芯片封装 - Google Patents

半导体芯片封装 Download PDF

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CN101540308B
CN101540308B CN2008101322539A CN200810132253A CN101540308B CN 101540308 B CN101540308 B CN 101540308B CN 2008101322539 A CN2008101322539 A CN 2008101322539A CN 200810132253 A CN200810132253 A CN 200810132253A CN 101540308 B CN101540308 B CN 101540308B
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packaging
base plate
die package
semiconductor die
package according
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陈南璋
林泓均
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MediaTek Inc
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Abstract

本发明提供一种半导体芯片封装，包含：导线架，具有芯片载体，其中芯片载体具有第一表面与相对的第二表面；半导体芯片，安装在第一表面上，其中半导体芯片具有多个焊盘，且半导体芯片的面积大于芯片载体的面积；以及封装基板，包含附着在第二表面的中央区域，并且封装基板的面积大于半导体芯片的面积，其中半导体芯片的该多个焊盘的一部分电性连接至封装基板的边缘区域。本发明提供的半导体芯片封装设计能够提供给半导体芯片大量的输入/输出连接，并且可通过其简单的布局来降低制造成本并且提升良品率。

Description

半导体芯片封装 
技术领域
本发明是关于半导体芯片封装(semiconductor chip package)，特别是关于具有增加输入/输出连接(input/output connections)数量的半导体芯片封装。 
背景技术
在半导体芯片封装设计中，对于多功能芯片的输入/输出连接数量的需求日益增加。然而，对于现有的导线架半导体封装(lead frame based semiconductorpackage)而言，半导体芯片的输入/输出连接的导脚数量是有限的。为了解决上述问题，开发了球栅阵列半导体封装(ball grid array semiconductor package，BGA)，以通过位于半导体芯片封装的封装基板(package substrate)底部的锡球(solder ball)来提供更多的输入/输出连接。增加输入/输出连接数量的需求可以通过更密的锡球跨距(ball pitch)来实现。然而，与现有的导线架半导体封装相比较，球栅阵列半导体封装由于附加的锡球的电性连接，因此具有较差的良品率与较高的制造成本。 
因此，需要一种新型的半导体封装设计，使其具有更多的输入/输出连接并且其制造成本处于导线架半导体封装与球栅阵列半导体封装之间。 
发明内容
为了解决现有半导体封装技术中制造成本与输入/输出连接数量不能同时兼顾的问题，本发明提供一种半导体芯片封装。 
依据本发明的一方面，其提供一种半导体芯片封装，包含：导线架，具有芯片载体，其中芯片载体具有第一表面与相对的第二表面；半导体芯片，安装在第一表面上，其中半导体芯片具有多个焊盘，以及半导体芯片的面积大于芯片载体的面积；以及封装基板，包含附着在第二表面的中央区域，并且封装基板的面积大于半导体芯片的面积，其中半导体芯片的该多个焊盘的部分电性连接至封装基板的边缘区域。 
依据本发明另一方面，其提供一种半导体芯片封装，包含：导线架，具有芯片载体；半导体芯片，附着在芯片载体的一侧，半导体芯片上具有多个焊盘，其中半导体芯片的面积大于芯片载体的面积；以及封装基板，附着在芯片载体的另一侧，封装基板的面积大于半导体芯片的面积，其中半导体芯片的焊盘的一部分电性连接至封装基板的上表面，并且上表面面向芯片载体。 
依据本发明再一方面，其提供一种半导体芯片封装，包含：导线架，具有芯片载体与多个导脚；半导体芯片，安装于芯片载体的一侧，并且具有多个焊盘；以及封装基板，具有附着在芯片载体的另一侧的上表面，其中芯片载体的面积小于半导体芯片与封装基板的面积，多个焊盘的一部分电性连接至封装基板的上表面，并且剩余的焊盘分别电性连接至导脚。 
本发明提供的半导体芯片封装设计能够提供给半导体芯片大量的输入/输出连接，并且可通过其简单的布局来降低制造成本并且提升良品率。 
附图说明
图1a是依据本发明的实施方式的半导体芯片封装的简要顶视图 
图1b是依据本发明的实施方式的半导体芯片封装的截面的简要示意图。 
图2是依据本发明的实施方式的半导体芯片封装500的组合示意图。 
图3a至图3e绘示了导线架200的芯片载体206的各种不同设计。 
图4a为依据本发明的实施方式的半导体芯片封装的封装基板的简要顶视图。 
图4b为图4a的一部分的放大示意图。 
图5是依据本发明的实施方式的组装半导体芯片封装的制造过程示意图。 
具体实施方式
配合附图，透过以下详细的描述、范例，可更了解本发明所揭露的所有实施方式的各个观点。 
本发明的实施方式提供一种半导体芯片封装。图1a与图1b是依据本发明的一个实施方式的半导体芯片封装500的简要示意图。图2是依据本发明的实施方式的半导体芯片封装500的组合示意图。依据本发明的实施方式，半导体芯片封装500可包含四侧引脚扁平封装(low-profile quad flat package，LQFP)。半导体芯片封装500包含导线架200，导线架200包含多个单体导脚(discrete lead)204、支撑架(supporting bond)202以及芯片载体(chip carrier)206。芯片载体206位于导线架200的中心部分，并且电性连接至支撑架202。芯片载体206具有第一表面232及与第一表面232相对的第二表面234。 
半导体芯片208通过粘结材料214附着在第一表面232上。半导体芯片208具有多个焊盘(bonding pad)210。依据本发明的实施方式，如图1a所示，焊盘210可位于半导体芯片208的邻近边缘。如图1a与图1b所示，半导体芯片208的面积可大于芯片载体206的面积。 
封装基板218包含中央区域220与边缘区域222，其中，中央区域220通过粘结材料216附着至芯片载体206的第二表面234，而边缘区域222暴露于芯片载体206之外。依据本发明的实施方式，封装基板218可包含球栅阵列(BGA)基板。封装基板218具有上表面242与下表面244，其中上表面242面向芯片载体206的第二表面234。依据本发明的实施方式，封装基板218的面积可大于半导体芯片208的面积。对应于边缘区域222的上表面242上形成有多个导体板(conductive plane)226以及252，并且对应于中央区域220的上表面242上形成有导体板227。对封装基板218钻孔得到多个通孔(via)224，其中部分通孔224电性连接至导体板226、227以及252。半导体芯片封装500进一步可包含位于封装基板218边缘并且穿过封装基板218的多个凹槽(recess)246。凹槽246可位于导体板252上。如图1b所示，位于封装基板218的下表面244的多个锡球垫(ball pad)228电性连接至通孔224。依据本发明的实施方式，各导体板226、227与252可分别经由通孔224电性连接至相应的锡球垫228。半导体芯片500可进一步包含形成于锡球垫228上的锡球(图中未标示)，以提供给最终产品的印制电路板(图中未标示)互连。 
如图1a与图1b所示，一些焊盘210，例如，邻近半导体芯片208边缘的焊盘210，分别经由焊线(bonding wire)212b电性连接至位于封装基板218边缘区域222的导体板226。而剩余的焊盘210，例如，远离半导体芯片208的焊盘210，经由焊线212a分别电性连接至导脚204。为了实现半导体芯片208与封装基板218之间焊线212b的电性连接，芯片载体206的面积可小于半导体芯片208与封装基板218的面积，并且封装基板218的面积可大于半导体芯片208的面积。可利用覆盖材料230，例如通过充型(mold filling)，来封装半导体芯片208、导线架200的内部以及封装基板218的一部分，使封装基板218的下表面244暴露于覆盖材料230之外。 
图3a至图3e绘示了导线架200的芯片载体206的各种不同设计，以优化半导体芯片208、芯片载体206以及封装基板218之间的粘结强度。如图3a所示，芯片载体206可以是支撑架202的交叉区域。如图3b所示，芯片载体206可以为方形。在本发明的一些实施方式中，如图3c至图3e所示，芯片载体206可具有形成于其内的孔250。备选地，可在芯片载体206外形成附加的支撑架260，并且将其连接至支撑架202，以增强芯片载体206与封装基板218之间的粘结强度。孔250可依据设计需要设计为多种形状，例如方形、梯形、圆形或者相类似的其它形状，且本发明并不限于此。 
图4a与图4b为依据本发明的实施方式的半导体芯片封装的封装基板218的设计的简要示意图。封装基板218不但提供一些半导体芯片208的输入/输出连接，还作为半导体芯片208的散热器(heat sink)。封装基板218可包含中央区域220与边缘区域222。位于封装基板218的上表面242的中央区域220附着并且电性连接至芯片载体206的第二表面234，并且中央区域220上具有导体板227。依据本发明的实施方式，封装基板218的中央区域220提供半导体芯片208的接地路径，例如数字电路接地路径。并且，位于中央区域220的通孔224可用来减少热阻。多个导体板226、252、256以及258可位于封装基板218的边缘区域222的上表面242，分别电性连接至半导体芯片208的多个焊盘210(如图1a所示)。依据本发明的实施方式，导体板226与导体板252可向半导体芯片208提供多个电源路径及/或接地路径，例如，模拟电路的电源路径及/或接地路径。对封装基板218钻孔得到多个通孔224，其中一部分通孔224电性连接至导体板226、227、256以及258。每一导体板226、227、256以及258可分别经由通孔224电性连接至下表面244相应的锡球垫228(如图1b所示)。 
此外，封装基板218的导体板256、258可提供用于传输数据的装置接口连接，例如，通用串行总线(universal serial bus，USB)、高清晰度多媒体接口(highdefinition multimedia interface，HDMI)、串行高级技术附件(serial advancedtechnology attachment，SATA)或者其它相似装置接口。如图4a所示，位于边缘区域222的导体板258、256可分别作为装置接口的成对差分信号线(differentialpair net)与阻抗控制板(impedance control plane)。与现有的导线架半导体封装相比较，可以缩减半导体芯片208的焊线长度以具有更好的电性能，例如，减小电阻和电感。 
更进一步，多个电子组件240与254可附着在封装基板218上，经由焊线 212b与通孔224电性连接至焊盘210(如图1a与图1b所示)。上述电子组件240与254可包含电源环线(power rings)、接地环线(ground rings)、电容、电阻、二极管或者电感等无源组件。例如，电子组件240可作为螺旋电感走线(spiral inductor trace)，并设置于封装基板218的下表面244上，经由通孔245与焊线212b(如图1a与图1b所示)电性连接至焊盘210。由于通常情况下，无法从顶视图上看见电感240，所以在图4a中利用虚线绘示出电感240。此外，电子组件254可作为去耦电容(de-coupling capacitor)，并设置于上表面242上，并且处于接地层(ground plane)与电源层(power plane)之间(例如，导体板227与导体板252)。去耦电容254可用来减少电路产生的噪声。与现有导线架半导体封装相比较，封装基板218可为半导体芯片208提供附加的电性连接，例如，电源路径以及/或者接地路径。封装基板218也可提供可附着电子组件(例如电源环线、接地环线、电容、电阻或者电感)的面积。并且可以增强一些电性能，例如电源电路电感或者接地电路电感。与现有的球栅阵列半导体封装相比较，封装基板218可具有简单的布局(layout)，例如，无密间距的大电源层与接地层。因此，可以降低制造成本并且增加良品率。 
图4b是图4a的一部分的放大示意图。依据本发明的一个实施方式，可于封装基板218的边缘处设计凹槽246，并且凹槽246穿过封装基板218。可首先在封装基板218上钻孔(图中未标示)，然后透过封装基板218切割，以形成凹槽246。凹槽246可提供至上表面242与下表面244的附加的电性连接路径。同时，凹槽246可增加封装基板218的表面粗糙度。因此，可以增加覆盖材料230与封装基板218之间的结合强度。 
图5是依据本发明的实施方式的组装半导体芯片封装500的制造过程示意图。如步骤1502所示，组装半导体芯片封装500的步骤包含通过粘结材料214将半导体芯片208附着在芯片载体206的第一表面232上。如步骤1504所示，封装基板218的中央区域220通过粘结材料216附着在芯片载体206的第二表面234上，使边缘区域222暴露于芯片载体206之外。如步骤1506所示，利用部分焊线212电性连接焊盘210与位于封装基板218的边缘区域222的导体板226，剩余的焊线212连接焊盘210与导脚204。如步骤1508所示，覆盖材料230利用成型(molding)来封装半导体芯片208、导线架200的内部以及部分封装基板218，并且使封装基板218的下表面244暴露于覆盖材料230之外。如步骤1510所示，打包(package)产生的半导体芯片封装500以完成产品交货。 
上述半导体芯片封装500仅作为举例说明之用。以下将详述依据本发明的实施方式的半导体芯片封装500的优点。封装基板218不仅作为半导体芯片208的散热器，同时也提供给半导体芯片208大量的输入/输出连接。与现有的导线架半导体封装相比较，封装基板218可提供给半导体芯片208附加的电性连接，例如电源路径以及/或者接地路径。封装基板218也可为设置于其上的电子组件(例如电源环线、接地环线、电感走线、二极管、电容、电阻或者电感)提供面积，并且可以增强一些电性能，例如降低电源电路电感或者接地电路电感。与现有的球栅阵列半导体封装相比较，封装基板218可具有简单的布局。因此，可以降低制造成本并且提升良品率。位于中央区域220的通孔224可以用来减少热阻。导线架200的芯片载体206可具有各种不同的设计，以优化半导体芯片208、芯片载体206与封装基板218之间的粘结强度。 
以上所述仅为本发明的较佳实施方式，凡依本发明权利要求所做的均等变化与修饰，都应属本度明的涵盖范围。 

Claims (28)

1. 一种半导体芯片封装，包含：
导线架，具有芯片载体，其中该芯片载体具有第一表面与相对的第二表面；
半导体芯片，安装在该第一表面上，其中该半导体芯片具有多个焊盘，以及该半导体芯片的面积大于该芯片载体的面积；以及
封装基板，包含附着在该第二表面的中央区域，并且该封装基板的面积大于该半导体芯片的面积，其中该半导体芯片的该多个焊盘的一部分电性连接至该封装基板的边缘区域。
2. 根据权利要求1所述的半导体芯片封装，其特征在于，该半导体芯片的该多个焊盘的一部分电性连接至该封装基板的上表面，其中该上表面面向该芯片载体的第二表面。
3. 根据权利要求1所述的半导体芯片封装，其特征在于，该导线架包含多个导脚，并且该多个导脚中至少一个电性连接至该多个焊盘其中之一。
4. 根据权利要求1所述的半导体芯片封装，其特征在于，更包含多个孔，形成于该芯片载体内。
5. 根据权利要求2所述的半导体芯片封装，其特征在于，更包含：
多个导体板，位于该边缘区域的上表面，并且电性连接至该半导体芯片的该多个焊盘；
多个通孔，其贯通该封装基板，其中该多个通孔的一部分电性连接至该多个导体板；以及
多个电子组件，其位于该封装基板上，电性连接至部分该多个焊盘。
6. 根据权利要求5所述的半导体芯片封装，其特征在于，更包含该封装基板边缘上的凹槽，位于该多个导体板其中之一内。
7. 根据权利要求5所述的半导体芯片封装，其特征在于，该多个导体板包含多个电源层或者多个接地层。
8. 根据权利要求5所述的半导体芯片封装，其特征在于，该多个电子组件包含多个电源环线、多个接地环线、多个电感走线、多个电容、多个电阻、多个二极管或者多个电感。
9. 根据权利要求5所述的半导体芯片封装，其特征在于，该多个导体板分别为用于装置接口连接的成对差分信号线与阻抗控制板。
10. 根据权利要求1所述的半导体芯片封装，其特征在于，更包含：
覆盖材料，封装该半导体芯片、该导线架的内部以及该封装基板的一部分，并且使该封装基板的下表面暴露于该覆盖材料之外。
11. 一种半导体芯片封装，包含：
导线架，具有芯片载体；
半导体芯片，安装于该芯片载体的一侧，该半导体芯片上具有多个焊盘，其中该半导体芯片的面积大于该芯片载体的面积；以及
封装基板，附着在该芯片载体的另一侧，该封装基板的面积大于该半导体芯片的面积，其中该半导体芯片的该多个焊盘的一部分电性连接至该封装基板的上表面，并且该上表面面向该芯片载体。
12. 根据权利要求11所述的半导体芯片封装，其特征在于，该导线架包含多个导脚，并且该多个导脚中至少一个电性连接至该多个焊盘其中之一。
13. 根据权利要求11所述的半导体芯片封装，其特征在于，更包含多个孔，形成于该芯片载体内。
14. 根据权利要求11所述的半导体芯片封装，其特征在于，更包含：
多个导体板，其位于该封装基板的该上表面，并且电性连接至该半导体芯片；
多个通孔，其贯通该封装基板，其中部分该多个通孔电性连接至该多个导体板；以及
多个电子组件，其位于该封装基板上，电性连接至部分该多个焊盘。
15. 根据权利要求14所述的半导体芯片封装，其特征在于，更包含该封装基板边缘上的凹槽，位于该多个导体板其中之一内。
16. 根据权利要求14所述的半导体芯片封装，其特征在于，该多个导体板包含多个电源层或者多个接地层。
17. 根据权利要求14所述的半导体芯片封装，其特征在于，该多个电子组件包含多个电源环线、多个接地环线、多个电感走线、多个电容、多个电阻、多个二极管或者多个电感。
18. 根据权利要求14所述的半导体芯片封装，其特征在于，该多个导体板分别为用于装置接口连接的成对差分信号线与阻抗控制板。
19. 根据权利要求11所述的半导体芯片封装，其特征在于，更包含：
覆盖材料，封装该半导体芯片、该导线架的内部以及部分该封装基板，并且使该封装基板的下表面暴露于该覆盖材料之外。
20. 一种半导体芯片封装，包含：
导线架，具有芯片载体与多个导脚；
半导体芯片，安装于该芯片载体的一侧，并且具有多个焊盘；以及
封装基板，具有附着在该芯片载体的另一侧的上表面，其中该芯片载体的面积小于该半导体芯片与该封装基板的面积，该多个焊盘的一部分电性连接至该封装基板的该上表面，并且剩余的该多个焊盘分别电性连接至该多个导脚。
21. 根据权利要求20所述的半导体芯片封装，其特征在于，该多个焊盘的一部分电性连接至该封装基板的边缘区域，并且该边缘区域并没有附着于该芯片载体。
22. 根据权利要求20所述的半导体芯片封装，其特征在于，更包含形成于该芯片载体内的多个孔。
23. 根据权利要求20所述的半导体芯片封装，其特征在于，更包含：
多个导体板，其位于该封装基板的该上表面，并且电性连接至该半导体芯片；
多个通孔，其贯通该封装基板，其中该多个通孔的一部分电性连接至该多个导体板；以及
多个电子组件，其位于该封装基板上，电性连接至部分该多个焊盘。
24. 根据权利要求23所述的半导体芯片封装，其特征在于，更包含该封装基板的边缘上的凹槽，位于该多个导体板其中之一内。
25. 根据权利要求23所述的半导体芯片封装，其特征在于，该多个导体板包含多个电源层或者多个接地层。
26. 根据权利要求23所述的半导体芯片封装，其特征在于，该多个电子组件包含多个电源环线、多个接地环线、多个电感走线、多个电容、多个电阻、多个二极管或者多个电感。
27. 根据权利要求23所述的半导体芯片封装，其特征在于，该多个导体板是分别为用于装置接口连接的成对差分信号线与阻抗控制板。
28. 根据权利要求20所述的半导体芯片封装，其特征在于，更包含：
覆盖材料，封装该半导体芯片、该导线架的内部以及部分该封装基板，并且使该封装基板的下表面暴露于该覆盖材料之外。
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