CN1098557A - 带有x形管芯支托的半导体器件及其制造方法 - Google Patents
带有x形管芯支托的半导体器件及其制造方法 Download PDFInfo
- Publication number
- CN1098557A CN1098557A CN94103949A CN94103949A CN1098557A CN 1098557 A CN1098557 A CN 1098557A CN 94103949 A CN94103949 A CN 94103949A CN 94103949 A CN94103949 A CN 94103949A CN 1098557 A CN1098557 A CN 1098557A
- Authority
- CN
- China
- Prior art keywords
- connecting rod
- tube core
- area
- semiconductor device
- lead
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49503—Lead-frames or other flat leads characterised by the die pad
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05553—Shape in top view being rectangular
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/3201—Structure
- H01L2224/32012—Structure relative to the bonding area, e.g. bond pad
- H01L2224/32014—Structure relative to the bonding area, e.g. bond pad the layer connector being smaller than the bonding area, e.g. bond pad
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01014—Silicon [Si]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
Claims (10)
Applications Claiming Priority (6)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US035422 | 1993-03-22 | ||
US08/035,422 US5327008A (en) | 1993-03-22 | 1993-03-22 | Semiconductor device having universal low-stress die support and method for making the same |
US035,422 | 1993-10-12 | ||
US133947 | 1993-10-12 | ||
US133,947 | 1993-10-12 | ||
US08/133,947 US5424576A (en) | 1993-03-22 | 1993-10-12 | Semiconductor device having x-shaped die support member and method for making the same |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CNA021548471A Division CN1514490A (zh) | 1993-03-22 | 1994-03-21 | 带有x形管芯支托的半导体器件及其制造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN1098557A true CN1098557A (zh) | 1995-02-08 |
CN1118873C CN1118873C (zh) | 2003-08-20 |
Family
ID=26712107
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN94103949A Expired - Lifetime CN1118873C (zh) | 1993-03-22 | 1994-03-21 | 带有x形管芯支托的半导体器件 |
CNA021548471A Pending CN1514490A (zh) | 1993-03-22 | 1994-03-21 | 带有x形管芯支托的半导体器件及其制造方法 |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CNA021548471A Pending CN1514490A (zh) | 1993-03-22 | 1994-03-21 | 带有x形管芯支托的半导体器件及其制造方法 |
Country Status (5)
Country | Link |
---|---|
EP (1) | EP0617464B1 (zh) |
JP (1) | JP2838160B2 (zh) |
CN (2) | CN1118873C (zh) |
DE (1) | DE69430648T2 (zh) |
SG (1) | SG75769A1 (zh) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1101598C (zh) * | 1997-03-24 | 2003-02-12 | 精工爱普生株式会社 | 半导体装置用基板、半导体装置及其制造方法、电路基板和电子装置 |
CN101866904A (zh) * | 2009-04-16 | 2010-10-20 | 联发科技股份有限公司 | 半导体芯片封装结构 |
CN101540308B (zh) * | 2008-03-18 | 2010-12-08 | 联发科技股份有限公司 | 半导体芯片封装 |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001074904A (ja) | 1999-09-02 | 2001-03-23 | Canon Inc | 二波長反射防止膜 |
KR100355794B1 (ko) * | 1999-10-15 | 2002-10-19 | 앰코 테크놀로지 코리아 주식회사 | 리드프레임 및 이를 이용한 반도체패키지 |
JP2005079181A (ja) * | 2003-08-28 | 2005-03-24 | Matsushita Electric Ind Co Ltd | リードフレーム、それを用いた樹脂封止型半導体装置およびその製造方法 |
JP5569097B2 (ja) | 2010-03-29 | 2014-08-13 | 富士通セミコンダクター株式会社 | 半導体装置及びリードフレーム |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5866346A (ja) * | 1981-10-16 | 1983-04-20 | Nec Kyushu Ltd | 半導体装置 |
JPS6072236A (ja) * | 1983-09-28 | 1985-04-24 | Toshiba Corp | 半導体装置 |
JPS61110454A (ja) * | 1984-11-02 | 1986-05-28 | Nec Corp | 混成集積回路装置 |
JPS6381966A (ja) * | 1986-09-26 | 1988-04-12 | Hitachi Ltd | 電子装置 |
JP2534251B2 (ja) * | 1987-02-20 | 1996-09-11 | 日東電工株式会社 | 半導体装置 |
JPH0274065A (ja) * | 1988-09-09 | 1990-03-14 | Matsushita Electron Corp | リードフレーム |
JPH04363056A (ja) * | 1990-11-20 | 1992-12-15 | Seiko Epson Corp | 集積回路用リードフレーム及びその製造方法 |
-
1994
- 1994-03-03 EP EP94103166A patent/EP0617464B1/en not_active Expired - Lifetime
- 1994-03-03 DE DE69430648T patent/DE69430648T2/de not_active Expired - Lifetime
- 1994-03-03 SG SG1996003719A patent/SG75769A1/en unknown
- 1994-03-15 JP JP6071548A patent/JP2838160B2/ja not_active Expired - Lifetime
- 1994-03-21 CN CN94103949A patent/CN1118873C/zh not_active Expired - Lifetime
- 1994-03-21 CN CNA021548471A patent/CN1514490A/zh active Pending
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1101598C (zh) * | 1997-03-24 | 2003-02-12 | 精工爱普生株式会社 | 半导体装置用基板、半导体装置及其制造方法、电路基板和电子装置 |
CN101540308B (zh) * | 2008-03-18 | 2010-12-08 | 联发科技股份有限公司 | 半导体芯片封装 |
US7875965B2 (en) | 2008-03-18 | 2011-01-25 | Mediatek Inc. | Semiconductor chip package |
CN101866904A (zh) * | 2009-04-16 | 2010-10-20 | 联发科技股份有限公司 | 半导体芯片封装结构 |
Also Published As
Publication number | Publication date |
---|---|
JP2838160B2 (ja) | 1998-12-16 |
EP0617464A2 (en) | 1994-09-28 |
EP0617464B1 (en) | 2002-05-22 |
DE69430648D1 (de) | 2002-06-27 |
SG75769A1 (en) | 2000-10-24 |
DE69430648T2 (de) | 2002-10-24 |
CN1514490A (zh) | 2004-07-21 |
JPH077124A (ja) | 1995-01-10 |
EP0617464A3 (en) | 1995-05-31 |
CN1118873C (zh) | 2003-08-20 |
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Legal Events
Date | Code | Title | Description |
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C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
ASS | Succession or assignment of patent right |
Owner name: FREEDOM SEMICONDUCTORS CO. Free format text: FORMER OWNER: MOTOROLA, INC. Effective date: 20041210 |
|
C41 | Transfer of patent application or patent right or utility model | ||
TR01 | Transfer of patent right |
Effective date of registration: 20041210 Address after: Texas in the United States Patentee after: FreeScale Semiconductor Address before: Illinois Instrunment Patentee before: Motorola, Inc. |
|
C56 | Change in the name or address of the patentee |
Owner name: FISICAL SEMICONDUCTOR INC. Free format text: FORMER NAME: FREEDOM SEMICONDUCTOR CORP. |
|
CP01 | Change in the name or title of a patent holder |
Address after: Texas in the United States Patentee after: FREESCALE SEMICONDUCTOR, Inc. Address before: Texas in the United States Patentee before: FreeScale Semiconductor |
|
C17 | Cessation of patent right | ||
CX01 | Expiry of patent term |
Expiration termination date: 20140321 Granted publication date: 20030820 |