CN1409392A - 基板在芯片上的芯片阵列式球栅阵列封装的制造方法 - Google Patents
基板在芯片上的芯片阵列式球栅阵列封装的制造方法 Download PDFInfo
- Publication number
- CN1409392A CN1409392A CN02131630A CN02131630A CN1409392A CN 1409392 A CN1409392 A CN 1409392A CN 02131630 A CN02131630 A CN 02131630A CN 02131630 A CN02131630 A CN 02131630A CN 1409392 A CN1409392 A CN 1409392A
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- Prior art keywords
- chip
- base board
- board unit
- grid array
- spherical grid
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73207—Bump and wire connectors
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- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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- H01L2924/01006—Carbon [C]
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- H01L2924/0102—Calcium [Ca]
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- H01L2924/01033—Arsenic [As]
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- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/10251—Elemental semiconductors, i.e. Group IV
- H01L2924/10253—Silicon [Si]
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- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
Description
Claims (5)
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/191,071 US20040009628A1 (en) | 2002-07-10 | 2002-07-10 | Fabrication method of substrate on chip CA ball grid array package |
JP2002218557A JP2004063680A (ja) | 2002-07-10 | 2002-07-26 | チップ上基板のチップアレイ式ボールグリッドアレイパッケージの製造方法 |
CN021316309A CN1218388C (zh) | 2002-07-10 | 2002-09-11 | 基板在芯片上的芯片阵列式球栅阵列封装的制造方法 |
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/191,071 US20040009628A1 (en) | 2002-07-10 | 2002-07-10 | Fabrication method of substrate on chip CA ball grid array package |
JP2002218557A JP2004063680A (ja) | 2002-07-10 | 2002-07-26 | チップ上基板のチップアレイ式ボールグリッドアレイパッケージの製造方法 |
CN021316309A CN1218388C (zh) | 2002-07-10 | 2002-09-11 | 基板在芯片上的芯片阵列式球栅阵列封装的制造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN1409392A true CN1409392A (zh) | 2003-04-09 |
CN1218388C CN1218388C (zh) | 2005-09-07 |
Family
ID=32314672
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN021316309A Expired - Fee Related CN1218388C (zh) | 2002-07-10 | 2002-09-11 | 基板在芯片上的芯片阵列式球栅阵列封装的制造方法 |
Country Status (3)
Country | Link |
---|---|
US (1) | US20040009628A1 (zh) |
JP (1) | JP2004063680A (zh) |
CN (1) | CN1218388C (zh) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101567322B (zh) * | 2008-04-21 | 2010-11-17 | 南茂科技股份有限公司 | 芯片的封装结构及其封装方法 |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7582963B2 (en) * | 2005-03-29 | 2009-09-01 | Texas Instruments Incorporated | Vertically integrated system-in-a-package |
KR100729639B1 (ko) * | 2006-09-08 | 2007-08-10 | (주)완도해조생약마을 | 김 또는 파래를 이용한 식초 제조방법 및 그 방법에 의해제조된 식초 |
KR100854694B1 (ko) * | 2007-01-19 | 2008-08-27 | 류충현 | 홍 고추를 이용한 고추식초 제조방법 |
KR100785409B1 (ko) * | 2007-03-07 | 2007-12-13 | 남정식 | 메밀을 이용한 기능성 식초 제조방법과 그 식초 및식초음료 |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5776796A (en) * | 1994-05-19 | 1998-07-07 | Tessera, Inc. | Method of encapsulating a semiconductor package |
JP2000156435A (ja) * | 1998-06-22 | 2000-06-06 | Fujitsu Ltd | 半導体装置及びその製造方法 |
US6268650B1 (en) * | 1999-05-25 | 2001-07-31 | Micron Technology, Inc. | Semiconductor device, ball grid array connection system, and method of making |
US20030082845A1 (en) * | 2000-01-14 | 2003-05-01 | Amkor Technology, Inc. | Package for multiple integrated circuits and method of making |
US6414396B1 (en) * | 2000-01-24 | 2002-07-02 | Amkor Technology, Inc. | Package for stacked integrated circuits |
US6326700B1 (en) * | 2000-08-15 | 2001-12-04 | United Test Center, Inc. | Low profile semiconductor package and process for making the same |
-
2002
- 2002-07-10 US US10/191,071 patent/US20040009628A1/en not_active Abandoned
- 2002-07-26 JP JP2002218557A patent/JP2004063680A/ja active Pending
- 2002-09-11 CN CN021316309A patent/CN1218388C/zh not_active Expired - Fee Related
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101567322B (zh) * | 2008-04-21 | 2010-11-17 | 南茂科技股份有限公司 | 芯片的封装结构及其封装方法 |
Also Published As
Publication number | Publication date |
---|---|
JP2004063680A (ja) | 2004-02-26 |
CN1218388C (zh) | 2005-09-07 |
US20040009628A1 (en) | 2004-01-15 |
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Owner name: WEIYU SEMICONDUCTOR (HONG KONG) LTD. Free format text: FORMER OWNER: LIWEI SCIENCE AND TECHNOLOGY CO., LTD. Effective date: 20041217 |
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Address after: 000000 Hongkong Tongluowan 33 hysanavenue Lee Garden 34/F Patentee after: Advanced packaging and testing (Hongkong) Co.,Ltd. Address before: 000000 Hongkong Special Administrative Region of China Patentee before: WEIYU SEMICONDUCTOR (HONGKONG) Co.,Ltd. |
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Effective date of registration: 20111228 Address after: Jing Road 201203 Shanghai Pudong New Area Zhangjiang High Tech Park No. 669 Patentee after: ASE ASSEMBLY & TEST (SHANGHAI) Ltd. Address before: Chinese Hongkong Tongluowan 33 hysanavenue Lee Garden 34/F Patentee before: Advanced packaging and testing (Hongkong) Co.,Ltd. |
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