DE69917880T2 - Halbleiteranordnung aus vergossenem Kunststoff, Verfahren zu ihrer Herstellung, und Leiterrahmen - Google Patents
Halbleiteranordnung aus vergossenem Kunststoff, Verfahren zu ihrer Herstellung, und Leiterrahmen Download PDFInfo
- Publication number
- DE69917880T2 DE69917880T2 DE69917880T DE69917880T DE69917880T2 DE 69917880 T2 DE69917880 T2 DE 69917880T2 DE 69917880 T DE69917880 T DE 69917880T DE 69917880 T DE69917880 T DE 69917880T DE 69917880 T2 DE69917880 T2 DE 69917880T2
- Authority
- DE
- Germany
- Prior art keywords
- making
- semiconductor device
- same
- lead frame
- molded plastic
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000004519 manufacturing process Methods 0.000 title 1
- 239000002991 molded plastic Substances 0.000 title 1
- 239000004065 semiconductor Substances 0.000 title 1
Classifications
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- H—ELECTRICITY
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/565—Moulds
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- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
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Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP04604099A JP3535760B2 (ja) | 1999-02-24 | 1999-02-24 | 樹脂封止型半導体装置,その製造方法及びリードフレーム |
JP11095185A JP3007632B1 (ja) | 1999-04-01 | 1999-04-01 | 樹脂封止型半導体装置およびその製造方法 |
Publications (2)
Publication Number | Publication Date |
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DE69917880D1 DE69917880D1 (de) | 2004-07-15 |
DE69917880T2 true DE69917880T2 (de) | 2004-10-07 |
Family
ID=26386152
Family Applications (3)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69927532T Expired - Lifetime DE69927532T2 (de) | 1999-02-24 | 1999-11-04 | Halbleiteranordnung aus vergossenem Kunststoff |
DE69917880T Expired - Lifetime DE69917880T2 (de) | 1999-02-24 | 1999-11-04 | Halbleiteranordnung aus vergossenem Kunststoff, Verfahren zu ihrer Herstellung, und Leiterrahmen |
DE69932268T Expired - Lifetime DE69932268T2 (de) | 1999-02-24 | 1999-11-04 | Halbleiteranordnung aus vergossenem Kunststoff und Verfahren zu Ihrer Herstellung |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69927532T Expired - Lifetime DE69927532T2 (de) | 1999-02-24 | 1999-11-04 | Halbleiteranordnung aus vergossenem Kunststoff |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69932268T Expired - Lifetime DE69932268T2 (de) | 1999-02-24 | 1999-11-04 | Halbleiteranordnung aus vergossenem Kunststoff und Verfahren zu Ihrer Herstellung |
Country Status (4)
Country | Link |
---|---|
US (2) | US6208020B1 (de) |
EP (3) | EP1335428B1 (de) |
DE (3) | DE69927532T2 (de) |
TW (1) | TW428295B (de) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE112018003393B4 (de) | 2017-08-30 | 2023-05-04 | Hitachi Astemo, Ltd. | Verfahren zur Herstellung eines Leistungshalbleiters |
Families Citing this family (198)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20020110354A1 (en) * | 1997-01-09 | 2002-08-15 | Osamu Ikeda | Image recording and editing apparatus, and method for capturing and editing an image |
US6229200B1 (en) | 1998-06-10 | 2001-05-08 | Asat Limited | Saw-singulated leadless plastic chip carrier |
US8330270B1 (en) * | 1998-06-10 | 2012-12-11 | Utac Hong Kong Limited | Integrated circuit package having a plurality of spaced apart pad portions |
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1999
- 1999-11-03 US US09/432,216 patent/US6208020B1/en not_active Expired - Lifetime
- 1999-11-03 TW TW088119156A patent/TW428295B/zh not_active IP Right Cessation
- 1999-11-04 DE DE69927532T patent/DE69927532T2/de not_active Expired - Lifetime
- 1999-11-04 EP EP03008810A patent/EP1335428B1/de not_active Expired - Lifetime
- 1999-11-04 DE DE69917880T patent/DE69917880T2/de not_active Expired - Lifetime
- 1999-11-04 EP EP03008809A patent/EP1335427B1/de not_active Expired - Lifetime
- 1999-11-04 EP EP99121878A patent/EP1032037B1/de not_active Expired - Lifetime
- 1999-11-04 DE DE69932268T patent/DE69932268T2/de not_active Expired - Lifetime
-
2001
- 2001-01-30 US US09/771,548 patent/US6338984B2/en not_active Expired - Lifetime
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DE112018003393B4 (de) | 2017-08-30 | 2023-05-04 | Hitachi Astemo, Ltd. | Verfahren zur Herstellung eines Leistungshalbleiters |
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EP1032037A2 (de) | 2000-08-30 |
EP1335428A2 (de) | 2003-08-13 |
EP1335427A2 (de) | 2003-08-13 |
DE69917880D1 (de) | 2004-07-15 |
US6338984B2 (en) | 2002-01-15 |
EP1335427A3 (de) | 2003-10-08 |
EP1335428B1 (de) | 2006-07-05 |
EP1032037B1 (de) | 2004-06-09 |
DE69927532D1 (de) | 2006-02-09 |
EP1335427B1 (de) | 2005-09-28 |
DE69932268D1 (de) | 2006-08-17 |
EP1335428A3 (de) | 2003-10-08 |
US6208020B1 (en) | 2001-03-27 |
TW428295B (en) | 2001-04-01 |
EP1032037A3 (de) | 2001-04-25 |
DE69932268T2 (de) | 2006-11-09 |
DE69927532T2 (de) | 2006-03-16 |
US20010007780A1 (en) | 2001-07-12 |
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