DE69827058T2 - Verbindungshalbleiter-Interfacestruktur und deren Herstellungsverfahren - Google Patents

Verbindungshalbleiter-Interfacestruktur und deren Herstellungsverfahren Download PDF

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Publication number
DE69827058T2
DE69827058T2 DE69827058T DE69827058T DE69827058T2 DE 69827058 T2 DE69827058 T2 DE 69827058T2 DE 69827058 T DE69827058 T DE 69827058T DE 69827058 T DE69827058 T DE 69827058T DE 69827058 T2 DE69827058 T2 DE 69827058T2
Authority
DE
Germany
Prior art keywords
compound semiconductor
interface structure
insulator
spacer layer
gallium arsenide
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69827058T
Other languages
German (de)
English (en)
Other versions
DE69827058D1 (de
Inventor
Matthias Chandler Passlack
Jun Gilbert Wang
Jonathan K. Gilbert Abrokwah
Zhiyi Jimmy Gilbert Yu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP USA Inc
Original Assignee
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Inc filed Critical Motorola Inc
Publication of DE69827058D1 publication Critical patent/DE69827058D1/de
Application granted granted Critical
Publication of DE69827058T2 publication Critical patent/DE69827058T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H10D64/691—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator comprising metallic compounds, e.g. metal oxides or metal silicates 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/015—Manufacture or treatment of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/80—FETs having rectifying junction gate electrodes
    • H10D30/801—FETs having heterojunction gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
    • H10D64/01302—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H10D64/01332—Making the insulator
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
    • H10D64/01358—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being a Group III-V material

Landscapes

  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Recrystallisation Techniques (AREA)
  • Formation Of Insulating Films (AREA)
  • Junction Field-Effect Transistors (AREA)
DE69827058T 1997-03-04 1998-03-02 Verbindungshalbleiter-Interfacestruktur und deren Herstellungsverfahren Expired - Fee Related DE69827058T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US812952 1997-03-04
US08/812,952 US6359294B1 (en) 1997-03-04 1997-03-04 Insulator-compound semiconductor interface structure

Publications (2)

Publication Number Publication Date
DE69827058D1 DE69827058D1 (de) 2004-11-25
DE69827058T2 true DE69827058T2 (de) 2005-03-03

Family

ID=25211069

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69827058T Expired - Fee Related DE69827058T2 (de) 1997-03-04 1998-03-02 Verbindungshalbleiter-Interfacestruktur und deren Herstellungsverfahren

Country Status (4)

Country Link
US (1) US6359294B1 (https=)
EP (1) EP0863539B1 (https=)
JP (1) JP3920447B2 (https=)
DE (1) DE69827058T2 (https=)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012074689A (ja) 2010-08-31 2012-04-12 Sumitomo Chemical Co Ltd 半導体基板、絶縁ゲート型電界効果トランジスタおよび半導体基板の製造方法
KR20130105804A (ko) 2010-08-31 2013-09-26 스미또모 가가꾸 가부시키가이샤 반도체 기판 및 절연 게이트형 전계 효과 트랜지스터
CN106560928B (zh) * 2015-09-28 2019-11-08 河北大学 一种电荷俘获型存储元件及其制备工艺

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4859253A (en) * 1988-07-20 1989-08-22 International Business Machines Corporation Method for passivating a compound semiconductor surface and device having improved semiconductor-insulator interface
US5124762A (en) * 1990-12-31 1992-06-23 Honeywell Inc. Gaas heterostructure metal-insulator-semiconductor integrated circuit technology
US5334865A (en) * 1991-07-31 1994-08-02 Allied-Signal Inc. MODFET structure for threshold control
US5597768A (en) * 1996-03-21 1997-01-28 Motorola, Inc. Method of forming a Ga2 O3 dielectric layer
US5747838A (en) * 1996-11-27 1998-05-05 The Regents Of The University Of California Ultra-low phase noise GaAs MOSFETs

Also Published As

Publication number Publication date
JPH10275806A (ja) 1998-10-13
US6359294B1 (en) 2002-03-19
EP0863539A1 (en) 1998-09-09
EP0863539B1 (en) 2004-10-20
JP3920447B2 (ja) 2007-05-30
DE69827058D1 (de) 2004-11-25

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: FREESCALE SEMICONDUCTOR, INC., AUSTIN, TEX., US

8339 Ceased/non-payment of the annual fee