DE69823909D1 - Halbleiteranordnung mit einer Sperrschicht zum Verhindern von Feuchtigkeitsdurchdringung - Google Patents

Halbleiteranordnung mit einer Sperrschicht zum Verhindern von Feuchtigkeitsdurchdringung

Info

Publication number
DE69823909D1
DE69823909D1 DE69823909T DE69823909T DE69823909D1 DE 69823909 D1 DE69823909 D1 DE 69823909D1 DE 69823909 T DE69823909 T DE 69823909T DE 69823909 T DE69823909 T DE 69823909T DE 69823909 D1 DE69823909 D1 DE 69823909D1
Authority
DE
Germany
Prior art keywords
semiconductor device
barrier layer
prevent moisture
moisture penetration
penetration
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69823909T
Other languages
English (en)
Other versions
DE69823909T2 (de
Inventor
Ryuichi Okamura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Electronics Corp
Original Assignee
NEC Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Electronics Corp filed Critical NEC Electronics Corp
Publication of DE69823909D1 publication Critical patent/DE69823909D1/de
Application granted granted Critical
Publication of DE69823909T2 publication Critical patent/DE69823909T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/564—Details not otherwise provided for, e.g. protection against moisture
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/291—Oxides or nitrides or carbides, e.g. ceramics, glass
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Formation Of Insulating Films (AREA)
DE69823909T 1997-03-24 1998-03-23 Halbleiteranordnung mit einer Sperrschicht zum Verhindern von Feuchtigkeitsdurchdringung Expired - Fee Related DE69823909T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP6988897 1997-03-24
JP06988897A JP3288246B2 (ja) 1997-03-24 1997-03-24 半導体装置および半導体装置の製造方法

Publications (2)

Publication Number Publication Date
DE69823909D1 true DE69823909D1 (de) 2004-06-24
DE69823909T2 DE69823909T2 (de) 2005-06-09

Family

ID=13415730

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69823909T Expired - Fee Related DE69823909T2 (de) 1997-03-24 1998-03-23 Halbleiteranordnung mit einer Sperrschicht zum Verhindern von Feuchtigkeitsdurchdringung

Country Status (6)

Country Link
US (1) US6111320A (de)
EP (1) EP0867936B1 (de)
JP (1) JP3288246B2 (de)
KR (1) KR100304686B1 (de)
CN (1) CN1083619C (de)
DE (1) DE69823909T2 (de)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100631279B1 (ko) * 2004-12-31 2006-10-02 동부일렉트로닉스 주식회사 고전압용 트랜지스터의 제조 방법
JP2007273756A (ja) * 2006-03-31 2007-10-18 Oki Electric Ind Co Ltd 半導体装置の製造方法
CN102373471B (zh) * 2010-08-25 2014-07-23 中国印钞造币总公司 纪念币模具表面制备氮化钽涂层的工艺方法
JP6767302B2 (ja) 2017-04-14 2020-10-14 東京エレクトロン株式会社 成膜方法

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3675313A (en) * 1970-10-01 1972-07-11 Westinghouse Electric Corp Process for producing self aligned gate field effect transistor
JPS60202943A (ja) * 1984-03-28 1985-10-14 Hitachi Ltd 絶縁膜の形成方法
JP2751181B2 (ja) * 1988-02-20 1998-05-18 ソニー株式会社 半導体装置の製法
JPH03173126A (ja) * 1989-11-30 1991-07-26 Mitsubishi Electric Corp 多層膜構造の半導体装置およびその製造方法
JP2561383B2 (ja) * 1990-11-02 1996-12-04 山形日本電気株式会社 半導体集積回路装置の製造方法
JPH04186657A (ja) * 1990-11-16 1992-07-03 Sharp Corp コンタクト配線の作製方法
US5294295A (en) * 1991-10-31 1994-03-15 Vlsi Technology, Inc. Method for moisture sealing integrated circuits using silicon nitride spacer protection of oxide passivation edges
JP3236399B2 (ja) * 1993-04-02 2001-12-10 三菱電機株式会社 半導体装置の製造方法

Also Published As

Publication number Publication date
JPH10270549A (ja) 1998-10-09
DE69823909T2 (de) 2005-06-09
CN1083619C (zh) 2002-04-24
CN1194468A (zh) 1998-09-30
KR100304686B1 (ko) 2001-11-02
EP0867936B1 (de) 2004-05-19
EP0867936A3 (de) 2000-06-28
US6111320A (en) 2000-08-29
JP3288246B2 (ja) 2002-06-04
EP0867936A2 (de) 1998-09-30
KR19980079938A (ko) 1998-11-25

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee