DE69804767T2 - Sdram-taktpruefmodus - Google Patents

Sdram-taktpruefmodus

Info

Publication number
DE69804767T2
DE69804767T2 DE69804767T DE69804767T DE69804767T2 DE 69804767 T2 DE69804767 T2 DE 69804767T2 DE 69804767 T DE69804767 T DE 69804767T DE 69804767 T DE69804767 T DE 69804767T DE 69804767 T2 DE69804767 T2 DE 69804767T2
Authority
DE
Germany
Prior art keywords
clock
test
signal
enable
terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69804767T
Other languages
English (en)
Other versions
DE69804767D1 (de
Inventor
A Manning
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Micron Technology Inc
Original Assignee
Micron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Publication of DE69804767D1 publication Critical patent/DE69804767D1/de
Application granted granted Critical
Publication of DE69804767T2 publication Critical patent/DE69804767T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/14—Implementation of control logic, e.g. test mode decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 

Landscapes

  • Tests Of Electronic Circuits (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
DE69804767T 1997-01-22 1998-01-21 Sdram-taktpruefmodus Expired - Lifetime DE69804767T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/787,149 US5757705A (en) 1997-01-22 1997-01-22 SDRAM clocking test mode
PCT/US1998/001219 WO1998032132A1 (en) 1997-01-22 1998-01-21 Sdram clocking test mode

Publications (2)

Publication Number Publication Date
DE69804767D1 DE69804767D1 (de) 2002-05-16
DE69804767T2 true DE69804767T2 (de) 2002-10-17

Family

ID=25140568

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69804767T Expired - Lifetime DE69804767T2 (de) 1997-01-22 1998-01-21 Sdram-taktpruefmodus

Country Status (8)

Country Link
US (1) US5757705A (de)
EP (1) EP0954866B1 (de)
JP (1) JP3697267B2 (de)
KR (1) KR100508196B1 (de)
AU (1) AU5963198A (de)
DE (1) DE69804767T2 (de)
TW (1) TW422990B (de)
WO (1) WO1998032132A1 (de)

Families Citing this family (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3301874B2 (ja) * 1994-12-19 2002-07-15 松下電器産業株式会社 半導体装置及びその検査方法
US5991850A (en) * 1996-08-15 1999-11-23 Micron Technology, Inc. Synchronous DRAM modules including multiple clock out signals for increasing processing speed
US5933379A (en) * 1996-11-18 1999-08-03 Samsung Electronics, Co., Ltd. Method and circuit for testing a semiconductor memory device operating at high frequency
US6104209A (en) 1998-08-27 2000-08-15 Micron Technology, Inc. Low skew differential receiver with disable feature
DE19711097C2 (de) * 1997-03-17 2000-04-06 Siemens Ag Integrierte Schaltung mit einem Speicher und einer Prüfschaltung
JP3262033B2 (ja) * 1997-07-31 2002-03-04 日本電気株式会社 半導体記憶装置
US5995426A (en) * 1997-11-04 1999-11-30 Micron Technology, Inc. Testing parameters of an electronic device
JPH11219600A (ja) * 1998-02-03 1999-08-10 Mitsubishi Electric Corp 半導体集積回路装置
US6212482B1 (en) * 1998-03-06 2001-04-03 Micron Technology, Inc. Circuit and method for specifying performance parameters in integrated circuits
KR100280481B1 (ko) * 1998-05-13 2001-02-01 김영환 엠씨유의테스트모드설정회로
US6178532B1 (en) 1998-06-11 2001-01-23 Micron Technology, Inc. On-chip circuit and method for testing memory devices
US6489819B1 (en) * 1998-10-27 2002-12-03 Mitsubishi Denki Kabushiki Kaisha Clock synchronous semiconductor memory device allowing testing by low speed tester
US6141276A (en) * 1999-09-02 2000-10-31 Micron Technology, Inc. Apparatus and method for increasing test flexibility of a memory device
JP2001291400A (ja) * 2000-04-07 2001-10-19 Mitsubishi Electric Corp 半導体メモリ用のテスト回路
US6275446B1 (en) 2000-08-25 2001-08-14 Micron Technology, Inc. Clock generation circuits and methods
DE10113458C2 (de) * 2001-03-19 2003-03-20 Infineon Technologies Ag Testschaltung
US6404250B1 (en) * 2001-03-28 2002-06-11 Infineon Technologies Richmond, Lp On-chip circuits for high speed memory testing with a slow memory tester
KR100400311B1 (ko) 2001-06-29 2003-10-01 주식회사 하이닉스반도체 반도체 메모리 소자의 신호 지연 제어 장치
ITRM20010556A1 (it) * 2001-09-12 2003-03-12 Micron Technology Inc Decodificatore per decodificare i comandi di commutazione a modo di test di circuiti integrati.
JP2003203497A (ja) * 2002-01-08 2003-07-18 Mitsubishi Electric Corp 半導体記憶装置
US7026646B2 (en) * 2002-06-20 2006-04-11 Micron Technology, Inc. Isolation circuit
US6967348B2 (en) * 2002-06-20 2005-11-22 Micron Technology, Inc. Signal sharing circuit with microelectric die isolation features
US7885129B2 (en) * 2008-05-28 2011-02-08 Macronix International Co., Ltd Memory chip and method for operating the same
JP2010182359A (ja) 2009-02-04 2010-08-19 Elpida Memory Inc 半導体記憶装置及びそのテスト方法
KR20120078998A (ko) * 2011-01-03 2012-07-11 에스케이하이닉스 주식회사 비휘발성 메모리 장치
CN114966345B (zh) * 2022-05-31 2023-07-21 北京泰岳天成科技有限公司 一种高频电流局放信号采样装置及方法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06242188A (ja) * 1993-02-16 1994-09-02 Mitsubishi Electric Corp 半導体集積回路及びそのテスト方法
EP0640986A1 (de) * 1993-08-26 1995-03-01 Siemens Aktiengesellschaft Halbleiterspeicheranordnung und Verfahren zum Testen dieser Halbleiterspeicheranordnung
US5450364A (en) * 1994-01-31 1995-09-12 Texas Instruments Incorporated Method and apparatus for production testing of self-refresh operations and a particular application to synchronous memory devices
US5386385A (en) * 1994-01-31 1995-01-31 Texas Instruments Inc. Method and apparatus for preventing invalid operating modes and an application to synchronous memory devices

Also Published As

Publication number Publication date
EP0954866A1 (de) 1999-11-10
DE69804767D1 (de) 2002-05-16
JP2001509937A (ja) 2001-07-24
WO1998032132A1 (en) 1998-07-23
EP0954866B1 (de) 2002-04-10
JP3697267B2 (ja) 2005-09-21
AU5963198A (en) 1998-08-07
KR100508196B1 (ko) 2005-08-17
KR20000070402A (ko) 2000-11-25
US5757705A (en) 1998-05-26
TW422990B (en) 2001-02-21

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Legal Events

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