DE69627999D1 - Schaltbarer Bustreiberabschlusswiderstand - Google Patents

Schaltbarer Bustreiberabschlusswiderstand

Info

Publication number
DE69627999D1
DE69627999D1 DE69627999T DE69627999T DE69627999D1 DE 69627999 D1 DE69627999 D1 DE 69627999D1 DE 69627999 T DE69627999 T DE 69627999T DE 69627999 T DE69627999 T DE 69627999T DE 69627999 D1 DE69627999 D1 DE 69627999D1
Authority
DE
Germany
Prior art keywords
bus driver
termination resistor
driver termination
switchable bus
switchable
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69627999T
Other languages
English (en)
Other versions
DE69627999T2 (de
Inventor
Masao Taguchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Semiconductor Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Publication of DE69627999D1 publication Critical patent/DE69627999D1/de
Application granted granted Critical
Publication of DE69627999T2 publication Critical patent/DE69627999T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1057—Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G06F13/4072—Drivers or receivers
    • G06F13/4077—Precharging or discharging
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G06F13/4086—Bus impedance matching, e.g. termination
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0008—Arrangements for reducing power consumption
    • H03K19/0016—Arrangements for reducing power consumption by using a control or a clock signal, e.g. in order to apply power supply
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/017545—Coupling arrangements; Impedance matching circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018585—Coupling arrangements; Interface arrangements using field effect transistors only programmable
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/22—Control and timing of internal memory operations
    • G11C2207/2227—Standby or low power modes
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
DE69627999T 1996-07-03 1996-11-20 Schaltbarer Bustreiberabschlusswiderstand Expired - Lifetime DE69627999T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8173910A JPH1020974A (ja) 1996-07-03 1996-07-03 バス構造及び入出力バッファ

Publications (2)

Publication Number Publication Date
DE69627999D1 true DE69627999D1 (de) 2003-06-12
DE69627999T2 DE69627999T2 (de) 2003-11-27

Family

ID=15969353

Family Applications (2)

Application Number Title Priority Date Filing Date
DE69627999T Expired - Lifetime DE69627999T2 (de) 1996-07-03 1996-11-20 Schaltbarer Bustreiberabschlusswiderstand
DE69638067T Expired - Lifetime DE69638067D1 (de) 1996-07-03 1996-11-20 Rechnerbuskonfiguration und Eingangs/Ausgangstreiber

Family Applications After (1)

Application Number Title Priority Date Filing Date
DE69638067T Expired - Lifetime DE69638067D1 (de) 1996-07-03 1996-11-20 Rechnerbuskonfiguration und Eingangs/Ausgangstreiber

Country Status (6)

Country Link
US (3) US5949252A (de)
EP (5) EP1308850A3 (de)
JP (1) JPH1020974A (de)
KR (1) KR100212597B1 (de)
DE (2) DE69627999T2 (de)
TW (1) TW325539B (de)

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US7365570B2 (en) * 2005-05-25 2008-04-29 Micron Technology, Inc. Pseudo-differential output driver with high immunity to noise and jitter
US7355450B1 (en) 2005-05-27 2008-04-08 Altera Corporation Differential input buffers for low power supply
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JP4524662B2 (ja) 2005-10-21 2010-08-18 エルピーダメモリ株式会社 半導体メモリチップ
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Also Published As

Publication number Publication date
EP1308848A3 (de) 2005-09-14
EP0818734B1 (de) 2003-05-07
US5949252A (en) 1999-09-07
TW325539B (en) 1998-01-21
EP1308847A2 (de) 2003-05-07
EP1308850A2 (de) 2003-05-07
DE69627999T2 (de) 2003-11-27
EP1308848A2 (de) 2003-05-07
EP0818734A3 (de) 1998-05-06
EP1308849A2 (de) 2003-05-07
KR980010746A (ko) 1998-04-30
EP0818734A2 (de) 1998-01-14
US6154047A (en) 2000-11-28
EP1308849A3 (de) 2005-09-14
US6480030B1 (en) 2002-11-12
KR100212597B1 (ko) 1999-08-02
EP1308847A3 (de) 2005-09-14
JPH1020974A (ja) 1998-01-23
DE69638067D1 (de) 2009-12-17
EP1308850A3 (de) 2005-09-14
EP1308847B1 (de) 2009-11-04

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: FUJITSU MICROELECTRONICS LTD., TOKYO, JP

8327 Change in the person/name/address of the patent owner

Owner name: FUJITSU SEMICONDUCTOR LTD., YOKOHAMA, KANAGAWA, JP

8328 Change in the person/name/address of the agent

Representative=s name: SEEGER SEEGER LINDNER PARTNERSCHAFT PATENTANWAELTE