TW325539B - Bus configuration and input/output buffer - Google Patents

Bus configuration and input/output buffer

Info

Publication number
TW325539B
TW325539B TW085114586A TW85114586A TW325539B TW 325539 B TW325539 B TW 325539B TW 085114586 A TW085114586 A TW 085114586A TW 85114586 A TW85114586 A TW 85114586A TW 325539 B TW325539 B TW 325539B
Authority
TW
Taiwan
Prior art keywords
bus
input
output buffer
bus configuration
termination
Prior art date
Application number
TW085114586A
Other languages
English (en)
Inventor
Masao Taguchi
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Application granted granted Critical
Publication of TW325539B publication Critical patent/TW325539B/zh

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1057—Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G06F13/4072—Drivers or receivers
    • G06F13/4077—Precharging or discharging
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G06F13/4086—Bus impedance matching, e.g. termination
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0008—Arrangements for reducing power consumption
    • H03K19/0016—Arrangements for reducing power consumption by using a control or a clock signal, e.g. in order to apply power supply
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/017545—Coupling arrangements; Impedance matching circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018585—Coupling arrangements; Interface arrangements using field effect transistors only programmable
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/22—Control and timing of internal memory operations
    • G11C2207/2227—Standby or low power modes
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
TW085114586A 1996-07-03 1996-11-26 Bus configuration and input/output buffer TW325539B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8173910A JPH1020974A (ja) 1996-07-03 1996-07-03 バス構造及び入出力バッファ

Publications (1)

Publication Number Publication Date
TW325539B true TW325539B (en) 1998-01-21

Family

ID=15969353

Family Applications (1)

Application Number Title Priority Date Filing Date
TW085114586A TW325539B (en) 1996-07-03 1996-11-26 Bus configuration and input/output buffer

Country Status (6)

Country Link
US (3) US5949252A (zh)
EP (5) EP1308850A3 (zh)
JP (1) JPH1020974A (zh)
KR (1) KR100212597B1 (zh)
DE (2) DE69627999T2 (zh)
TW (1) TW325539B (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI803059B (zh) * 2021-10-01 2023-05-21 南亞科技股份有限公司 接收器電路、記憶體裝置以及使用其的操作方法

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US11830535B2 (en) 2021-10-01 2023-11-28 Nanya Technology Corporation Receiver circuit, memory device and operation method using the same

Also Published As

Publication number Publication date
EP1308848A3 (en) 2005-09-14
DE69627999D1 (de) 2003-06-12
EP0818734B1 (en) 2003-05-07
US5949252A (en) 1999-09-07
EP1308847A2 (en) 2003-05-07
EP1308850A2 (en) 2003-05-07
DE69627999T2 (de) 2003-11-27
EP1308848A2 (en) 2003-05-07
EP0818734A3 (en) 1998-05-06
EP1308849A2 (en) 2003-05-07
KR980010746A (ko) 1998-04-30
EP0818734A2 (en) 1998-01-14
US6154047A (en) 2000-11-28
EP1308849A3 (en) 2005-09-14
US6480030B1 (en) 2002-11-12
KR100212597B1 (ko) 1999-08-02
EP1308847A3 (en) 2005-09-14
JPH1020974A (ja) 1998-01-23
DE69638067D1 (de) 2009-12-17
EP1308850A3 (en) 2005-09-14
EP1308847B1 (en) 2009-11-04

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