DE69619918T2 - Halbleiterspeicheranordnung mit erweitertem Bereich eines verriegelbaren Eingangssignals - Google Patents
Halbleiterspeicheranordnung mit erweitertem Bereich eines verriegelbaren EingangssignalsInfo
- Publication number
- DE69619918T2 DE69619918T2 DE69619918T DE69619918T DE69619918T2 DE 69619918 T2 DE69619918 T2 DE 69619918T2 DE 69619918 T DE69619918 T DE 69619918T DE 69619918 T DE69619918 T DE 69619918T DE 69619918 T2 DE69619918 T2 DE 69619918T2
- Authority
- DE
- Germany
- Prior art keywords
- input
- latch
- signal
- clock signal
- mode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 title claims description 26
- 230000004044 response Effects 0.000 claims description 42
- 238000000034 method Methods 0.000 claims description 15
- 230000003111 delayed effect Effects 0.000 claims description 9
- 230000003139 buffering effect Effects 0.000 claims description 4
- 230000001360 synchronised effect Effects 0.000 description 33
- 238000010586 diagram Methods 0.000 description 17
- 230000004913 activation Effects 0.000 description 9
- 102100035606 Beta-casein Human genes 0.000 description 6
- 101000947120 Homo sapiens Beta-casein Proteins 0.000 description 6
- 101100060388 Arabidopsis thaliana CLT1 gene Proteins 0.000 description 4
- 101100060390 Arabidopsis thaliana CLT3 gene Proteins 0.000 description 4
- 101100113686 Clitocybe nebularis clt4 gene Proteins 0.000 description 4
- 230000000630 rising effect Effects 0.000 description 3
- 230000005540 biological transmission Effects 0.000 description 2
- 101150006280 clt2 gene Proteins 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 230000007704 transition Effects 0.000 description 2
- 230000001133 acceleration Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
- G11C7/1093—Input synchronization
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Dram (AREA)
- Static Random-Access Memory (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7273616A JP2907081B2 (ja) | 1995-09-26 | 1995-09-26 | 半導体記憶装置 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| DE69619918D1 DE69619918D1 (de) | 2002-04-25 |
| DE69619918T2 true DE69619918T2 (de) | 2002-09-19 |
Family
ID=17530219
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| DE69619918T Expired - Lifetime DE69619918T2 (de) | 1995-09-26 | 1996-09-04 | Halbleiterspeicheranordnung mit erweitertem Bereich eines verriegelbaren Eingangssignals |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US5748553A (esLanguage) |
| EP (1) | EP0766251B1 (esLanguage) |
| JP (1) | JP2907081B2 (esLanguage) |
| KR (1) | KR100222812B1 (esLanguage) |
| DE (1) | DE69619918T2 (esLanguage) |
| TW (1) | TW318934B (esLanguage) |
Families Citing this family (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2988392B2 (ja) * | 1996-08-09 | 1999-12-13 | 日本電気株式会社 | 半導体メモリ集積回路 |
| JPH10162573A (ja) * | 1996-11-29 | 1998-06-19 | Nec Corp | 半導体記憶装置 |
| KR100230407B1 (ko) * | 1997-02-17 | 1999-11-15 | 윤종용 | 반도체장치의 클럭 발생회로 및 클럭발생방법 |
| US5912846A (en) * | 1997-02-28 | 1999-06-15 | Ramtron International Corporation | Serial ferroelectric random access memory architecture to equalize column accesses and improve data retention reliability by mitigating imprint effects |
| JP4059951B2 (ja) * | 1997-04-11 | 2008-03-12 | 株式会社ルネサステクノロジ | 半導体記憶装置 |
| US5848022A (en) * | 1997-05-02 | 1998-12-08 | Integrated Silicon Solution Inc. | Address enable circuit in synchronous SRAM |
| US5930182A (en) * | 1997-08-22 | 1999-07-27 | Micron Technology, Inc. | Adjustable delay circuit for setting the speed grade of a semiconductor device |
| DE19929121B4 (de) * | 1998-06-30 | 2013-02-28 | Fujitsu Semiconductor Ltd. | Integrierte Halbleiterschaltung |
| US6279071B1 (en) * | 1998-07-07 | 2001-08-21 | Mitsubishi Electric And Electronics Usa, Inc. | System and method for column access in random access memories |
| JP4034886B2 (ja) * | 1998-10-13 | 2008-01-16 | 富士通株式会社 | 半導体装置 |
| US20050132128A1 (en) * | 2003-12-15 | 2005-06-16 | Jin-Yub Lee | Flash memory device and flash memory system including buffer memory |
| US9171600B2 (en) | 2013-09-04 | 2015-10-27 | Naoki Shimizu | Semiconductor memory device |
Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR960003526B1 (ko) * | 1992-10-02 | 1996-03-14 | 삼성전자주식회사 | 반도체 메모리장치 |
| US4763303A (en) * | 1986-02-24 | 1988-08-09 | Motorola, Inc. | Write-drive data controller |
| JPS63253592A (ja) * | 1987-04-10 | 1988-10-20 | Nec Corp | 集積回路 |
| JP2830594B2 (ja) * | 1992-03-26 | 1998-12-02 | 日本電気株式会社 | 半導体メモリ装置 |
| JPH0737389A (ja) * | 1993-07-20 | 1995-02-07 | Mitsubishi Electric Corp | 半導体装置 |
| US5493530A (en) * | 1993-08-26 | 1996-02-20 | Paradigm Technology, Inc. | Ram with pre-input register logic |
| JP2697634B2 (ja) * | 1994-09-30 | 1998-01-14 | 日本電気株式会社 | 同期型半導体記憶装置 |
| JP2697633B2 (ja) * | 1994-09-30 | 1998-01-14 | 日本電気株式会社 | 同期型半導体記憶装置 |
-
1995
- 1995-09-26 JP JP7273616A patent/JP2907081B2/ja not_active Expired - Lifetime
-
1996
- 1996-08-28 TW TW085110461A patent/TW318934B/zh not_active IP Right Cessation
- 1996-09-04 DE DE69619918T patent/DE69619918T2/de not_active Expired - Lifetime
- 1996-09-04 EP EP96114143A patent/EP0766251B1/en not_active Expired - Lifetime
- 1996-09-12 US US08/712,875 patent/US5748553A/en not_active Expired - Lifetime
- 1996-09-23 KR KR1019960041591A patent/KR100222812B1/ko not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| EP0766251A2 (en) | 1997-04-02 |
| EP0766251B1 (en) | 2002-03-20 |
| KR970017629A (ko) | 1997-04-30 |
| JP2907081B2 (ja) | 1999-06-21 |
| EP0766251A3 (en) | 1999-09-15 |
| TW318934B (esLanguage) | 1997-11-01 |
| US5748553A (en) | 1998-05-05 |
| JPH0991956A (ja) | 1997-04-04 |
| KR100222812B1 (ko) | 1999-10-01 |
| DE69619918D1 (de) | 2002-04-25 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| 8364 | No opposition during term of opposition | ||
| 8327 | Change in the person/name/address of the patent owner |
Owner name: NEC CORP., TOKIO/TOKYO, JP Owner name: NEC ELECTRONICS CORP., KAWASAKI, KANAGAWA, JP |
|
| 8327 | Change in the person/name/address of the patent owner |
Owner name: ELPIDA MEMORY, INC., TOKYO, JP |