DE69531093D1 - Lese- und Wiederherstellungsverfahren eines Mehrzustand-DRAM-Speichers - Google Patents
Lese- und Wiederherstellungsverfahren eines Mehrzustand-DRAM-SpeichersInfo
- Publication number
- DE69531093D1 DE69531093D1 DE69531093T DE69531093T DE69531093D1 DE 69531093 D1 DE69531093 D1 DE 69531093D1 DE 69531093 T DE69531093 T DE 69531093T DE 69531093 T DE69531093 T DE 69531093T DE 69531093 D1 DE69531093 D1 DE 69531093D1
- Authority
- DE
- Germany
- Prior art keywords
- recovery method
- dram memory
- memory reading
- state dram
- state
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3418—Disturbance prevention or evaluation; Refreshing of disturbed memory data
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C11/565—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using capacitive charge storage elements
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3418—Disturbance prevention or evaluation; Refreshing of disturbed memory data
- G11C16/3431—Circuits or methods to detect disturbed nonvolatile memory cells, e.g. which still read as programmed but with threshold less than the program verify threshold or read as erased but with threshold greater than the erase verify threshold, and to reverse the disturbance via a refreshing programming or erasing step
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/24—Bit-line control circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/18—Bit line organisation; Bit line lay-out
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Dram (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/366,921 US5532955A (en) | 1994-12-30 | 1994-12-30 | Method of multilevel dram sense and restore |
US366921 | 1994-12-30 |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69531093D1 true DE69531093D1 (de) | 2003-07-24 |
DE69531093T2 DE69531093T2 (de) | 2004-05-06 |
Family
ID=23445168
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69531093T Expired - Lifetime DE69531093T2 (de) | 1994-12-30 | 1995-12-28 | Lese- und Wiederherstellungsverfahren eines Mehrzustand-DRAM-Speichers |
Country Status (4)
Country | Link |
---|---|
US (2) | US5532955A (de) |
EP (1) | EP0720176B1 (de) |
JP (1) | JP3771617B2 (de) |
DE (1) | DE69531093T2 (de) |
Families Citing this family (42)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
USRE40075E1 (en) * | 1992-07-22 | 2008-02-19 | Mosaid Technologies, Incorporated | Method of multi-level storage in DRAM and apparatus thereof |
US5532955A (en) * | 1994-12-30 | 1996-07-02 | Mosaid Technologies Incorporated | Method of multilevel dram sense and restore |
KR0166046B1 (ko) * | 1995-10-06 | 1999-02-01 | 김주용 | 계층적 비트라인 구조를 갖는 반도체 메모리 장치 |
US5684736A (en) * | 1996-06-17 | 1997-11-04 | Nuram Technology, Inc. | Multilevel memory cell sense amplifier system |
US6857099B1 (en) * | 1996-09-18 | 2005-02-15 | Nippon Steel Corporation | Multilevel semiconductor memory, write/read method thereto/therefrom and storage medium storing write/read program |
US5982659A (en) * | 1996-12-23 | 1999-11-09 | Lsi Logic Corporation | Memory cell capable of storing more than two logic states by using different via resistances |
US5784328A (en) * | 1996-12-23 | 1998-07-21 | Lsi Logic Corporation | Memory system including an on-chip temperature sensor for regulating the refresh rate of a DRAM array |
US5847990A (en) * | 1996-12-23 | 1998-12-08 | Lsi Logic Corporation | Ram cell capable of storing 3 logic states |
US5761110A (en) * | 1996-12-23 | 1998-06-02 | Lsi Logic Corporation | Memory cell capable of storing more than two logic states by using programmable resistances |
US5808932A (en) * | 1996-12-23 | 1998-09-15 | Lsi Logic Corporation | Memory system which enables storage and retrieval of more than two states in a memory cell |
US5771187A (en) * | 1996-12-23 | 1998-06-23 | Lsi Logic Corporation | Multiple level storage DRAM cell |
US5915167A (en) * | 1997-04-04 | 1999-06-22 | Elm Technology Corporation | Three dimensional structure memory |
US5995431A (en) * | 1997-06-11 | 1999-11-30 | Texas Instruments Incorporated | Bit line precharge circuit with reduced standby current |
US5901078A (en) | 1997-06-19 | 1999-05-04 | Micron Technology, Inc. | Variable voltage isolation gate and method |
US6554705B1 (en) | 1997-08-22 | 2003-04-29 | Blake Cumbers | Passive biometric customer identification and tracking system |
CA2217359C (en) * | 1997-09-30 | 2005-04-12 | Mosaid Technologies Incorporated | Method for multilevel dram sensing |
US5956350A (en) * | 1997-10-27 | 1999-09-21 | Lsi Logic Corporation | Built in self repair for DRAMs using on-chip temperature sensing and heating |
EP0920029A3 (de) * | 1997-12-01 | 1999-07-14 | Texas Instruments Incorporated | RAM-Speicher mit mehreren Zuständen |
US6279133B1 (en) | 1997-12-31 | 2001-08-21 | Kawasaki Steel Corporation | Method and apparatus for significantly improving the reliability of multilevel memory architecture |
US5917748A (en) * | 1998-03-17 | 1999-06-29 | Vanguard International Semiconductor Corporation | Multi-level DRAM sensing scheme |
US5909404A (en) * | 1998-03-27 | 1999-06-01 | Lsi Logic Corporation | Refresh sampling built-in self test and repair circuit |
US6137739A (en) * | 1998-06-29 | 2000-10-24 | Hyundai Electronics Industries Co., Ltd. | Multilevel sensing circuit and method thereof |
CA2273122A1 (en) | 1999-05-26 | 2000-11-26 | Gershom Birk | Multilevel dram with local reference generation |
JP3415502B2 (ja) * | 1999-07-30 | 2003-06-09 | Necエレクトロニクス株式会社 | 半導体記憶装置 |
US6292395B1 (en) | 1999-12-30 | 2001-09-18 | Macronix International Co., Ltd. | Source and drain sensing |
US6901007B2 (en) * | 2001-01-11 | 2005-05-31 | Micron Technology, Inc. | Memory device with multi-level storage cells and apparatuses, systems and methods including same |
US6587372B2 (en) * | 2001-01-11 | 2003-07-01 | Micron Technology, Inc. | Memory device with multi-level storage cells and apparatuses, systems and methods including same |
US7209245B2 (en) * | 2001-09-20 | 2007-04-24 | Sharp Laboratories Of America, Inc. | Printing systems, softwares, and methods for user characterization of unknown printer media |
US6940772B1 (en) | 2002-03-18 | 2005-09-06 | T-Ram, Inc | Reference cells for TCCT based memory cells |
US7123508B1 (en) | 2002-03-18 | 2006-10-17 | T-Ram, Inc. | Reference cells for TCCT based memory cells |
US20030235089A1 (en) * | 2002-04-02 | 2003-12-25 | Gerhard Mueller | Memory array with diagonal bitlines |
KR100512168B1 (ko) * | 2002-09-11 | 2005-09-02 | 삼성전자주식회사 | 미소 전압차를 감지하는 감지증폭기 및 감지 증폭 방법 |
JP4084149B2 (ja) * | 2002-09-13 | 2008-04-30 | 富士通株式会社 | 半導体記憶装置 |
US7936829B2 (en) * | 2004-10-22 | 2011-05-03 | Lsi Corporation | Driving multiple consecutive bits in a serial data stream at multiple voltage levels |
US8773925B2 (en) | 2010-02-23 | 2014-07-08 | Rambus Inc. | Multilevel DRAM |
US8345469B2 (en) | 2010-09-16 | 2013-01-01 | Freescale Semiconductor, Inc. | Static random access memory (SRAM) having bit cells accessible by separate read and write paths |
US9111638B2 (en) | 2012-07-13 | 2015-08-18 | Freescale Semiconductor, Inc. | SRAM bit cell with reduced bit line pre-charge voltage |
KR20160074826A (ko) | 2014-12-18 | 2016-06-29 | 삼성전자주식회사 | 반도체 장치 |
US10652032B2 (en) * | 2017-06-20 | 2020-05-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Device signature generation |
KR20190073102A (ko) | 2017-12-18 | 2019-06-26 | 삼성전자주식회사 | 비트 라인 감지 증폭기, 반도체 메모리 장치, 그리고 그것의 멀티 비트 데이터의 센싱 방법 |
US10667621B2 (en) * | 2018-04-19 | 2020-06-02 | Micron Technology, Inc. | Multi-stage memory sensing |
US10706911B1 (en) | 2018-10-10 | 2020-07-07 | Samsung Electronics Co., Ltd. | Sense amplifier for sensing multi-level cell and memory device including the sense amplifier |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4287570A (en) * | 1979-06-01 | 1981-09-01 | Intel Corporation | Multiple bit read-only memory cell and its sense amplifier |
US4415992A (en) * | 1981-02-25 | 1983-11-15 | Motorola, Inc. | Memory system having memory cells capable of storing more than two states |
JPS59203298A (ja) * | 1983-05-04 | 1984-11-17 | Nec Corp | 半導体メモリ |
DE3485595D1 (de) * | 1983-12-23 | 1992-04-23 | Hitachi Ltd | Halbleiterspeicher mit einer speicherstruktur mit vielfachen pegeln. |
US4771404A (en) * | 1984-09-05 | 1988-09-13 | Nippon Telegraph And Telephone Corporation | Memory device employing multilevel storage circuits |
JP2618938B2 (ja) * | 1987-11-25 | 1997-06-11 | 株式会社東芝 | 半導体記憶装置 |
US5293563A (en) * | 1988-12-29 | 1994-03-08 | Sharp Kabushiki Kaisha | Multi-level memory cell with increased read-out margin |
JP2719237B2 (ja) * | 1990-12-20 | 1998-02-25 | シャープ株式会社 | ダイナミック型半導体記憶装置 |
US5283761A (en) * | 1992-07-22 | 1994-02-01 | Mosaid Technologies Incorporated | Method of multi-level storage in DRAM |
JPH07114792A (ja) * | 1993-10-19 | 1995-05-02 | Mitsubishi Electric Corp | 半導体記憶装置 |
JP3237971B2 (ja) * | 1993-09-02 | 2001-12-10 | 株式会社東芝 | 半導体記憶装置 |
US5532955A (en) * | 1994-12-30 | 1996-07-02 | Mosaid Technologies Incorporated | Method of multilevel dram sense and restore |
-
1994
- 1994-12-30 US US08/366,921 patent/US5532955A/en not_active Expired - Lifetime
-
1995
- 1995-12-28 DE DE69531093T patent/DE69531093T2/de not_active Expired - Lifetime
- 1995-12-28 EP EP95309490A patent/EP0720176B1/de not_active Expired - Lifetime
- 1995-12-29 JP JP35293295A patent/JP3771617B2/ja not_active Expired - Lifetime
-
1996
- 1996-01-11 US US08/584,887 patent/US5612912A/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
US5612912A (en) | 1997-03-18 |
EP0720176A3 (de) | 1998-01-14 |
EP0720176A2 (de) | 1996-07-03 |
DE69531093T2 (de) | 2004-05-06 |
US5532955A (en) | 1996-07-02 |
JPH08315568A (ja) | 1996-11-29 |
JP3771617B2 (ja) | 2006-04-26 |
EP0720176B1 (de) | 2003-06-18 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition |